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1 | /* linux/arch/arm/plat-s3c/pm.c |
2 | * | |
3 | * Copyright 2008 Openmoko, Inc. | |
ccae941e | 4 | * Copyright 2004-2008 Simtec Electronics |
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5 | * Ben Dooks <ben@simtec.co.uk> |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * S3C common power management (suspend to ram) support. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/suspend.h> | |
17 | #include <linux/errno.h> | |
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18 | #include <linux/delay.h> |
19 | #include <linux/serial_core.h> | |
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20 | #include <linux/io.h> |
21 | ||
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22 | #include <asm/cacheflush.h> |
23 | #include <mach/hardware.h> | |
bd117bd1 | 24 | #include <mach/map.h> |
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25 | |
26 | #include <plat/regs-serial.h> | |
27 | #include <mach/regs-clock.h> | |
2261e0e6 | 28 | #include <mach/regs-irq.h> |
56b34426 | 29 | #include <asm/irq.h> |
2261e0e6 | 30 | |
6419711a | 31 | #include <plat/pm.h> |
431fb7df | 32 | #include <mach/pm-core.h> |
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33 | |
34 | /* for external use */ | |
35 | ||
36 | unsigned long s3c_pm_flags; | |
37 | ||
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38 | /* Debug code: |
39 | * | |
40 | * This code supports debug output to the low level UARTs for use on | |
41 | * resume before the console layer is available. | |
42 | */ | |
43 | ||
8005745d | 44 | #ifdef CONFIG_SAMSUNG_PM_DEBUG |
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45 | extern void printascii(const char *); |
46 | ||
47 | void s3c_pm_dbg(const char *fmt, ...) | |
48 | { | |
49 | va_list va; | |
50 | char buff[256]; | |
51 | ||
52 | va_start(va, fmt); | |
53 | vsprintf(buff, fmt, va); | |
54 | va_end(va); | |
55 | ||
56 | printascii(buff); | |
57 | } | |
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58 | |
59 | static inline void s3c_pm_debug_init(void) | |
60 | { | |
61 | /* restart uart clocks so we can use them to output */ | |
62 | s3c_pm_debug_init_uart(); | |
63 | } | |
64 | ||
65 | #else | |
66 | #define s3c_pm_debug_init() do { } while(0) | |
67 | ||
8005745d | 68 | #endif /* CONFIG_SAMSUNG_PM_DEBUG */ |
6419711a | 69 | |
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70 | /* Save the UART configurations if we are configured for debug. */ |
71 | ||
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72 | unsigned char pm_uart_udivslot; |
73 | ||
8005745d | 74 | #ifdef CONFIG_SAMSUNG_PM_DEBUG |
2261e0e6 | 75 | |
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76 | struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; |
77 | ||
78 | static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) | |
79 | { | |
80 | void __iomem *regs = S3C_VA_UARTx(uart); | |
81 | ||
82 | save->ulcon = __raw_readl(regs + S3C2410_ULCON); | |
83 | save->ucon = __raw_readl(regs + S3C2410_UCON); | |
84 | save->ufcon = __raw_readl(regs + S3C2410_UFCON); | |
85 | save->umcon = __raw_readl(regs + S3C2410_UMCON); | |
86 | save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); | |
57699e9a | 87 | |
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88 | if (pm_uart_udivslot) |
89 | save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); | |
90 | ||
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91 | S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n", |
92 | uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv); | |
d2b07fe2 | 93 | } |
2261e0e6 | 94 | |
d2b07fe2 | 95 | static void s3c_pm_save_uarts(void) |
2261e0e6 | 96 | { |
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97 | struct pm_uart_save *save = uart_save; |
98 | unsigned int uart; | |
99 | ||
100 | for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++) | |
101 | s3c_pm_save_uart(uart, save); | |
102 | } | |
103 | ||
104 | static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save) | |
105 | { | |
106 | void __iomem *regs = S3C_VA_UARTx(uart); | |
107 | ||
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108 | s3c_pm_arch_update_uart(regs, save); |
109 | ||
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110 | __raw_writel(save->ulcon, regs + S3C2410_ULCON); |
111 | __raw_writel(save->ucon, regs + S3C2410_UCON); | |
112 | __raw_writel(save->ufcon, regs + S3C2410_UFCON); | |
113 | __raw_writel(save->umcon, regs + S3C2410_UMCON); | |
114 | __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); | |
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115 | |
116 | if (pm_uart_udivslot) | |
117 | __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT); | |
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118 | } |
119 | ||
d2b07fe2 | 120 | static void s3c_pm_restore_uarts(void) |
2261e0e6 | 121 | { |
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122 | struct pm_uart_save *save = uart_save; |
123 | unsigned int uart; | |
124 | ||
125 | for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++) | |
126 | s3c_pm_restore_uart(uart, save); | |
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127 | } |
128 | #else | |
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129 | static void s3c_pm_save_uarts(void) { } |
130 | static void s3c_pm_restore_uarts(void) { } | |
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131 | #endif |
132 | ||
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133 | /* The IRQ ext-int code goes here, it is too small to currently bother |
134 | * with its own file. */ | |
135 | ||
136 | unsigned long s3c_irqwake_intmask = 0xffffffffL; | |
137 | unsigned long s3c_irqwake_eintmask = 0xffffffffL; | |
138 | ||
f5aeffb7 | 139 | int s3c_irqext_wake(struct irq_data *data, unsigned int state) |
56b34426 | 140 | { |
f5aeffb7 | 141 | unsigned long bit = 1L << IRQ_EINT_BIT(data->irq); |
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142 | |
143 | if (!(s3c_irqwake_eintallow & bit)) | |
144 | return -ENOENT; | |
145 | ||
146 | printk(KERN_INFO "wake %s for irq %d\n", | |
f5aeffb7 | 147 | state ? "enabled" : "disabled", data->irq); |
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148 | |
149 | if (!state) | |
150 | s3c_irqwake_eintmask |= bit; | |
151 | else | |
152 | s3c_irqwake_eintmask &= ~bit; | |
153 | ||
154 | return 0; | |
155 | } | |
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156 | |
157 | /* helper functions to save and restore register state */ | |
158 | ||
159 | /** | |
160 | * s3c_pm_do_save() - save a set of registers for restoration on resume. | |
161 | * @ptr: Pointer to an array of registers. | |
162 | * @count: Size of the ptr array. | |
163 | * | |
164 | * Run through the list of registers given, saving their contents in the | |
165 | * array for later restoration when we wakeup. | |
166 | */ | |
167 | void s3c_pm_do_save(struct sleep_save *ptr, int count) | |
168 | { | |
169 | for (; count > 0; count--, ptr++) { | |
170 | ptr->val = __raw_readl(ptr->reg); | |
171 | S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); | |
172 | } | |
173 | } | |
174 | ||
175 | /** | |
176 | * s3c_pm_do_restore() - restore register values from the save list. | |
177 | * @ptr: Pointer to an array of registers. | |
178 | * @count: Size of the ptr array. | |
179 | * | |
180 | * Restore the register values saved from s3c_pm_do_save(). | |
181 | * | |
182 | * Note, we do not use S3C_PMDBG() in here, as the system may not have | |
183 | * restore the UARTs state yet | |
184 | */ | |
185 | ||
186 | void s3c_pm_do_restore(struct sleep_save *ptr, int count) | |
187 | { | |
188 | for (; count > 0; count--, ptr++) { | |
189 | printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", | |
190 | ptr->reg, ptr->val, __raw_readl(ptr->reg)); | |
191 | ||
192 | __raw_writel(ptr->val, ptr->reg); | |
193 | } | |
194 | } | |
195 | ||
196 | /** | |
197 | * s3c_pm_do_restore_core() - early restore register values from save list. | |
198 | * | |
199 | * This is similar to s3c_pm_do_restore() except we try and minimise the | |
200 | * side effects of the function in case registers that hardware might need | |
201 | * to work has been restored. | |
202 | * | |
203 | * WARNING: Do not put any debug in here that may effect memory or use | |
204 | * peripherals, as things may be changing! | |
205 | */ | |
206 | ||
207 | void s3c_pm_do_restore_core(struct sleep_save *ptr, int count) | |
208 | { | |
209 | for (; count > 0; count--, ptr++) | |
210 | __raw_writel(ptr->val, ptr->reg); | |
211 | } | |
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212 | |
213 | /* s3c2410_pm_show_resume_irqs | |
214 | * | |
215 | * print any IRQs asserted at resume time (ie, we woke from) | |
216 | */ | |
baab7307 MC |
217 | static void __maybe_unused s3c_pm_show_resume_irqs(int start, |
218 | unsigned long which, | |
219 | unsigned long mask) | |
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220 | { |
221 | int i; | |
222 | ||
223 | which &= ~mask; | |
224 | ||
225 | for (i = 0; i <= 31; i++) { | |
226 | if (which & (1L<<i)) { | |
227 | S3C_PMDBG("IRQ %d asserted at resume\n", start+i); | |
228 | } | |
229 | } | |
230 | } | |
231 | ||
232 | ||
233 | void (*pm_cpu_prep)(void); | |
e7089da9 | 234 | void (*pm_cpu_sleep)(unsigned long); |
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235 | |
236 | #define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) | |
237 | ||
238 | /* s3c_pm_enter | |
239 | * | |
240 | * central control for sleep/resume process | |
241 | */ | |
242 | ||
243 | static int s3c_pm_enter(suspend_state_t state) | |
244 | { | |
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245 | /* ensure the debug is initialised (if enabled) */ |
246 | ||
247 | s3c_pm_debug_init(); | |
248 | ||
249 | S3C_PMDBG("%s(%d)\n", __func__, state); | |
250 | ||
251 | if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { | |
252 | printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__); | |
253 | return -EINVAL; | |
254 | } | |
255 | ||
256 | /* check if we have anything to wake-up with... bad things seem | |
257 | * to happen if you suspend with no wakeup (system will often | |
258 | * require a full power-cycle) | |
259 | */ | |
260 | ||
261 | if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && | |
262 | !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { | |
263 | printk(KERN_ERR "%s: No wake-up sources!\n", __func__); | |
264 | printk(KERN_ERR "%s: Aborting sleep\n", __func__); | |
265 | return -EINVAL; | |
266 | } | |
267 | ||
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268 | /* save all necessary core registers not covered by the drivers */ |
269 | ||
270 | s3c_pm_save_gpios(); | |
d2b07fe2 | 271 | s3c_pm_save_uarts(); |
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272 | s3c_pm_save_core(); |
273 | ||
274 | /* set the irq configuration for wake */ | |
275 | ||
276 | s3c_pm_configure_extint(); | |
277 | ||
278 | S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n", | |
279 | s3c_irqwake_intmask, s3c_irqwake_eintmask); | |
280 | ||
281 | s3c_pm_arch_prepare_irqs(); | |
282 | ||
283 | /* call cpu specific preparation */ | |
284 | ||
285 | pm_cpu_prep(); | |
286 | ||
287 | /* flush cache back to ram */ | |
288 | ||
289 | flush_cache_all(); | |
290 | ||
291 | s3c_pm_check_store(); | |
292 | ||
293 | /* send the cpu to sleep... */ | |
294 | ||
295 | s3c_pm_arch_stop_clocks(); | |
296 | ||
e7089da9 | 297 | /* this will also act as our return point from when |
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298 | * we resume as it saves its own register state and restores it |
299 | * during the resume. */ | |
2261e0e6 | 300 | |
e7089da9 | 301 | cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, 0, pm_cpu_sleep); |
2261e0e6 | 302 | |
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303 | /* restore the system state */ |
304 | ||
305 | s3c_pm_restore_core(); | |
d2b07fe2 | 306 | s3c_pm_restore_uarts(); |
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307 | s3c_pm_restore_gpios(); |
308 | ||
309 | s3c_pm_debug_init(); | |
310 | ||
311 | /* check what irq (if any) restored the system */ | |
312 | ||
313 | s3c_pm_arch_show_resume_irqs(); | |
314 | ||
315 | S3C_PMDBG("%s: post sleep, preparing to return\n", __func__); | |
316 | ||
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317 | /* LEDs should now be 1110 */ |
318 | s3c_pm_debug_smdkled(1 << 1, 0); | |
319 | ||
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320 | s3c_pm_check_restore(); |
321 | ||
322 | /* ok, let's return from sleep */ | |
323 | ||
324 | S3C_PMDBG("S3C PM Resume (post-restore)\n"); | |
325 | return 0; | |
326 | } | |
327 | ||
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328 | static int s3c_pm_prepare(void) |
329 | { | |
330 | /* prepare check area if configured */ | |
331 | ||
332 | s3c_pm_check_prepare(); | |
333 | return 0; | |
334 | } | |
335 | ||
336 | static void s3c_pm_finish(void) | |
337 | { | |
338 | s3c_pm_check_cleanup(); | |
339 | } | |
340 | ||
2f55ac07 | 341 | static const struct platform_suspend_ops s3c_pm_ops = { |
2261e0e6 | 342 | .enter = s3c_pm_enter, |
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343 | .prepare = s3c_pm_prepare, |
344 | .finish = s3c_pm_finish, | |
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345 | .valid = suspend_valid_only_mem, |
346 | }; | |
347 | ||
4e59c25d | 348 | /* s3c_pm_init |
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349 | * |
350 | * Attach the power management functions. This should be called | |
351 | * from the board specific initialisation if the board supports | |
352 | * it. | |
353 | */ | |
354 | ||
4e59c25d | 355 | int __init s3c_pm_init(void) |
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356 | { |
357 | printk("S3C Power Management, Copyright 2004 Simtec Electronics\n"); | |
358 | ||
359 | suspend_set_ops(&s3c_pm_ops); | |
360 | return 0; | |
361 | } |