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1 | /* linux/arch/arm/plat-s3c/pm.c |
2 | * | |
3 | * Copyright 2008 Openmoko, Inc. | |
ccae941e | 4 | * Copyright 2004-2008 Simtec Electronics |
6419711a BD |
5 | * Ben Dooks <ben@simtec.co.uk> |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * S3C common power management (suspend to ram) support. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/suspend.h> | |
17 | #include <linux/errno.h> | |
2261e0e6 | 18 | #include <linux/delay.h> |
cd3fc1b9 | 19 | #include <linux/of.h> |
2261e0e6 | 20 | #include <linux/serial_core.h> |
6419711a BD |
21 | #include <linux/io.h> |
22 | ||
2261e0e6 | 23 | #include <asm/cacheflush.h> |
2c74a0ce | 24 | #include <asm/suspend.h> |
2261e0e6 BD |
25 | |
26 | #include <plat/regs-serial.h> | |
d6280ffb TF |
27 | |
28 | #ifdef CONFIG_SAMSUNG_ATAGS | |
29 | #include <mach/hardware.h> | |
30 | #include <mach/map.h> | |
05a6380c | 31 | #ifndef CONFIG_ARCH_EXYNOS |
2857f650 | 32 | #include <mach/regs-clock.h> |
2261e0e6 | 33 | #include <mach/regs-irq.h> |
05a6380c | 34 | #endif |
7ba8022f | 35 | #include <mach/irqs.h> |
d6280ffb TF |
36 | #endif |
37 | ||
56b34426 | 38 | #include <asm/irq.h> |
2261e0e6 | 39 | |
6419711a | 40 | #include <plat/pm.h> |
431fb7df | 41 | #include <mach/pm-core.h> |
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42 | |
43 | /* for external use */ | |
44 | ||
45 | unsigned long s3c_pm_flags; | |
46 | ||
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47 | /* Debug code: |
48 | * | |
49 | * This code supports debug output to the low level UARTs for use on | |
50 | * resume before the console layer is available. | |
51 | */ | |
52 | ||
8005745d | 53 | #ifdef CONFIG_SAMSUNG_PM_DEBUG |
6419711a BD |
54 | extern void printascii(const char *); |
55 | ||
56 | void s3c_pm_dbg(const char *fmt, ...) | |
57 | { | |
58 | va_list va; | |
59 | char buff[256]; | |
60 | ||
61 | va_start(va, fmt); | |
8baaa265 | 62 | vsnprintf(buff, sizeof(buff), fmt, va); |
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63 | va_end(va); |
64 | ||
65 | printascii(buff); | |
66 | } | |
2261e0e6 BD |
67 | |
68 | static inline void s3c_pm_debug_init(void) | |
69 | { | |
70 | /* restart uart clocks so we can use them to output */ | |
71 | s3c_pm_debug_init_uart(); | |
72 | } | |
73 | ||
74 | #else | |
75 | #define s3c_pm_debug_init() do { } while(0) | |
76 | ||
8005745d | 77 | #endif /* CONFIG_SAMSUNG_PM_DEBUG */ |
6419711a | 78 | |
2261e0e6 BD |
79 | /* Save the UART configurations if we are configured for debug. */ |
80 | ||
4b637dc2 BD |
81 | unsigned char pm_uart_udivslot; |
82 | ||
8005745d | 83 | #ifdef CONFIG_SAMSUNG_PM_DEBUG |
2261e0e6 | 84 | |
7bdc84fb | 85 | static struct pm_uart_save uart_save; |
d2b07fe2 BD |
86 | |
87 | static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) | |
88 | { | |
89 | void __iomem *regs = S3C_VA_UARTx(uart); | |
90 | ||
91 | save->ulcon = __raw_readl(regs + S3C2410_ULCON); | |
92 | save->ucon = __raw_readl(regs + S3C2410_UCON); | |
93 | save->ufcon = __raw_readl(regs + S3C2410_UFCON); | |
94 | save->umcon = __raw_readl(regs + S3C2410_UMCON); | |
95 | save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); | |
57699e9a | 96 | |
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97 | if (pm_uart_udivslot) |
98 | save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); | |
99 | ||
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100 | S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n", |
101 | uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv); | |
d2b07fe2 | 102 | } |
2261e0e6 | 103 | |
d2b07fe2 | 104 | static void s3c_pm_save_uarts(void) |
2261e0e6 | 105 | { |
7bdc84fb | 106 | s3c_pm_save_uart(CONFIG_DEBUG_S3C_UART, &uart_save); |
d2b07fe2 BD |
107 | } |
108 | ||
109 | static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save) | |
110 | { | |
111 | void __iomem *regs = S3C_VA_UARTx(uart); | |
112 | ||
57699e9a BD |
113 | s3c_pm_arch_update_uart(regs, save); |
114 | ||
d2b07fe2 BD |
115 | __raw_writel(save->ulcon, regs + S3C2410_ULCON); |
116 | __raw_writel(save->ucon, regs + S3C2410_UCON); | |
117 | __raw_writel(save->ufcon, regs + S3C2410_UFCON); | |
118 | __raw_writel(save->umcon, regs + S3C2410_UMCON); | |
119 | __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); | |
4b637dc2 BD |
120 | |
121 | if (pm_uart_udivslot) | |
122 | __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT); | |
2261e0e6 BD |
123 | } |
124 | ||
d2b07fe2 | 125 | static void s3c_pm_restore_uarts(void) |
2261e0e6 | 126 | { |
7bdc84fb | 127 | s3c_pm_restore_uart(CONFIG_DEBUG_S3C_UART, &uart_save); |
2261e0e6 BD |
128 | } |
129 | #else | |
d2b07fe2 BD |
130 | static void s3c_pm_save_uarts(void) { } |
131 | static void s3c_pm_restore_uarts(void) { } | |
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132 | #endif |
133 | ||
56b34426 BD |
134 | /* The IRQ ext-int code goes here, it is too small to currently bother |
135 | * with its own file. */ | |
136 | ||
137 | unsigned long s3c_irqwake_intmask = 0xffffffffL; | |
138 | unsigned long s3c_irqwake_eintmask = 0xffffffffL; | |
139 | ||
f5aeffb7 | 140 | int s3c_irqext_wake(struct irq_data *data, unsigned int state) |
56b34426 | 141 | { |
f5aeffb7 | 142 | unsigned long bit = 1L << IRQ_EINT_BIT(data->irq); |
56b34426 BD |
143 | |
144 | if (!(s3c_irqwake_eintallow & bit)) | |
145 | return -ENOENT; | |
146 | ||
147 | printk(KERN_INFO "wake %s for irq %d\n", | |
f5aeffb7 | 148 | state ? "enabled" : "disabled", data->irq); |
56b34426 BD |
149 | |
150 | if (!state) | |
151 | s3c_irqwake_eintmask |= bit; | |
152 | else | |
153 | s3c_irqwake_eintmask &= ~bit; | |
154 | ||
155 | return 0; | |
156 | } | |
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157 | |
158 | /* helper functions to save and restore register state */ | |
159 | ||
160 | /** | |
161 | * s3c_pm_do_save() - save a set of registers for restoration on resume. | |
162 | * @ptr: Pointer to an array of registers. | |
163 | * @count: Size of the ptr array. | |
164 | * | |
165 | * Run through the list of registers given, saving their contents in the | |
166 | * array for later restoration when we wakeup. | |
167 | */ | |
168 | void s3c_pm_do_save(struct sleep_save *ptr, int count) | |
169 | { | |
170 | for (; count > 0; count--, ptr++) { | |
171 | ptr->val = __raw_readl(ptr->reg); | |
172 | S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); | |
173 | } | |
174 | } | |
175 | ||
176 | /** | |
177 | * s3c_pm_do_restore() - restore register values from the save list. | |
178 | * @ptr: Pointer to an array of registers. | |
179 | * @count: Size of the ptr array. | |
180 | * | |
181 | * Restore the register values saved from s3c_pm_do_save(). | |
182 | * | |
183 | * Note, we do not use S3C_PMDBG() in here, as the system may not have | |
184 | * restore the UARTs state yet | |
185 | */ | |
186 | ||
c143751a | 187 | void s3c_pm_do_restore(const struct sleep_save *ptr, int count) |
6419711a BD |
188 | { |
189 | for (; count > 0; count--, ptr++) { | |
190 | printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", | |
191 | ptr->reg, ptr->val, __raw_readl(ptr->reg)); | |
192 | ||
193 | __raw_writel(ptr->val, ptr->reg); | |
194 | } | |
195 | } | |
196 | ||
197 | /** | |
198 | * s3c_pm_do_restore_core() - early restore register values from save list. | |
199 | * | |
200 | * This is similar to s3c_pm_do_restore() except we try and minimise the | |
201 | * side effects of the function in case registers that hardware might need | |
202 | * to work has been restored. | |
203 | * | |
204 | * WARNING: Do not put any debug in here that may effect memory or use | |
205 | * peripherals, as things may be changing! | |
206 | */ | |
207 | ||
c143751a | 208 | void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count) |
6419711a BD |
209 | { |
210 | for (; count > 0; count--, ptr++) | |
211 | __raw_writel(ptr->val, ptr->reg); | |
212 | } | |
2261e0e6 BD |
213 | |
214 | /* s3c2410_pm_show_resume_irqs | |
215 | * | |
216 | * print any IRQs asserted at resume time (ie, we woke from) | |
217 | */ | |
baab7307 MC |
218 | static void __maybe_unused s3c_pm_show_resume_irqs(int start, |
219 | unsigned long which, | |
220 | unsigned long mask) | |
2261e0e6 BD |
221 | { |
222 | int i; | |
223 | ||
224 | which &= ~mask; | |
225 | ||
226 | for (i = 0; i <= 31; i++) { | |
227 | if (which & (1L<<i)) { | |
228 | S3C_PMDBG("IRQ %d asserted at resume\n", start+i); | |
229 | } | |
230 | } | |
231 | } | |
232 | ||
233 | ||
234 | void (*pm_cpu_prep)(void); | |
29cb3cd2 | 235 | int (*pm_cpu_sleep)(unsigned long); |
2261e0e6 BD |
236 | |
237 | #define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) | |
238 | ||
239 | /* s3c_pm_enter | |
240 | * | |
241 | * central control for sleep/resume process | |
242 | */ | |
243 | ||
244 | static int s3c_pm_enter(suspend_state_t state) | |
245 | { | |
d3fcacf5 | 246 | int ret; |
2261e0e6 BD |
247 | /* ensure the debug is initialised (if enabled) */ |
248 | ||
249 | s3c_pm_debug_init(); | |
250 | ||
251 | S3C_PMDBG("%s(%d)\n", __func__, state); | |
252 | ||
253 | if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { | |
254 | printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__); | |
255 | return -EINVAL; | |
256 | } | |
257 | ||
258 | /* check if we have anything to wake-up with... bad things seem | |
259 | * to happen if you suspend with no wakeup (system will often | |
260 | * require a full power-cycle) | |
261 | */ | |
262 | ||
cd3fc1b9 TF |
263 | if (!of_have_populated_dt() && |
264 | !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && | |
2261e0e6 BD |
265 | !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { |
266 | printk(KERN_ERR "%s: No wake-up sources!\n", __func__); | |
267 | printk(KERN_ERR "%s: Aborting sleep\n", __func__); | |
268 | return -EINVAL; | |
269 | } | |
270 | ||
2261e0e6 BD |
271 | /* save all necessary core registers not covered by the drivers */ |
272 | ||
cd3fc1b9 TF |
273 | if (!of_have_populated_dt()) { |
274 | samsung_pm_save_gpios(); | |
275 | samsung_pm_saved_gpios(); | |
276 | } | |
277 | ||
d2b07fe2 | 278 | s3c_pm_save_uarts(); |
2261e0e6 BD |
279 | s3c_pm_save_core(); |
280 | ||
281 | /* set the irq configuration for wake */ | |
282 | ||
283 | s3c_pm_configure_extint(); | |
284 | ||
285 | S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n", | |
286 | s3c_irqwake_intmask, s3c_irqwake_eintmask); | |
287 | ||
288 | s3c_pm_arch_prepare_irqs(); | |
289 | ||
290 | /* call cpu specific preparation */ | |
291 | ||
292 | pm_cpu_prep(); | |
293 | ||
294 | /* flush cache back to ram */ | |
295 | ||
296 | flush_cache_all(); | |
297 | ||
298 | s3c_pm_check_store(); | |
299 | ||
300 | /* send the cpu to sleep... */ | |
301 | ||
302 | s3c_pm_arch_stop_clocks(); | |
303 | ||
e7089da9 | 304 | /* this will also act as our return point from when |
fff94cd9 BD |
305 | * we resume as it saves its own register state and restores it |
306 | * during the resume. */ | |
2261e0e6 | 307 | |
d3fcacf5 AK |
308 | ret = cpu_suspend(0, pm_cpu_sleep); |
309 | if (ret) | |
310 | return ret; | |
2261e0e6 | 311 | |
2261e0e6 BD |
312 | /* restore the system state */ |
313 | ||
314 | s3c_pm_restore_core(); | |
d2b07fe2 | 315 | s3c_pm_restore_uarts(); |
cd3fc1b9 TF |
316 | |
317 | if (!of_have_populated_dt()) { | |
318 | samsung_pm_restore_gpios(); | |
319 | s3c_pm_restored_gpios(); | |
320 | } | |
2261e0e6 BD |
321 | |
322 | s3c_pm_debug_init(); | |
323 | ||
324 | /* check what irq (if any) restored the system */ | |
325 | ||
326 | s3c_pm_arch_show_resume_irqs(); | |
327 | ||
328 | S3C_PMDBG("%s: post sleep, preparing to return\n", __func__); | |
329 | ||
bd117bd1 BD |
330 | /* LEDs should now be 1110 */ |
331 | s3c_pm_debug_smdkled(1 << 1, 0); | |
332 | ||
2261e0e6 BD |
333 | s3c_pm_check_restore(); |
334 | ||
335 | /* ok, let's return from sleep */ | |
336 | ||
337 | S3C_PMDBG("S3C PM Resume (post-restore)\n"); | |
338 | return 0; | |
339 | } | |
340 | ||
aa8aba69 BD |
341 | static int s3c_pm_prepare(void) |
342 | { | |
343 | /* prepare check area if configured */ | |
344 | ||
345 | s3c_pm_check_prepare(); | |
346 | return 0; | |
347 | } | |
348 | ||
349 | static void s3c_pm_finish(void) | |
350 | { | |
351 | s3c_pm_check_cleanup(); | |
352 | } | |
353 | ||
2f55ac07 | 354 | static const struct platform_suspend_ops s3c_pm_ops = { |
2261e0e6 | 355 | .enter = s3c_pm_enter, |
aa8aba69 BD |
356 | .prepare = s3c_pm_prepare, |
357 | .finish = s3c_pm_finish, | |
2261e0e6 BD |
358 | .valid = suspend_valid_only_mem, |
359 | }; | |
360 | ||
4e59c25d | 361 | /* s3c_pm_init |
2261e0e6 BD |
362 | * |
363 | * Attach the power management functions. This should be called | |
364 | * from the board specific initialisation if the board supports | |
365 | * it. | |
366 | */ | |
367 | ||
4e59c25d | 368 | int __init s3c_pm_init(void) |
2261e0e6 BD |
369 | { |
370 | printk("S3C Power Management, Copyright 2004 Simtec Electronics\n"); | |
371 | ||
372 | suspend_set_ops(&s3c_pm_ops); | |
373 | return 0; | |
374 | } |