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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/vfp/vfphw.S | |
3 | * | |
4 | * Copyright (C) 2004 ARM Limited. | |
5 | * Written by Deep Blue Solutions Limited. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This code is called from the kernel's undefined instruction trap. | |
12 | * r9 holds the return address for successful handling. | |
13 | * lr holds the return address for unrecognised instructions. | |
14 | * r10 points at the start of the private FP workspace in the thread structure | |
15 | * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h) | |
16 | */ | |
39ad04cc CM |
17 | #include <linux/init.h> |
18 | #include <linux/linkage.h> | |
1da177e4 LT |
19 | #include <asm/thread_info.h> |
20 | #include <asm/vfpmacros.h> | |
0cc41e4a | 21 | #include <linux/kern_levels.h> |
39ad04cc CM |
22 | #include <asm/assembler.h> |
23 | #include <asm/asm-offsets.h> | |
1da177e4 LT |
24 | |
25 | .macro DBGSTR, str | |
26 | #ifdef DEBUG | |
27 | stmfd sp!, {r0-r3, ip, lr} | |
ded3ef0f | 28 | ldr r0, =1f |
1da177e4 | 29 | bl printk |
ded3ef0f RK |
30 | ldmfd sp!, {r0-r3, ip, lr} |
31 | ||
32 | .pushsection .rodata, "a" | |
33 | 1: .ascii KERN_DEBUG "VFP: \str\n" | |
34 | .byte 0 | |
35 | .previous | |
1da177e4 LT |
36 | #endif |
37 | .endm | |
38 | ||
39 | .macro DBGSTR1, str, arg | |
40 | #ifdef DEBUG | |
41 | stmfd sp!, {r0-r3, ip, lr} | |
42 | mov r1, \arg | |
ded3ef0f | 43 | ldr r0, =1f |
1da177e4 | 44 | bl printk |
ded3ef0f RK |
45 | ldmfd sp!, {r0-r3, ip, lr} |
46 | ||
47 | .pushsection .rodata, "a" | |
48 | 1: .ascii KERN_DEBUG "VFP: \str\n" | |
49 | .byte 0 | |
50 | .previous | |
1da177e4 LT |
51 | #endif |
52 | .endm | |
53 | ||
54 | .macro DBGSTR3, str, arg1, arg2, arg3 | |
55 | #ifdef DEBUG | |
56 | stmfd sp!, {r0-r3, ip, lr} | |
57 | mov r3, \arg3 | |
58 | mov r2, \arg2 | |
59 | mov r1, \arg1 | |
ded3ef0f | 60 | ldr r0, =1f |
1da177e4 | 61 | bl printk |
ded3ef0f RK |
62 | ldmfd sp!, {r0-r3, ip, lr} |
63 | ||
64 | .pushsection .rodata, "a" | |
65 | 1: .ascii KERN_DEBUG "VFP: \str\n" | |
66 | .byte 0 | |
67 | .previous | |
1da177e4 LT |
68 | #endif |
69 | .endm | |
70 | ||
71 | ||
72 | @ VFP hardware support entry point. | |
73 | @ | |
15ac49b6 RK |
74 | @ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) |
75 | @ r2 = PC value to resume execution after successful emulation | |
76 | @ r9 = normal "successful" return address | |
1da177e4 | 77 | @ r10 = vfp_state union |
c6428464 | 78 | @ r11 = CPU number |
15ac49b6 RK |
79 | @ lr = unrecognised instruction return address |
80 | @ IRQs enabled. | |
93ed3970 | 81 | ENTRY(vfp_support_entry) |
1da177e4 LT |
82 | DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10 |
83 | ||
ab3da156 AB |
84 | ldr r3, [sp, #S_PSR] @ Neither lazy restore nor FP exceptions |
85 | and r3, r3, #MODE_MASK @ are supported in kernel mode | |
86 | teq r3, #USR_MODE | |
87 | bne vfp_kmode_exception @ Returns through lr | |
88 | ||
1da177e4 LT |
89 | VFPFMRX r1, FPEXC @ Is the VFP enabled? |
90 | DBGSTR1 "fpexc %08x", r1 | |
228adef1 | 91 | tst r1, #FPEXC_EN |
1da177e4 LT |
92 | bne look_for_VFP_exceptions @ VFP is already enabled |
93 | ||
94 | DBGSTR1 "enable %x", r10 | |
af61bdf0 | 95 | ldr r3, vfp_current_hw_state_address |
228adef1 | 96 | orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set |
af61bdf0 | 97 | ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer |
228adef1 | 98 | bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled |
08409c33 | 99 | cmp r4, r10 @ this thread owns the hw context? |
f8f2a852 RK |
100 | #ifndef CONFIG_SMP |
101 | @ For UP, checking that this thread owns the hw context is | |
102 | @ sufficient to determine that the hardware state is valid. | |
08409c33 | 103 | beq vfp_hw_state_valid |
1da177e4 | 104 | |
f8f2a852 RK |
105 | @ On UP, we lazily save the VFP context. As a different |
106 | @ thread wants ownership of the VFP hardware, save the old | |
107 | @ state if there was a previous (valid) owner. | |
108 | ||
1da177e4 LT |
109 | VFPFMXR FPEXC, r5 @ enable VFP, disable any pending |
110 | @ exceptions, so we can get at the | |
111 | @ rest of it | |
112 | ||
1da177e4 | 113 | DBGSTR1 "save old state %p", r4 |
f8f2a852 RK |
114 | cmp r4, #0 @ if the vfp_current_hw_state is NULL |
115 | beq vfp_reload_hw @ then the hw state needs reloading | |
25ebee02 | 116 | VFPFSTMIA r4, r5 @ save the working registers |
1da177e4 | 117 | VFPFMRX r5, FPSCR @ current status |
85d6943a | 118 | #ifndef CONFIG_CPU_FEROCEON |
c98929c0 | 119 | tst r1, #FPEXC_EX @ is there additional state to save? |
24b647a0 CM |
120 | beq 1f |
121 | VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) | |
122 | tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? | |
123 | beq 1f | |
124 | VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) | |
125 | 1: | |
85d6943a | 126 | #endif |
1da177e4 | 127 | stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 |
f8f2a852 RK |
128 | vfp_reload_hw: |
129 | ||
130 | #else | |
131 | @ For SMP, if this thread does not own the hw context, then we | |
132 | @ need to reload it. No need to save the old state as on SMP, | |
133 | @ we always save the state when we switch away from a thread. | |
134 | bne vfp_reload_hw | |
135 | ||
136 | @ This thread has ownership of the current hardware context. | |
137 | @ However, it may have been migrated to another CPU, in which | |
138 | @ case the saved state is newer than the hardware context. | |
139 | @ Check this by looking at the CPU number which the state was | |
140 | @ last loaded onto. | |
141 | ldr ip, [r10, #VFP_CPU] | |
142 | teq ip, r11 | |
143 | beq vfp_hw_state_valid | |
144 | ||
145 | vfp_reload_hw: | |
146 | @ We're loading this threads state into the VFP hardware. Update | |
147 | @ the CPU number which contains the most up to date VFP context. | |
148 | str r11, [r10, #VFP_CPU] | |
149 | ||
150 | VFPFMXR FPEXC, r5 @ enable VFP, disable any pending | |
151 | @ exceptions, so we can get at the | |
152 | @ rest of it | |
c6428464 | 153 | #endif |
1da177e4 | 154 | |
1da177e4 | 155 | DBGSTR1 "load state %p", r10 |
af61bdf0 | 156 | str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer |
1da177e4 | 157 | @ Load the saved state back into the VFP |
25ebee02 | 158 | VFPFLDMIA r10, r5 @ reload the working registers while |
1da177e4 | 159 | @ FPEXC is in a safe state |
80ed3547 | 160 | ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2 |
85d6943a | 161 | #ifndef CONFIG_CPU_FEROCEON |
c98929c0 | 162 | tst r1, #FPEXC_EX @ is there additional state to restore? |
24b647a0 CM |
163 | beq 1f |
164 | VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set) | |
165 | tst r1, #FPEXC_FP2V @ is there an FPINST2 to write? | |
166 | beq 1f | |
167 | VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present) | |
168 | 1: | |
85d6943a | 169 | #endif |
1da177e4 LT |
170 | VFPFMXR FPSCR, r5 @ restore status |
171 | ||
08409c33 RK |
172 | @ The context stored in the VFP hardware is up to date with this thread |
173 | vfp_hw_state_valid: | |
228adef1 | 174 | tst r1, #FPEXC_EX |
1da177e4 LT |
175 | bne process_exception @ might as well handle the pending |
176 | @ exception before retrying branch | |
177 | @ out before setting an FPEXC that | |
178 | @ stops us reading stuff | |
15ac49b6 RK |
179 | VFPFMXR FPEXC, r1 @ Restore FPEXC last |
180 | sub r2, r2, #4 @ Retry current instruction - if Thumb | |
181 | str r2, [sp, #S_PC] @ mode it's two 16-bit instructions, | |
182 | @ else it's one 32-bit instruction, so | |
183 | @ always subtract 4 from the following | |
184 | @ instruction address. | |
0b1f68e8 | 185 | dec_preempt_count_ti r10, r4 |
6ebbf2ce | 186 | ret r9 @ we think we have handled things |
1da177e4 LT |
187 | |
188 | ||
189 | look_for_VFP_exceptions: | |
c98929c0 CM |
190 | @ Check for synchronous or asynchronous exception |
191 | tst r1, #FPEXC_EX | FPEXC_DEX | |
1da177e4 | 192 | bne process_exception |
c98929c0 CM |
193 | @ On some implementations of the VFP subarch 1, setting FPSCR.IXE |
194 | @ causes all the CDP instructions to be bounced synchronously without | |
195 | @ setting the FPEXC.EX bit | |
1da177e4 | 196 | VFPFMRX r5, FPSCR |
c98929c0 | 197 | tst r5, #FPSCR_IXE |
1da177e4 LT |
198 | bne process_exception |
199 | ||
1ca8bf6f SM |
200 | tst r5, #FPSCR_LENGTH_MASK |
201 | beq skip | |
202 | orr r1, r1, #FPEXC_DEX | |
203 | b process_exception | |
204 | skip: | |
205 | ||
1da177e4 LT |
206 | @ Fall into hand on to next handler - appropriate coproc instr |
207 | @ not recognised by VFP | |
208 | ||
209 | DBGSTR "not VFP" | |
0b1f68e8 | 210 | dec_preempt_count_ti r10, r4 |
6ebbf2ce | 211 | ret lr |
1da177e4 LT |
212 | |
213 | process_exception: | |
214 | DBGSTR "bounce" | |
1da177e4 LT |
215 | mov r2, sp @ nothing stacked - regdump is at TOS |
216 | mov lr, r9 @ setup for a return to the user code. | |
217 | ||
218 | @ Now call the C code to package up the bounce to the support code | |
219 | @ r0 holds the trigger instruction | |
220 | @ r1 holds the FPEXC value | |
221 | @ r2 pointer to register dump | |
c98929c0 | 222 | b VFP_bounce @ we have handled this - the support |
1da177e4 LT |
223 | @ code will raise an exception if |
224 | @ required. If not, the user code will | |
225 | @ retry the faulted instruction | |
93ed3970 | 226 | ENDPROC(vfp_support_entry) |
1da177e4 | 227 | |
93ed3970 | 228 | ENTRY(vfp_save_state) |
c6428464 CM |
229 | @ Save the current VFP state |
230 | @ r0 - save location | |
231 | @ r1 - FPEXC | |
232 | DBGSTR1 "save VFP state %p", r0 | |
25ebee02 | 233 | VFPFSTMIA r0, r2 @ save the working registers |
c6428464 | 234 | VFPFMRX r2, FPSCR @ current status |
c98929c0 | 235 | tst r1, #FPEXC_EX @ is there additional state to save? |
24b647a0 CM |
236 | beq 1f |
237 | VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set) | |
238 | tst r1, #FPEXC_FP2V @ is there an FPINST2 to read? | |
239 | beq 1f | |
240 | VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present) | |
241 | 1: | |
c6428464 | 242 | stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 |
6ebbf2ce | 243 | ret lr |
93ed3970 | 244 | ENDPROC(vfp_save_state) |
c6428464 | 245 | |
7eb25ebe | 246 | .align |
af61bdf0 RK |
247 | vfp_current_hw_state_address: |
248 | .word vfp_current_hw_state | |
1da177e4 | 249 | |
07f33a03 CM |
250 | .macro tbl_branch, base, tmp, shift |
251 | #ifdef CONFIG_THUMB2_KERNEL | |
252 | adr \tmp, 1f | |
253 | add \tmp, \tmp, \base, lsl \shift | |
6ebbf2ce | 254 | ret \tmp |
07f33a03 CM |
255 | #else |
256 | add pc, pc, \base, lsl \shift | |
1da177e4 | 257 | mov r0, r0 |
07f33a03 CM |
258 | #endif |
259 | 1: | |
260 | .endm | |
261 | ||
262 | ENTRY(vfp_get_float) | |
263 | tbl_branch r0, r3, #3 | |
1da177e4 | 264 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
07f33a03 | 265 | 1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0 |
6ebbf2ce | 266 | ret lr |
07f33a03 CM |
267 | .org 1b + 8 |
268 | 1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1 | |
6ebbf2ce | 269 | ret lr |
07f33a03 | 270 | .org 1b + 8 |
1da177e4 | 271 | .endr |
93ed3970 | 272 | ENDPROC(vfp_get_float) |
1da177e4 | 273 | |
93ed3970 | 274 | ENTRY(vfp_put_float) |
07f33a03 | 275 | tbl_branch r1, r3, #3 |
1da177e4 | 276 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
07f33a03 | 277 | 1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0 |
6ebbf2ce | 278 | ret lr |
07f33a03 CM |
279 | .org 1b + 8 |
280 | 1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1 | |
6ebbf2ce | 281 | ret lr |
07f33a03 | 282 | .org 1b + 8 |
1da177e4 | 283 | .endr |
93ed3970 | 284 | ENDPROC(vfp_put_float) |
1da177e4 | 285 | |
93ed3970 | 286 | ENTRY(vfp_get_double) |
07f33a03 | 287 | tbl_branch r0, r3, #3 |
1da177e4 | 288 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
07f33a03 | 289 | 1: fmrrd r0, r1, d\dr |
6ebbf2ce | 290 | ret lr |
07f33a03 | 291 | .org 1b + 8 |
1da177e4 | 292 | .endr |
25ebee02 CM |
293 | #ifdef CONFIG_VFPv3 |
294 | @ d16 - d31 registers | |
295 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 | |
07f33a03 | 296 | 1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr |
6ebbf2ce | 297 | ret lr |
07f33a03 | 298 | .org 1b + 8 |
25ebee02 CM |
299 | .endr |
300 | #endif | |
1da177e4 | 301 | |
25ebee02 | 302 | @ virtual register 16 (or 32 if VFPv3) for compare with zero |
1da177e4 LT |
303 | mov r0, #0 |
304 | mov r1, #0 | |
6ebbf2ce | 305 | ret lr |
93ed3970 | 306 | ENDPROC(vfp_get_double) |
1da177e4 | 307 | |
93ed3970 | 308 | ENTRY(vfp_put_double) |
07f33a03 | 309 | tbl_branch r2, r3, #3 |
1da177e4 | 310 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
07f33a03 | 311 | 1: fmdrr d\dr, r0, r1 |
6ebbf2ce | 312 | ret lr |
07f33a03 | 313 | .org 1b + 8 |
1da177e4 | 314 | .endr |
25ebee02 CM |
315 | #ifdef CONFIG_VFPv3 |
316 | @ d16 - d31 registers | |
317 | .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 | |
138de1c4 | 318 | 1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr |
6ebbf2ce | 319 | ret lr |
07f33a03 | 320 | .org 1b + 8 |
25ebee02 CM |
321 | .endr |
322 | #endif | |
93ed3970 | 323 | ENDPROC(vfp_put_double) |