Commit | Line | Data |
---|---|---|
8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
b6197b93 | 3 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 4 | select ACPI_GENERIC_GSI if ACPI |
6933de0c | 5 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
8c2c3df3 | 6 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE |
2b68f6ca | 7 | select ARCH_HAS_ELF_RANDOMIZE |
957e3fac | 8 | select ARCH_HAS_GCOV_PROFILE_ALL |
308c09f1 | 9 | select ARCH_HAS_SG_CHAIN |
1f85008e | 10 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
c63c8700 | 11 | select ARCH_USE_CMPXCHG_LOCKREF |
4badad35 | 12 | select ARCH_SUPPORTS_ATOMIC_RMW |
9170100e | 13 | select ARCH_WANT_OPTIONAL_GPIOLIB |
6212a512 | 14 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 15 | select ARCH_WANT_FRAME_POINTERS |
25c92a37 | 16 | select ARM_AMBA |
1aee5d7a | 17 | select ARM_ARCH_TIMER |
c4188edc | 18 | select ARM_GIC |
875cbf3e | 19 | select AUDIT_ARCH_COMPAT_GENERIC |
853a33ce | 20 | select ARM_GIC_V2M if PCI_MSI |
021f6537 | 21 | select ARM_GIC_V3 |
19812729 | 22 | select ARM_GIC_V3_ITS if PCI_MSI |
bff60792 | 23 | select ARM_PSCI_FW |
adace895 | 24 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 25 | select CLONE_BACKWARDS |
7ca2ef33 | 26 | select COMMON_CLK |
166936ba | 27 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 28 | select DCACHE_WORD_ACCESS |
ef37566c | 29 | select EDAC_SUPPORT |
d4932f9e | 30 | select GENERIC_ALLOCATOR |
8c2c3df3 | 31 | select GENERIC_CLOCKEVENTS |
4b3dc967 | 32 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 33 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 34 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 35 | select GENERIC_IDLE_POLL_SETUP |
8c2c3df3 CM |
36 | select GENERIC_IRQ_PROBE |
37 | select GENERIC_IRQ_SHOW | |
6544e67b | 38 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 39 | select GENERIC_PCI_IOMAP |
65cd4f6c | 40 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 41 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
42 | select GENERIC_STRNCPY_FROM_USER |
43 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 44 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 45 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 46 | select HARDIRQS_SW_RESEND |
5284e1b4 | 47 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 48 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 49 | select HAVE_ARCH_BITREVERSE |
9732cafd | 50 | select HAVE_ARCH_JUMP_LABEL |
39d114dd | 51 | select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP |
9529247d | 52 | select HAVE_ARCH_KGDB |
a1ae65b2 | 53 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 54 | select HAVE_ARCH_TRACEHOOK |
e54bcde3 | 55 | select HAVE_BPF_JIT |
af64d2aa | 56 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 57 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 58 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 59 | select HAVE_CMPXCHG_LOCAL |
9b2a60c4 | 60 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 61 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 CM |
62 | select HAVE_DMA_API_DEBUG |
63 | select HAVE_DMA_ATTRS | |
6ac2104d | 64 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 65 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 66 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 67 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
68 | select HAVE_FUNCTION_TRACER |
69 | select HAVE_FUNCTION_GRAPH_TRACER | |
8c2c3df3 | 70 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 71 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
8c2c3df3 | 72 | select HAVE_MEMBLOCK |
55834a77 | 73 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 74 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
75 | select HAVE_PERF_REGS |
76 | select HAVE_PERF_USER_STACK_DUMP | |
5e5f6dc1 | 77 | select HAVE_RCU_TABLE_FREE |
055b1212 | 78 | select HAVE_SYSCALL_TRACEPOINTS |
876945db | 79 | select IOMMU_DMA if IOMMU_SUPPORT |
8c2c3df3 | 80 | select IRQ_DOMAIN |
e8557d1f | 81 | select IRQ_FORCED_THREADING |
fea2acaa | 82 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
83 | select NO_BOOTMEM |
84 | select OF | |
85 | select OF_EARLY_FLATTREE | |
9bf14b7c | 86 | select OF_RESERVED_MEM |
8c2c3df3 | 87 | select PERF_USE_VMALLOC |
aa1e8ec1 CM |
88 | select POWER_RESET |
89 | select POWER_SUPPLY | |
8c2c3df3 CM |
90 | select RTC_LIB |
91 | select SPARSE_IRQ | |
7ac57a89 | 92 | select SYSCTL_EXCEPTION_TRACE |
6c81fe79 | 93 | select HAVE_CONTEXT_TRACKING |
8c2c3df3 CM |
94 | help |
95 | ARM 64-bit (AArch64) Linux support. | |
96 | ||
97 | config 64BIT | |
98 | def_bool y | |
99 | ||
100 | config ARCH_PHYS_ADDR_T_64BIT | |
101 | def_bool y | |
102 | ||
103 | config MMU | |
104 | def_bool y | |
105 | ||
ce816fa8 | 106 | config NO_IOPORT_MAP |
d1e6dc91 | 107 | def_bool y if !PCI |
8c2c3df3 CM |
108 | |
109 | config STACKTRACE_SUPPORT | |
110 | def_bool y | |
111 | ||
bf0c4e04 JVS |
112 | config ILLEGAL_POINTER_VALUE |
113 | hex | |
114 | default 0xdead000000000000 | |
115 | ||
8c2c3df3 CM |
116 | config LOCKDEP_SUPPORT |
117 | def_bool y | |
118 | ||
119 | config TRACE_IRQFLAGS_SUPPORT | |
120 | def_bool y | |
121 | ||
c209f799 | 122 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
123 | def_bool y |
124 | ||
9fb7410f DM |
125 | config GENERIC_BUG |
126 | def_bool y | |
127 | depends on BUG | |
128 | ||
129 | config GENERIC_BUG_RELATIVE_POINTERS | |
130 | def_bool y | |
131 | depends on GENERIC_BUG | |
132 | ||
8c2c3df3 CM |
133 | config GENERIC_HWEIGHT |
134 | def_bool y | |
135 | ||
136 | config GENERIC_CSUM | |
137 | def_bool y | |
138 | ||
139 | config GENERIC_CALIBRATE_DELAY | |
140 | def_bool y | |
141 | ||
19e7640d | 142 | config ZONE_DMA |
8c2c3df3 CM |
143 | def_bool y |
144 | ||
29e56940 SC |
145 | config HAVE_GENERIC_RCU_GUP |
146 | def_bool y | |
147 | ||
8c2c3df3 CM |
148 | config ARCH_DMA_ADDR_T_64BIT |
149 | def_bool y | |
150 | ||
151 | config NEED_DMA_MAP_STATE | |
152 | def_bool y | |
153 | ||
154 | config NEED_SG_DMA_LENGTH | |
155 | def_bool y | |
156 | ||
4b3dc967 WD |
157 | config SMP |
158 | def_bool y | |
159 | ||
8c2c3df3 CM |
160 | config SWIOTLB |
161 | def_bool y | |
162 | ||
163 | config IOMMU_HELPER | |
164 | def_bool SWIOTLB | |
165 | ||
4cfb3613 AB |
166 | config KERNEL_MODE_NEON |
167 | def_bool y | |
168 | ||
92cc15fc RH |
169 | config FIX_EARLYCON_MEM |
170 | def_bool y | |
171 | ||
9f25e6ad KS |
172 | config PGTABLE_LEVELS |
173 | int | |
21539939 | 174 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad KS |
175 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
176 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
177 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
44eaacf1 SP |
178 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
179 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 180 | |
8c2c3df3 CM |
181 | source "init/Kconfig" |
182 | ||
183 | source "kernel/Kconfig.freezer" | |
184 | ||
6a377491 | 185 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 CM |
186 | |
187 | menu "Bus support" | |
188 | ||
d1e6dc91 LD |
189 | config PCI |
190 | bool "PCI support" | |
191 | help | |
192 | This feature enables support for PCI bus system. If you say Y | |
193 | here, the kernel will include drivers and infrastructure code | |
194 | to support PCI bus devices. | |
195 | ||
196 | config PCI_DOMAINS | |
197 | def_bool PCI | |
198 | ||
199 | config PCI_DOMAINS_GENERIC | |
200 | def_bool PCI | |
201 | ||
202 | config PCI_SYSCALL | |
203 | def_bool PCI | |
204 | ||
205 | source "drivers/pci/Kconfig" | |
206 | source "drivers/pci/pcie/Kconfig" | |
207 | source "drivers/pci/hotplug/Kconfig" | |
208 | ||
8c2c3df3 CM |
209 | endmenu |
210 | ||
211 | menu "Kernel Features" | |
212 | ||
c0a01b84 AP |
213 | menu "ARM errata workarounds via the alternatives framework" |
214 | ||
215 | config ARM64_ERRATUM_826319 | |
216 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
217 | default y | |
218 | help | |
219 | This option adds an alternative code sequence to work around ARM | |
220 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
221 | AXI master interface and an L2 cache. | |
222 | ||
223 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
224 | and is unable to accept a certain write via this interface, it will | |
225 | not progress on read data presented on the read data channel and the | |
226 | system can deadlock. | |
227 | ||
228 | The workaround promotes data cache clean instructions to | |
229 | data cache clean-and-invalidate. | |
230 | Please note that this does not necessarily enable the workaround, | |
231 | as it depends on the alternative framework, which will only patch | |
232 | the kernel if an affected CPU is detected. | |
233 | ||
234 | If unsure, say Y. | |
235 | ||
236 | config ARM64_ERRATUM_827319 | |
237 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
238 | default y | |
239 | help | |
240 | This option adds an alternative code sequence to work around ARM | |
241 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
242 | master interface and an L2 cache. | |
243 | ||
244 | Under certain conditions this erratum can cause a clean line eviction | |
245 | to occur at the same time as another transaction to the same address | |
246 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
247 | interconnect reorders the two transactions. | |
248 | ||
249 | The workaround promotes data cache clean instructions to | |
250 | data cache clean-and-invalidate. | |
251 | Please note that this does not necessarily enable the workaround, | |
252 | as it depends on the alternative framework, which will only patch | |
253 | the kernel if an affected CPU is detected. | |
254 | ||
255 | If unsure, say Y. | |
256 | ||
257 | config ARM64_ERRATUM_824069 | |
258 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
259 | default y | |
260 | help | |
261 | This option adds an alternative code sequence to work around ARM | |
262 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
263 | to a coherent interconnect. | |
264 | ||
265 | If a Cortex-A53 processor is executing a store or prefetch for | |
266 | write instruction at the same time as a processor in another | |
267 | cluster is executing a cache maintenance operation to the same | |
268 | address, then this erratum might cause a clean cache line to be | |
269 | incorrectly marked as dirty. | |
270 | ||
271 | The workaround promotes data cache clean instructions to | |
272 | data cache clean-and-invalidate. | |
273 | Please note that this option does not necessarily enable the | |
274 | workaround, as it depends on the alternative framework, which will | |
275 | only patch the kernel if an affected CPU is detected. | |
276 | ||
277 | If unsure, say Y. | |
278 | ||
279 | config ARM64_ERRATUM_819472 | |
280 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
281 | default y | |
282 | help | |
283 | This option adds an alternative code sequence to work around ARM | |
284 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
285 | present when it is connected to a coherent interconnect. | |
286 | ||
287 | If the processor is executing a load and store exclusive sequence at | |
288 | the same time as a processor in another cluster is executing a cache | |
289 | maintenance operation to the same address, then this erratum might | |
290 | cause data corruption. | |
291 | ||
292 | The workaround promotes data cache clean instructions to | |
293 | data cache clean-and-invalidate. | |
294 | Please note that this does not necessarily enable the workaround, | |
295 | as it depends on the alternative framework, which will only patch | |
296 | the kernel if an affected CPU is detected. | |
297 | ||
298 | If unsure, say Y. | |
299 | ||
300 | config ARM64_ERRATUM_832075 | |
301 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
302 | default y | |
303 | help | |
304 | This option adds an alternative code sequence to work around ARM | |
305 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
306 | ||
307 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
308 | instructions to Write-Back memory are mixed with Device loads. | |
309 | ||
310 | The workaround is to promote device loads to use Load-Acquire | |
311 | semantics. | |
312 | Please note that this does not necessarily enable the workaround, | |
313 | as it depends on the alternative framework, which will only patch | |
314 | the kernel if an affected CPU is detected. | |
315 | ||
316 | If unsure, say Y. | |
317 | ||
905e8c5d WD |
318 | config ARM64_ERRATUM_845719 |
319 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
320 | depends on COMPAT | |
321 | default y | |
322 | help | |
323 | This option adds an alternative code sequence to work around ARM | |
324 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
325 | ||
326 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
327 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
328 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
329 | might return incorrect data. | |
330 | ||
331 | The workaround is to write the contextidr_el1 register on exception | |
332 | return to a 32-bit task. | |
333 | Please note that this does not necessarily enable the workaround, | |
334 | as it depends on the alternative framework, which will only patch | |
335 | the kernel if an affected CPU is detected. | |
336 | ||
337 | If unsure, say Y. | |
338 | ||
df057cc7 WD |
339 | config ARM64_ERRATUM_843419 |
340 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
341 | depends on MODULES | |
342 | default y | |
343 | help | |
344 | This option builds kernel modules using the large memory model in | |
345 | order to avoid the use of the ADRP instruction, which can cause | |
346 | a subsequent memory access to use an incorrect address on Cortex-A53 | |
347 | parts up to r0p4. | |
348 | ||
349 | Note that the kernel itself must be linked with a version of ld | |
350 | which fixes potentially affected ADRP instructions through the | |
351 | use of veneers. | |
352 | ||
353 | If unsure, say Y. | |
354 | ||
94100970 RR |
355 | config CAVIUM_ERRATUM_22375 |
356 | bool "Cavium erratum 22375, 24313" | |
357 | default y | |
358 | help | |
359 | Enable workaround for erratum 22375, 24313. | |
360 | ||
361 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
362 | with small impact affecting only ITS table allocation. | |
363 | ||
364 | erratum 22375: only alloc 8MB table size | |
365 | erratum 24313: ignore memory access type | |
366 | ||
367 | The fixes are in ITS initialization and basically ignore memory access | |
368 | type and table size provided by the TYPER and BASER registers. | |
369 | ||
370 | If unsure, say Y. | |
371 | ||
6d4e11c5 RR |
372 | config CAVIUM_ERRATUM_23154 |
373 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" | |
374 | default y | |
375 | help | |
376 | The gicv3 of ThunderX requires a modified version for | |
377 | reading the IAR status to ensure data synchronization | |
378 | (access to icc_iar1_el1 is not sync'ed before and after). | |
379 | ||
380 | If unsure, say Y. | |
381 | ||
c0a01b84 AP |
382 | endmenu |
383 | ||
384 | ||
e41ceed0 JL |
385 | choice |
386 | prompt "Page size" | |
387 | default ARM64_4K_PAGES | |
388 | help | |
389 | Page size (translation granule) configuration. | |
390 | ||
391 | config ARM64_4K_PAGES | |
392 | bool "4KB" | |
393 | help | |
394 | This feature enables 4KB pages support. | |
395 | ||
44eaacf1 SP |
396 | config ARM64_16K_PAGES |
397 | bool "16KB" | |
398 | help | |
399 | The system will use 16KB pages support. AArch32 emulation | |
400 | requires applications compiled with 16K (or a multiple of 16K) | |
401 | aligned segments. | |
402 | ||
8c2c3df3 | 403 | config ARM64_64K_PAGES |
e41ceed0 | 404 | bool "64KB" |
8c2c3df3 CM |
405 | help |
406 | This feature enables 64KB pages support (4KB by default) | |
407 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
408 | look-up. AArch32 emulation requires applications compiled |
409 | with 64K aligned segments. | |
8c2c3df3 | 410 | |
e41ceed0 JL |
411 | endchoice |
412 | ||
413 | choice | |
414 | prompt "Virtual address space size" | |
415 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 416 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
417 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
418 | help | |
419 | Allows choosing one of multiple possible virtual address | |
420 | space sizes. The level of translation table is determined by | |
421 | a combination of page size and virtual address space size. | |
422 | ||
21539939 | 423 | config ARM64_VA_BITS_36 |
56a3f30e | 424 | bool "36-bit" if EXPERT |
21539939 SP |
425 | depends on ARM64_16K_PAGES |
426 | ||
e41ceed0 JL |
427 | config ARM64_VA_BITS_39 |
428 | bool "39-bit" | |
429 | depends on ARM64_4K_PAGES | |
430 | ||
431 | config ARM64_VA_BITS_42 | |
432 | bool "42-bit" | |
433 | depends on ARM64_64K_PAGES | |
434 | ||
44eaacf1 SP |
435 | config ARM64_VA_BITS_47 |
436 | bool "47-bit" | |
437 | depends on ARM64_16K_PAGES | |
438 | ||
c79b954b JL |
439 | config ARM64_VA_BITS_48 |
440 | bool "48-bit" | |
c79b954b | 441 | |
e41ceed0 JL |
442 | endchoice |
443 | ||
444 | config ARM64_VA_BITS | |
445 | int | |
21539939 | 446 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
447 | default 39 if ARM64_VA_BITS_39 |
448 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 449 | default 47 if ARM64_VA_BITS_47 |
c79b954b | 450 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 451 | |
a872013d WD |
452 | config CPU_BIG_ENDIAN |
453 | bool "Build big-endian kernel" | |
454 | help | |
455 | Say Y if you plan on running a kernel in big-endian mode. | |
456 | ||
f6e763b9 MB |
457 | config SCHED_MC |
458 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
459 | help |
460 | Multi-core scheduler support improves the CPU scheduler's decision | |
461 | making when dealing with multi-core CPU chips at a cost of slightly | |
462 | increased overhead in some places. If unsure say N here. | |
463 | ||
464 | config SCHED_SMT | |
465 | bool "SMT scheduler support" | |
f6e763b9 MB |
466 | help |
467 | Improves the CPU scheduler's decision making when dealing with | |
468 | MultiThreading at a cost of slightly increased overhead in some | |
469 | places. If unsure say N here. | |
470 | ||
8c2c3df3 | 471 | config NR_CPUS |
62aa9655 GK |
472 | int "Maximum number of CPUs (2-4096)" |
473 | range 2 4096 | |
15942853 | 474 | # These have to remain sorted largest to smallest |
e3672649 | 475 | default "64" |
8c2c3df3 | 476 | |
9327e2c6 MR |
477 | config HOTPLUG_CPU |
478 | bool "Support for hot-pluggable CPUs" | |
217d453d | 479 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
480 | help |
481 | Say Y here to experiment with turning CPUs off and on. CPUs | |
482 | can be controlled through /sys/devices/system/cpu. | |
483 | ||
8c2c3df3 | 484 | source kernel/Kconfig.preempt |
f90df5e2 | 485 | source kernel/Kconfig.hz |
8c2c3df3 CM |
486 | |
487 | config ARCH_HAS_HOLES_MEMORYMODEL | |
488 | def_bool y if SPARSEMEM | |
489 | ||
490 | config ARCH_SPARSEMEM_ENABLE | |
491 | def_bool y | |
492 | select SPARSEMEM_VMEMMAP_ENABLE | |
493 | ||
494 | config ARCH_SPARSEMEM_DEFAULT | |
495 | def_bool ARCH_SPARSEMEM_ENABLE | |
496 | ||
497 | config ARCH_SELECT_MEMORY_MODEL | |
498 | def_bool ARCH_SPARSEMEM_ENABLE | |
499 | ||
500 | config HAVE_ARCH_PFN_VALID | |
501 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
502 | ||
503 | config HW_PERF_EVENTS | |
6475b2d8 MR |
504 | def_bool y |
505 | depends on ARM_PMU | |
8c2c3df3 | 506 | |
084bd298 SC |
507 | config SYS_SUPPORTS_HUGETLBFS |
508 | def_bool y | |
509 | ||
510 | config ARCH_WANT_GENERAL_HUGETLB | |
511 | def_bool y | |
512 | ||
513 | config ARCH_WANT_HUGE_PMD_SHARE | |
21539939 | 514 | def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
084bd298 | 515 | |
af074848 SC |
516 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
517 | def_bool y | |
518 | ||
a41dc0e8 CM |
519 | config ARCH_HAS_CACHE_LINE_SIZE |
520 | def_bool y | |
521 | ||
8c2c3df3 CM |
522 | source "mm/Kconfig" |
523 | ||
a1ae65b2 AT |
524 | config SECCOMP |
525 | bool "Enable seccomp to safely compute untrusted bytecode" | |
526 | ---help--- | |
527 | This kernel feature is useful for number crunching applications | |
528 | that may need to compute untrusted bytecode during their | |
529 | execution. By using pipes or other transports made available to | |
530 | the process as file descriptors supporting the read/write | |
531 | syscalls, it's possible to isolate those applications in | |
532 | their own address space using seccomp. Once seccomp is | |
533 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
534 | and the task is only allowed to execute a few safe syscalls | |
535 | defined by each seccomp mode. | |
536 | ||
aa42aa13 SS |
537 | config XEN_DOM0 |
538 | def_bool y | |
539 | depends on XEN | |
540 | ||
541 | config XEN | |
c2ba1f7d | 542 | bool "Xen guest support on ARM64" |
aa42aa13 | 543 | depends on ARM64 && OF |
83862ccf | 544 | select SWIOTLB_XEN |
aa42aa13 SS |
545 | help |
546 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
547 | ||
d03bb145 SC |
548 | config FORCE_MAX_ZONEORDER |
549 | int | |
550 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
44eaacf1 | 551 | default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) |
d03bb145 | 552 | default "11" |
44eaacf1 SP |
553 | help |
554 | The kernel memory allocator divides physically contiguous memory | |
555 | blocks into "zones", where each zone is a power of two number of | |
556 | pages. This option selects the largest power of two that the kernel | |
557 | keeps in the memory allocator. If you need to allocate very large | |
558 | blocks of physically contiguous memory, then you may need to | |
559 | increase this value. | |
560 | ||
561 | This config option is actually maximum order plus one. For example, | |
562 | a value of 11 means that the largest free memory block is 2^10 pages. | |
563 | ||
564 | We make sure that we can allocate upto a HugePage size for each configuration. | |
565 | Hence we have : | |
566 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 | |
567 | ||
568 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us | |
569 | 4M allocations matching the default size used by generic code. | |
d03bb145 | 570 | |
1b907f46 WD |
571 | menuconfig ARMV8_DEPRECATED |
572 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
573 | depends on COMPAT | |
574 | help | |
575 | Legacy software support may require certain instructions | |
576 | that have been deprecated or obsoleted in the architecture. | |
577 | ||
578 | Enable this config to enable selective emulation of these | |
579 | features. | |
580 | ||
581 | If unsure, say Y | |
582 | ||
583 | if ARMV8_DEPRECATED | |
584 | ||
585 | config SWP_EMULATION | |
586 | bool "Emulate SWP/SWPB instructions" | |
587 | help | |
588 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
589 | they are always undefined. Say Y here to enable software | |
590 | emulation of these instructions for userspace using LDXR/STXR. | |
591 | ||
592 | In some older versions of glibc [<=2.8] SWP is used during futex | |
593 | trylock() operations with the assumption that the code will not | |
594 | be preempted. This invalid assumption may be more likely to fail | |
595 | with SWP emulation enabled, leading to deadlock of the user | |
596 | application. | |
597 | ||
598 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
599 | on an external transaction monitoring block called a global | |
600 | monitor to maintain update atomicity. If your system does not | |
601 | implement a global monitor, this option can cause programs that | |
602 | perform SWP operations to uncached memory to deadlock. | |
603 | ||
604 | If unsure, say Y | |
605 | ||
606 | config CP15_BARRIER_EMULATION | |
607 | bool "Emulate CP15 Barrier instructions" | |
608 | help | |
609 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
610 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
611 | strongly recommended to use the ISB, DSB, and DMB | |
612 | instructions instead. | |
613 | ||
614 | Say Y here to enable software emulation of these | |
615 | instructions for AArch32 userspace code. When this option is | |
616 | enabled, CP15 barrier usage is traced which can help | |
617 | identify software that needs updating. | |
618 | ||
619 | If unsure, say Y | |
620 | ||
2d888f48 SP |
621 | config SETEND_EMULATION |
622 | bool "Emulate SETEND instruction" | |
623 | help | |
624 | The SETEND instruction alters the data-endianness of the | |
625 | AArch32 EL0, and is deprecated in ARMv8. | |
626 | ||
627 | Say Y here to enable software emulation of the instruction | |
628 | for AArch32 userspace code. | |
629 | ||
630 | Note: All the cpus on the system must have mixed endian support at EL0 | |
631 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
632 | endian - is hotplugged in after this feature has been enabled, there could | |
633 | be unexpected results in the applications. | |
634 | ||
635 | If unsure, say Y | |
1b907f46 WD |
636 | endif |
637 | ||
0e4a0709 WD |
638 | menu "ARMv8.1 architectural features" |
639 | ||
640 | config ARM64_HW_AFDBM | |
641 | bool "Support for hardware updates of the Access and Dirty page flags" | |
642 | default y | |
643 | help | |
644 | The ARMv8.1 architecture extensions introduce support for | |
645 | hardware updates of the access and dirty information in page | |
646 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
647 | capable processors, accesses to pages with PTE_AF cleared will | |
648 | set this bit instead of raising an access flag fault. | |
649 | Similarly, writes to read-only pages with the DBM bit set will | |
650 | clear the read-only bit (AP[2]) instead of raising a | |
651 | permission fault. | |
652 | ||
653 | Kernels built with this configuration option enabled continue | |
654 | to work on pre-ARMv8.1 hardware and the performance impact is | |
655 | minimal. If unsure, say Y. | |
656 | ||
657 | config ARM64_PAN | |
658 | bool "Enable support for Privileged Access Never (PAN)" | |
659 | default y | |
660 | help | |
661 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
662 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
663 | memory directly. | |
664 | ||
665 | Choosing this option will cause any unprotected (not using | |
666 | copy_to_user et al) memory access to fail with a permission fault. | |
667 | ||
668 | The feature is detected at runtime, and will remain as a 'nop' | |
669 | instruction if the cpu does not implement the feature. | |
670 | ||
671 | config ARM64_LSE_ATOMICS | |
672 | bool "Atomic instructions" | |
673 | help | |
674 | As part of the Large System Extensions, ARMv8.1 introduces new | |
675 | atomic instructions that are designed specifically to scale in | |
676 | very large systems. | |
677 | ||
678 | Say Y here to make use of these instructions for the in-kernel | |
679 | atomic routines. This incurs a small overhead on CPUs that do | |
680 | not support these instructions and requires the kernel to be | |
681 | built with binutils >= 2.25. | |
682 | ||
683 | endmenu | |
684 | ||
8c2c3df3 CM |
685 | endmenu |
686 | ||
687 | menu "Boot options" | |
688 | ||
689 | config CMDLINE | |
690 | string "Default kernel command string" | |
691 | default "" | |
692 | help | |
693 | Provide a set of default command-line options at build time by | |
694 | entering them here. As a minimum, you should specify the the | |
695 | root device (e.g. root=/dev/nfs). | |
696 | ||
697 | config CMDLINE_FORCE | |
698 | bool "Always use the default kernel command string" | |
699 | help | |
700 | Always use the default kernel command string, even if the boot | |
701 | loader passes other arguments to the kernel. | |
702 | This is useful if you cannot or don't want to change the | |
703 | command-line options your boot loader passes to the kernel. | |
704 | ||
f4f75ad5 AB |
705 | config EFI_STUB |
706 | bool | |
707 | ||
f84d0275 MS |
708 | config EFI |
709 | bool "UEFI runtime support" | |
710 | depends on OF && !CPU_BIG_ENDIAN | |
711 | select LIBFDT | |
712 | select UCS2_STRING | |
713 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 714 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
715 | select EFI_STUB |
716 | select EFI_ARMSTUB | |
f84d0275 MS |
717 | default y |
718 | help | |
719 | This option provides support for runtime services provided | |
720 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
721 | clock, and platform reset). A UEFI stub is also provided to |
722 | allow the kernel to be booted as an EFI application. This | |
723 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 724 | |
d1ae8c00 YL |
725 | config DMI |
726 | bool "Enable support for SMBIOS (DMI) tables" | |
727 | depends on EFI | |
728 | default y | |
729 | help | |
730 | This enables SMBIOS/DMI feature for systems. | |
731 | ||
732 | This option is only useful on systems that have UEFI firmware. | |
733 | However, even with this option, the resultant kernel should | |
734 | continue to boot on existing non-UEFI platforms. | |
735 | ||
8c2c3df3 CM |
736 | endmenu |
737 | ||
738 | menu "Userspace binary formats" | |
739 | ||
740 | source "fs/Kconfig.binfmt" | |
741 | ||
742 | config COMPAT | |
743 | bool "Kernel support for 32-bit EL0" | |
755e70b7 | 744 | depends on ARM64_4K_PAGES || EXPERT |
8c2c3df3 | 745 | select COMPAT_BINFMT_ELF |
af1839eb | 746 | select HAVE_UID16 |
84b9e9b4 | 747 | select OLD_SIGSUSPEND3 |
51682036 | 748 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
749 | help |
750 | This option enables support for a 32-bit EL0 running under a 64-bit | |
751 | kernel at EL1. AArch32-specific components such as system calls, | |
752 | the user helper functions, VFP support and the ptrace interface are | |
753 | handled appropriately by the kernel. | |
754 | ||
44eaacf1 SP |
755 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware |
756 | that you will only be able to execute AArch32 binaries that were compiled | |
757 | with page size aligned segments. | |
a8fcd8b1 | 758 | |
8c2c3df3 CM |
759 | If you want to execute 32-bit userspace applications, say Y. |
760 | ||
761 | config SYSVIPC_COMPAT | |
762 | def_bool y | |
763 | depends on COMPAT && SYSVIPC | |
764 | ||
765 | endmenu | |
766 | ||
166936ba LP |
767 | menu "Power management options" |
768 | ||
769 | source "kernel/power/Kconfig" | |
770 | ||
771 | config ARCH_SUSPEND_POSSIBLE | |
772 | def_bool y | |
773 | ||
166936ba LP |
774 | endmenu |
775 | ||
1307220d LP |
776 | menu "CPU Power Management" |
777 | ||
778 | source "drivers/cpuidle/Kconfig" | |
779 | ||
52e7e816 RH |
780 | source "drivers/cpufreq/Kconfig" |
781 | ||
782 | endmenu | |
783 | ||
8c2c3df3 CM |
784 | source "net/Kconfig" |
785 | ||
786 | source "drivers/Kconfig" | |
787 | ||
f84d0275 MS |
788 | source "drivers/firmware/Kconfig" |
789 | ||
b6a02173 GG |
790 | source "drivers/acpi/Kconfig" |
791 | ||
8c2c3df3 CM |
792 | source "fs/Kconfig" |
793 | ||
c3eb5b14 MZ |
794 | source "arch/arm64/kvm/Kconfig" |
795 | ||
8c2c3df3 CM |
796 | source "arch/arm64/Kconfig.debug" |
797 | ||
798 | source "security/Kconfig" | |
799 | ||
800 | source "crypto/Kconfig" | |
2c98833a AB |
801 | if CRYPTO |
802 | source "arch/arm64/crypto/Kconfig" | |
803 | endif | |
8c2c3df3 CM |
804 | |
805 | source "lib/Kconfig" |