[deliverable/linux.git] / arch / arm64 / include / asm / arch_timer.h

/*
 * arch/arm64/include/asm/arch_timer.h
 *
 * Copyright (C) 2012 ARM Ltd.
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_ARCH_TIMER_H
#define __ASM_ARCH_TIMER_H

#include <asm/barrier.h>

#include <linux/init.h>
#include <linux/types.h>

#include <clocksource/arm_arch_timer.h>

/*
 * These register accessors are marked inline so the compiler can
 * nicely work out which register we want, and chuck away the rest of
 * the code.
 */
static __always_inline
void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
{
	if (access == ARCH_TIMER_PHYS_ACCESS) {
		switch (reg) {
		case ARCH_TIMER_REG_CTRL:
			asm volatile("msr cntp_ctl_el0,  %0" : : "r" (val));
			break;
		case ARCH_TIMER_REG_TVAL:
			asm volatile("msr cntp_tval_el0, %0" : : "r" (val));
			break;
		}
	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
		switch (reg) {
		case ARCH_TIMER_REG_CTRL:
			asm volatile("msr cntv_ctl_el0,  %0" : : "r" (val));
			break;
		case ARCH_TIMER_REG_TVAL:
			asm volatile("msr cntv_tval_el0, %0" : : "r" (val));
			break;
		}
	}

	isb();
}

static __always_inline
u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
{
	u32 val;

	if (access == ARCH_TIMER_PHYS_ACCESS) {
		switch (reg) {
		case ARCH_TIMER_REG_CTRL:
			asm volatile("mrs %0,  cntp_ctl_el0" : "=r" (val));
			break;
		case ARCH_TIMER_REG_TVAL:
			asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
			break;
		}
	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
		switch (reg) {
		case ARCH_TIMER_REG_CTRL:
			asm volatile("mrs %0,  cntv_ctl_el0" : "=r" (val));
			break;
		case ARCH_TIMER_REG_TVAL:
			asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
			break;
		}
	}

	return val;
}

static inline u32 arch_timer_get_cntfrq(void)
{
	u32 val;
	asm volatile("mrs %0,   cntfrq_el0" : "=r" (val));
	return val;
}

static inline void arch_counter_set_user_access(void)
{
	u32 cntkctl;

	asm volatile("mrs	%0, cntkctl_el1" : "=r" (cntkctl));

	/* Disable user access to the timers and the physical counter */
	cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
			| ARCH_TIMER_USR_VT_ACCESS_EN
			| ARCH_TIMER_USR_PCT_ACCESS_EN);

	/* Enable user access to the virtual counter */
	cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;

	asm volatile("msr	cntkctl_el1, %0" : : "r" (cntkctl));
}

static inline u64 arch_counter_get_cntvct(void)
{
	u64 cval;

	isb();
	asm volatile("mrs %0, cntvct_el0" : "=r" (cval));

	return cval;
}

static inline int arch_timer_arch_init(void)
{
	return 0;
}

#endif
Commit	Line	Data
1aee5d7a MR	1	/*
	2	* arch/arm64/include/asm/arch_timer.h
	3	*
	4	* Copyright (C) 2012 ARM Ltd.
	5	* Author: Marc Zyngier <marc.zyngier@arm.com>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#ifndef __ASM_ARCH_TIMER_H
	20	#define __ASM_ARCH_TIMER_H
	21
	22	#include <asm/barrier.h>
	23
	24	#include <linux/init.h>
	25	#include <linux/types.h>
	26
	27	#include <clocksource/arm_arch_timer.h>
	28
e09f3cc0 SB	29	/*
	30	* These register accessors are marked inline so the compiler can
	31	* nicely work out which register we want, and chuck away the rest of
	32	* the code.
	33	*/
	34	static __always_inline
60faddf6	35	void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
1aee5d7a MR	36	{
	37	if (access == ARCH_TIMER_PHYS_ACCESS) {
	38	switch (reg) {
	39	case ARCH_TIMER_REG_CTRL:
	40	asm volatile("msr cntp_ctl_el0, %0" : : "r" (val));
	41	break;
	42	case ARCH_TIMER_REG_TVAL:
	43	asm volatile("msr cntp_tval_el0, %0" : : "r" (val));
	44	break;
1aee5d7a MR	45	}
	46	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
	47	switch (reg) {
	48	case ARCH_TIMER_REG_CTRL:
	49	asm volatile("msr cntv_ctl_el0, %0" : : "r" (val));
	50	break;
	51	case ARCH_TIMER_REG_TVAL:
	52	asm volatile("msr cntv_tval_el0, %0" : : "r" (val));
	53	break;
1aee5d7a	54	}
1aee5d7a MR	55	}
	56
	57	isb();
	58	}
	59
e09f3cc0	60	static __always_inline
60faddf6	61	u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
1aee5d7a MR	62	{
	63	u32 val;
	64
	65	if (access == ARCH_TIMER_PHYS_ACCESS) {
	66	switch (reg) {
	67	case ARCH_TIMER_REG_CTRL:
	68	asm volatile("mrs %0, cntp_ctl_el0" : "=r" (val));
	69	break;
	70	case ARCH_TIMER_REG_TVAL:
	71	asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
	72	break;
1aee5d7a MR	73	}
	74	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
	75	switch (reg) {
	76	case ARCH_TIMER_REG_CTRL:
	77	asm volatile("mrs %0, cntv_ctl_el0" : "=r" (val));
	78	break;
	79	case ARCH_TIMER_REG_TVAL:
	80	asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
	81	break;
1aee5d7a	82	}
1aee5d7a MR	83	}
	84
	85	return val;
	86	}
	87
	88	static inline u32 arch_timer_get_cntfrq(void)
	89	{
	90	u32 val;
	91	asm volatile("mrs %0, cntfrq_el0" : "=r" (val));
	92	return val;
	93	}
	94
b8c6453a	95	static inline void arch_counter_set_user_access(void)
1aee5d7a MR	96	{
	97	u32 cntkctl;
	98
1aee5d7a	99	asm volatile("mrs %0, cntkctl_el1" : "=r" (cntkctl));
1aee5d7a	100
28061758 SK	101	/* Disable user access to the timers and the physical counter */
	102	cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
	103	\| ARCH_TIMER_USR_VT_ACCESS_EN
	104	\| ARCH_TIMER_USR_PCT_ACCESS_EN);
	105
	106	/* Enable user access to the virtual counter */
	107	cntkctl \|= ARCH_TIMER_USR_VCT_ACCESS_EN;
	108
1aee5d7a MR	109	asm volatile("msr cntkctl_el1, %0" : : "r" (cntkctl));
	110	}
	111
1aee5d7a MR	112	static inline u64 arch_counter_get_cntvct(void)
	113	{
	114	u64 cval;
	115
	116	isb();
	117	asm volatile("mrs %0, cntvct_el0" : "=r" (cval));
	118
	119	return cval;
	120	}
	121
0583fe47 RH	122	static inline int arch_timer_arch_init(void)
	123	{
	124	return 0;
	125	}
	126
1aee5d7a	127	#endif