[deliverable/linux.git] / arch / arm64 / include / asm / ptrace.h

/*
 * Based on arch/arm/include/asm/ptrace.h
 *
 * Copyright (C) 1996-2003 Russell King
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_PTRACE_H
#define __ASM_PTRACE_H

#include <uapi/asm/ptrace.h>

/* AArch32-specific ptrace requests */
#define COMPAT_PTRACE_GETREGS		12
#define COMPAT_PTRACE_SETREGS		13
#define COMPAT_PTRACE_GET_THREAD_AREA	22
#define COMPAT_PTRACE_SET_SYSCALL	23
#define COMPAT_PTRACE_GETVFPREGS	27
#define COMPAT_PTRACE_SETVFPREGS	28
#define COMPAT_PTRACE_GETHBPREGS	29
#define COMPAT_PTRACE_SETHBPREGS	30

/* AArch32 CPSR bits */
#define COMPAT_PSR_MODE_MASK	0x0000001f
#define COMPAT_PSR_MODE_USR	0x00000010
#define COMPAT_PSR_MODE_FIQ	0x00000011
#define COMPAT_PSR_MODE_IRQ	0x00000012
#define COMPAT_PSR_MODE_SVC	0x00000013
#define COMPAT_PSR_MODE_ABT	0x00000017
#define COMPAT_PSR_MODE_HYP	0x0000001a
#define COMPAT_PSR_MODE_UND	0x0000001b
#define COMPAT_PSR_MODE_SYS	0x0000001f
#define COMPAT_PSR_T_BIT	0x00000020
#define COMPAT_PSR_E_BIT	0x00000200
#define COMPAT_PSR_F_BIT	0x00000040
#define COMPAT_PSR_I_BIT	0x00000080
#define COMPAT_PSR_A_BIT	0x00000100
#define COMPAT_PSR_E_BIT	0x00000200
#define COMPAT_PSR_J_BIT	0x01000000
#define COMPAT_PSR_Q_BIT	0x08000000
#define COMPAT_PSR_V_BIT	0x10000000
#define COMPAT_PSR_C_BIT	0x20000000
#define COMPAT_PSR_Z_BIT	0x40000000
#define COMPAT_PSR_N_BIT	0x80000000
#define COMPAT_PSR_IT_MASK	0x0600fc00	/* If-Then execution state mask */
/*
 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
 * process is located in memory.
 */
#define COMPAT_PT_TEXT_ADDR		0x10000
#define COMPAT_PT_DATA_ADDR		0x10004
#define COMPAT_PT_TEXT_END_ADDR		0x10008
#ifndef __ASSEMBLY__

/* sizeof(struct user) for AArch32 */
#define COMPAT_USER_SZ	296

/* Architecturally defined mapping between AArch32 and AArch64 registers */
#define compat_usr(x)	regs[(x)]
#define compat_sp	regs[13]
#define compat_lr	regs[14]
#define compat_sp_hyp	regs[15]
#define compat_sp_irq	regs[16]
#define compat_lr_irq	regs[17]
#define compat_sp_svc	regs[18]
#define compat_lr_svc	regs[19]
#define compat_sp_abt	regs[20]
#define compat_lr_abt	regs[21]
#define compat_sp_und	regs[22]
#define compat_lr_und	regs[23]
#define compat_r8_fiq	regs[24]
#define compat_r9_fiq	regs[25]
#define compat_r10_fiq	regs[26]
#define compat_r11_fiq	regs[27]
#define compat_r12_fiq	regs[28]
#define compat_sp_fiq	regs[29]
#define compat_lr_fiq	regs[30]

/*
 * This struct defines the way the registers are stored on the stack during an
 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
 */
struct pt_regs {
	union {
		struct user_pt_regs user_regs;
		struct {
			u64 regs[31];
			u64 sp;
			u64 pc;
			u64 pstate;
		};
	};
	u64 orig_x0;
	u64 syscallno;
};

#define arch_has_single_step()	(1)

#ifdef CONFIG_COMPAT
#define compat_thumb_mode(regs) \
	(((regs)->pstate & COMPAT_PSR_T_BIT))
#else
#define compat_thumb_mode(regs) (0)
#endif

#define user_mode(regs)	\
	(((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)

#define compat_user_mode(regs)	\
	(((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
	 (PSR_MODE32_BIT | PSR_MODE_EL0t))

#define processor_mode(regs) \
	((regs)->pstate & PSR_MODE_MASK)

#define interrupts_enabled(regs) \
	(!((regs)->pstate & PSR_I_BIT))

#define fast_interrupts_enabled(regs) \
	(!((regs)->pstate & PSR_F_BIT))

#define user_stack_pointer(regs) \
	((regs)->sp)

/*
 * Are the current registers suitable for user mode? (used to maintain
 * security in signal handlers)
 */
static inline int valid_user_regs(struct user_pt_regs *regs)
{
	if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) {
		regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT);

		/* The T bit is reserved for AArch64 */
		if (!(regs->pstate & PSR_MODE32_BIT))
			regs->pstate &= ~COMPAT_PSR_T_BIT;

		return 1;
	}

	/*
	 * Force PSR to something logical...
	 */
	regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \
			COMPAT_PSR_T_BIT | PSR_MODE32_BIT;

	if (!(regs->pstate & PSR_MODE32_BIT)) {
		regs->pstate &= ~COMPAT_PSR_T_BIT;
		regs->pstate |= PSR_MODE_EL0t;
	}

	return 0;
}

#define instruction_pointer(regs)	(regs)->pc

#ifdef CONFIG_SMP
extern unsigned long profile_pc(struct pt_regs *regs);
#else
#define profile_pc(regs) instruction_pointer(regs)
#endif

#endif /* __ASSEMBLY__ */
#endif
Commit	Line	Data
60ffc30d CM	1	/*
	2	* Based on arch/arm/include/asm/ptrace.h
	3	*
	4	* Copyright (C) 1996-2003 Russell King
	5	* Copyright (C) 2012 ARM Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#ifndef __ASM_PTRACE_H
	20	#define __ASM_PTRACE_H
	21
4262a727	22	#include <uapi/asm/ptrace.h>
60ffc30d	23
60ffc30d	24	/* AArch32-specific ptrace requests */
27aa55c5 WD	25	#define COMPAT_PTRACE_GETREGS 12
	26	#define COMPAT_PTRACE_SETREGS 13
	27	#define COMPAT_PTRACE_GET_THREAD_AREA 22
	28	#define COMPAT_PTRACE_SET_SYSCALL 23
60ffc30d CM	29	#define COMPAT_PTRACE_GETVFPREGS 27
60ffc30d CM	30	#define COMPAT_PTRACE_SETVFPREGS 28
27aa55c5 WD	31	#define COMPAT_PTRACE_GETHBPREGS 29
27aa55c5 WD	32	#define COMPAT_PTRACE_SETHBPREGS 30
9ec218b8 MZ	33
	34	/* AArch32 CPSR bits */
	35	#define COMPAT_PSR_MODE_MASK 0x0000001f
60ffc30d	36	#define COMPAT_PSR_MODE_USR 0x00000010
9ec218b8 MZ	37	#define COMPAT_PSR_MODE_FIQ 0x00000011
	38	#define COMPAT_PSR_MODE_IRQ 0x00000012
	39	#define COMPAT_PSR_MODE_SVC 0x00000013
	40	#define COMPAT_PSR_MODE_ABT 0x00000017
	41	#define COMPAT_PSR_MODE_HYP 0x0000001a
	42	#define COMPAT_PSR_MODE_UND 0x0000001b
	43	#define COMPAT_PSR_MODE_SYS 0x0000001f
60ffc30d	44	#define COMPAT_PSR_T_BIT 0x00000020
a795a38e	45	#define COMPAT_PSR_E_BIT 0x00000200
10a3cc2f MZ	46	#define COMPAT_PSR_F_BIT 0x00000040
	47	#define COMPAT_PSR_I_BIT 0x00000080
	48	#define COMPAT_PSR_A_BIT 0x00000100
	49	#define COMPAT_PSR_E_BIT 0x00000200
	50	#define COMPAT_PSR_J_BIT 0x01000000
	51	#define COMPAT_PSR_Q_BIT 0x08000000
	52	#define COMPAT_PSR_V_BIT 0x10000000
	53	#define COMPAT_PSR_C_BIT 0x20000000
	54	#define COMPAT_PSR_Z_BIT 0x40000000
	55	#define COMPAT_PSR_N_BIT 0x80000000
60ffc30d	56	#define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
60ffc30d CM	57	/*
	58	* These are 'magic' values for PTRACE_PEEKUSR that return info about where a
	59	* process is located in memory.
	60	*/
7606c37d CM	61	#define COMPAT_PT_TEXT_ADDR 0x10000
	62	#define COMPAT_PT_DATA_ADDR 0x10004
	63	#define COMPAT_PT_TEXT_END_ADDR 0x10008
60ffc30d CM	64	#ifndef __ASSEMBLY__
60ffc30d CM	65
60ffc30d CM	66	/* sizeof(struct user) for AArch32 */
60ffc30d CM	67	#define COMPAT_USER_SZ 296
88483ec6 MZ	68
	69	/* Architecturally defined mapping between AArch32 and AArch64 registers */
	70	#define compat_usr(x) regs[(x)]
60ffc30d	71	#define compat_sp regs[13]
60ffc30d	72	#define compat_lr regs[14]
88483ec6 MZ	73	#define compat_sp_hyp regs[15]
	74	#define compat_sp_irq regs[16]
	75	#define compat_lr_irq regs[17]
	76	#define compat_sp_svc regs[18]
	77	#define compat_lr_svc regs[19]
	78	#define compat_sp_abt regs[20]
	79	#define compat_lr_abt regs[21]
	80	#define compat_sp_und regs[22]
	81	#define compat_lr_und regs[23]
	82	#define compat_r8_fiq regs[24]
	83	#define compat_r9_fiq regs[25]
	84	#define compat_r10_fiq regs[26]
	85	#define compat_r11_fiq regs[27]
	86	#define compat_r12_fiq regs[28]
	87	#define compat_sp_fiq regs[29]
	88	#define compat_lr_fiq regs[30]
60ffc30d CM	89
	90	/*
	91	* This struct defines the way the registers are stored on the stack during an
	92	* exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
	93	* stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
	94	*/
	95	struct pt_regs {
	96	union {
	97	struct user_pt_regs user_regs;
	98	struct {
	99	u64 regs[31];
	100	u64 sp;
	101	u64 pc;
	102	u64 pstate;
	103	};
	104	};
	105	u64 orig_x0;
	106	u64 syscallno;
	107	};
	108
	109	#define arch_has_single_step() (1)
	110
	111	#ifdef CONFIG_COMPAT
	112	#define compat_thumb_mode(regs) \
	113	(((regs)->pstate & COMPAT_PSR_T_BIT))
	114	#else
	115	#define compat_thumb_mode(regs) (0)
	116	#endif
	117
	118	#define user_mode(regs) \
	119	(((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
	120
	121	#define compat_user_mode(regs) \
	122	(((regs)->pstate & (PSR_MODE32_BIT \| PSR_MODE_MASK)) == \
	123	(PSR_MODE32_BIT \| PSR_MODE_EL0t))
	124
	125	#define processor_mode(regs) \
	126	((regs)->pstate & PSR_MODE_MASK)
	127
	128	#define interrupts_enabled(regs) \
	129	(!((regs)->pstate & PSR_I_BIT))
	130
	131	#define fast_interrupts_enabled(regs) \
	132	(!((regs)->pstate & PSR_F_BIT))
	133
	134	#define user_stack_pointer(regs) \
	135	((regs)->sp)
	136
	137	/*
	138	* Are the current registers suitable for user mode? (used to maintain
	139	* security in signal handlers)
	140	*/
	141	static inline int valid_user_regs(struct user_pt_regs *regs)
	142	{
	143	if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) {
	144	regs->pstate &= ~(PSR_F_BIT \| PSR_A_BIT);
	145
	146	/* The T bit is reserved for AArch64 */
	147	if (!(regs->pstate & PSR_MODE32_BIT))
	148	regs->pstate &= ~COMPAT_PSR_T_BIT;
	149
	150	return 1;
	151	}
	152
153	/*
154	* Force PSR to something logical...
155	*/
156	regs->pstate &= PSR_f \| PSR_s \| (PSR_x & ~PSR_A_BIT) \| \
157	COMPAT_PSR_T_BIT \| PSR_MODE32_BIT;
158
159	if (!(regs->pstate & PSR_MODE32_BIT)) {
160	regs->pstate &= ~COMPAT_PSR_T_BIT;
161	regs->pstate \|= PSR_MODE_EL0t;
162	}
163
164	return 0;
165	}
166
167	#define instruction_pointer(regs) (regs)->pc
168
169	#ifdef CONFIG_SMP
170	extern unsigned long profile_pc(struct pt_regs *regs);
171	#else
172	#define profile_pc(regs) instruction_pointer(regs)
173	#endif
174
60ffc30d	175	#endif /* __ASSEMBLY__ */
60ffc30d	176	#endif