projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 72c58395 CM |
1 | /* |
| 2 | * Macros for accessing system registers with older binutils. | |
| 3 | * | |
| 4 | * Copyright (C) 2014 ARM Ltd. | |
| 5 | * Author: Catalin Marinas <catalin.marinas@arm.com> | |
| 6 | * | |
| 7 | * This program is free software: you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | * GNU General Public License for more details. | |
| 15 | * | |
| 16 | * You should have received a copy of the GNU General Public License | |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
| 18 | */ | |
| 19 | ||
| 20 | #ifndef __ASM_SYSREG_H | |
| 21 | #define __ASM_SYSREG_H | |
| 22 | ||
| 870828e5 JM |
23 | #define SCTLR_EL1_CP15BEN (0x1 << 5) |
| 24 | #define SCTLR_EL1_SED (0x1 << 8) | |
| 25 | ||
| 9ded63aa SP |
26 | /* |
| 27 | * ARMv8 ARM reserves the following encoding for system registers: | |
| 28 | * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", | |
| 29 | * C5.2, version:ARM DDI 0487A.f) | |
| 30 | * [20-19] : Op0 | |
| 31 | * [18-16] : Op1 | |
| 32 | * [15-12] : CRn | |
| 33 | * [11-8] : CRm | |
| 34 | * [7-5] : Op2 | |
| 35 | */ | |
| 72c58395 | 36 | #define sys_reg(op0, op1, crn, crm, op2) \ |
| 9ded63aa | 37 | ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5)) |
| 72c58395 CM |
38 | |
| 39 | #ifdef __ASSEMBLY__ | |
| 40 | ||
| 41 | .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 | |
| 42 | .equ __reg_num_x\num, \num | |
| 43 | .endr | |
| 44 | .equ __reg_num_xzr, 31 | |
| 45 | ||
| 46 | .macro mrs_s, rt, sreg | |
| 9ded63aa | 47 | .inst 0xd5200000|(\sreg)|(__reg_num_\rt) |
| 72c58395 CM |
48 | .endm |
| 49 | ||
| 50 | .macro msr_s, sreg, rt | |
| 9ded63aa | 51 | .inst 0xd5000000|(\sreg)|(__reg_num_\rt) |
| 72c58395 CM |
52 | .endm |
| 53 | ||
| 54 | #else | |
| 55 | ||
| 56 | asm( | |
| 57 | " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" | |
| 58 | " .equ __reg_num_x\\num, \\num\n" | |
| 59 | " .endr\n" | |
| 60 | " .equ __reg_num_xzr, 31\n" | |
| 61 | "\n" | |
| 62 | " .macro mrs_s, rt, sreg\n" | |
| 9ded63aa | 63 | " .inst 0xd5200000|(\\sreg)|(__reg_num_\\rt)\n" |
| 72c58395 CM |
64 | " .endm\n" |
| 65 | "\n" | |
| 66 | " .macro msr_s, sreg, rt\n" | |
| 9ded63aa | 67 | " .inst 0xd5000000|(\\sreg)|(__reg_num_\\rt)\n" |
| 72c58395 CM |
68 | " .endm\n" |
| 69 | ); | |
| 70 | ||
| 870828e5 JM |
71 | static inline void config_sctlr_el1(u32 clear, u32 set) |
| 72 | { | |
| 73 | u32 val; | |
| 74 | ||
| 75 | asm volatile("mrs %0, sctlr_el1" : "=r" (val)); | |
| 76 | val &= ~clear; | |
| 77 | val |= set; | |
| 78 | asm volatile("msr sctlr_el1, %0" : : "r" (val)); | |
| 79 | } | |
| 72c58395 CM |
80 | #endif |
| 81 | ||
| 82 | #endif /* __ASM_SYSREG_H */ |