Commit | Line | Data |
---|---|---|
60ffc30d CM |
1 | /* |
2 | * Low-level exception handling code | |
3 | * | |
4 | * Copyright (C) 2012 ARM Ltd. | |
5 | * Authors: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * Will Deacon <will.deacon@arm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/linkage.h> | |
23 | ||
8d883b23 | 24 | #include <asm/alternative.h> |
60ffc30d CM |
25 | #include <asm/assembler.h> |
26 | #include <asm/asm-offsets.h> | |
905e8c5d | 27 | #include <asm/cpufeature.h> |
60ffc30d | 28 | #include <asm/errno.h> |
5c1ce6f7 | 29 | #include <asm/esr.h> |
8e23dacd | 30 | #include <asm/irq.h> |
60ffc30d CM |
31 | #include <asm/thread_info.h> |
32 | #include <asm/unistd.h> | |
33 | ||
6c81fe79 LB |
34 | /* |
35 | * Context tracking subsystem. Used to instrument transitions | |
36 | * between user and kernel mode. | |
37 | */ | |
38 | .macro ct_user_exit, syscall = 0 | |
39 | #ifdef CONFIG_CONTEXT_TRACKING | |
40 | bl context_tracking_user_exit | |
41 | .if \syscall == 1 | |
42 | /* | |
43 | * Save/restore needed during syscalls. Restore syscall arguments from | |
44 | * the values already saved on stack during kernel_entry. | |
45 | */ | |
46 | ldp x0, x1, [sp] | |
47 | ldp x2, x3, [sp, #S_X2] | |
48 | ldp x4, x5, [sp, #S_X4] | |
49 | ldp x6, x7, [sp, #S_X6] | |
50 | .endif | |
51 | #endif | |
52 | .endm | |
53 | ||
54 | .macro ct_user_enter | |
55 | #ifdef CONFIG_CONTEXT_TRACKING | |
56 | bl context_tracking_user_enter | |
57 | #endif | |
58 | .endm | |
59 | ||
60ffc30d CM |
60 | /* |
61 | * Bad Abort numbers | |
62 | *----------------- | |
63 | */ | |
64 | #define BAD_SYNC 0 | |
65 | #define BAD_IRQ 1 | |
66 | #define BAD_FIQ 2 | |
67 | #define BAD_ERROR 3 | |
68 | ||
69 | .macro kernel_entry, el, regsize = 64 | |
63648dd2 | 70 | sub sp, sp, #S_FRAME_SIZE |
60ffc30d CM |
71 | .if \regsize == 32 |
72 | mov w0, w0 // zero upper 32 bits of x0 | |
73 | .endif | |
63648dd2 WD |
74 | stp x0, x1, [sp, #16 * 0] |
75 | stp x2, x3, [sp, #16 * 1] | |
76 | stp x4, x5, [sp, #16 * 2] | |
77 | stp x6, x7, [sp, #16 * 3] | |
78 | stp x8, x9, [sp, #16 * 4] | |
79 | stp x10, x11, [sp, #16 * 5] | |
80 | stp x12, x13, [sp, #16 * 6] | |
81 | stp x14, x15, [sp, #16 * 7] | |
82 | stp x16, x17, [sp, #16 * 8] | |
83 | stp x18, x19, [sp, #16 * 9] | |
84 | stp x20, x21, [sp, #16 * 10] | |
85 | stp x22, x23, [sp, #16 * 11] | |
86 | stp x24, x25, [sp, #16 * 12] | |
87 | stp x26, x27, [sp, #16 * 13] | |
88 | stp x28, x29, [sp, #16 * 14] | |
89 | ||
60ffc30d CM |
90 | .if \el == 0 |
91 | mrs x21, sp_el0 | |
6cdf9c7c JL |
92 | mov tsk, sp |
93 | and tsk, tsk, #~(THREAD_SIZE - 1) // Ensure MDSCR_EL1.SS is clear, | |
2a283070 WD |
94 | ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug |
95 | disable_step_tsk x19, x20 // exceptions when scheduling. | |
49003a8d JM |
96 | |
97 | mov x29, xzr // fp pointed to user-space | |
60ffc30d CM |
98 | .else |
99 | add x21, sp, #S_FRAME_SIZE | |
100 | .endif | |
101 | mrs x22, elr_el1 | |
102 | mrs x23, spsr_el1 | |
103 | stp lr, x21, [sp, #S_LR] | |
104 | stp x22, x23, [sp, #S_PC] | |
105 | ||
106 | /* | |
107 | * Set syscallno to -1 by default (overridden later if real syscall). | |
108 | */ | |
109 | .if \el == 0 | |
110 | mvn x21, xzr | |
111 | str x21, [sp, #S_SYSCALLNO] | |
112 | .endif | |
113 | ||
6cdf9c7c JL |
114 | /* |
115 | * Set sp_el0 to current thread_info. | |
116 | */ | |
117 | .if \el == 0 | |
118 | msr sp_el0, tsk | |
119 | .endif | |
120 | ||
60ffc30d CM |
121 | /* |
122 | * Registers that may be useful after this macro is invoked: | |
123 | * | |
124 | * x21 - aborted SP | |
125 | * x22 - aborted PC | |
126 | * x23 - aborted PSTATE | |
127 | */ | |
128 | .endm | |
129 | ||
412fcb6c | 130 | .macro kernel_exit, el |
60ffc30d CM |
131 | ldp x21, x22, [sp, #S_PC] // load ELR, SPSR |
132 | .if \el == 0 | |
6c81fe79 | 133 | ct_user_enter |
60ffc30d | 134 | ldr x23, [sp, #S_SP] // load return stack pointer |
63648dd2 | 135 | msr sp_el0, x23 |
905e8c5d | 136 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
e28cabf1 DT |
137 | alternative_if_not ARM64_WORKAROUND_845719 |
138 | nop | |
139 | nop | |
905e8c5d | 140 | #ifdef CONFIG_PID_IN_CONTEXTIDR |
e28cabf1 DT |
141 | nop |
142 | #endif | |
143 | alternative_else | |
144 | tbz x22, #4, 1f | |
145 | #ifdef CONFIG_PID_IN_CONTEXTIDR | |
146 | mrs x29, contextidr_el1 | |
147 | msr contextidr_el1, x29 | |
905e8c5d | 148 | #else |
e28cabf1 | 149 | msr contextidr_el1, xzr |
905e8c5d | 150 | #endif |
e28cabf1 DT |
151 | 1: |
152 | alternative_endif | |
905e8c5d | 153 | #endif |
60ffc30d | 154 | .endif |
63648dd2 WD |
155 | msr elr_el1, x21 // set up the return data |
156 | msr spsr_el1, x22 | |
63648dd2 | 157 | ldp x0, x1, [sp, #16 * 0] |
63648dd2 WD |
158 | ldp x2, x3, [sp, #16 * 1] |
159 | ldp x4, x5, [sp, #16 * 2] | |
160 | ldp x6, x7, [sp, #16 * 3] | |
161 | ldp x8, x9, [sp, #16 * 4] | |
162 | ldp x10, x11, [sp, #16 * 5] | |
163 | ldp x12, x13, [sp, #16 * 6] | |
164 | ldp x14, x15, [sp, #16 * 7] | |
165 | ldp x16, x17, [sp, #16 * 8] | |
166 | ldp x18, x19, [sp, #16 * 9] | |
167 | ldp x20, x21, [sp, #16 * 10] | |
168 | ldp x22, x23, [sp, #16 * 11] | |
169 | ldp x24, x25, [sp, #16 * 12] | |
170 | ldp x26, x27, [sp, #16 * 13] | |
171 | ldp x28, x29, [sp, #16 * 14] | |
172 | ldr lr, [sp, #S_LR] | |
173 | add sp, sp, #S_FRAME_SIZE // restore sp | |
60ffc30d CM |
174 | eret // return to kernel |
175 | .endm | |
176 | ||
177 | .macro get_thread_info, rd | |
6cdf9c7c | 178 | mrs \rd, sp_el0 |
60ffc30d CM |
179 | .endm |
180 | ||
971c67ce | 181 | .macro irq_stack_entry |
8e23dacd JM |
182 | mov x19, sp // preserve the original sp |
183 | ||
8e23dacd | 184 | /* |
d224a69e JM |
185 | * Compare sp with the current thread_info, if the top |
186 | * ~(THREAD_SIZE - 1) bits match, we are on a task stack, and | |
187 | * should switch to the irq stack. | |
8e23dacd | 188 | */ |
d224a69e JM |
189 | and x25, x19, #~(THREAD_SIZE - 1) |
190 | cmp x25, tsk | |
191 | b.ne 9998f | |
8e23dacd | 192 | |
d224a69e | 193 | this_cpu_ptr irq_stack, x25, x26 |
8e23dacd JM |
194 | mov x26, #IRQ_STACK_START_SP |
195 | add x26, x25, x26 | |
d224a69e JM |
196 | |
197 | /* switch to the irq stack */ | |
8e23dacd JM |
198 | mov sp, x26 |
199 | ||
971c67ce JM |
200 | /* |
201 | * Add a dummy stack frame, this non-standard format is fixed up | |
202 | * by unwind_frame() | |
203 | */ | |
204 | stp x29, x19, [sp, #-16]! | |
8e23dacd | 205 | mov x29, sp |
8e23dacd JM |
206 | |
207 | 9998: | |
208 | .endm | |
209 | ||
210 | /* | |
211 | * x19 should be preserved between irq_stack_entry and | |
212 | * irq_stack_exit. | |
213 | */ | |
214 | .macro irq_stack_exit | |
215 | mov sp, x19 | |
216 | .endm | |
217 | ||
60ffc30d CM |
218 | /* |
219 | * These are the registers used in the syscall handler, and allow us to | |
220 | * have in theory up to 7 arguments to a function - x0 to x6. | |
221 | * | |
222 | * x7 is reserved for the system call number in 32-bit mode. | |
223 | */ | |
224 | sc_nr .req x25 // number of system calls | |
225 | scno .req x26 // syscall number | |
226 | stbl .req x27 // syscall table pointer | |
227 | tsk .req x28 // current thread_info | |
228 | ||
229 | /* | |
230 | * Interrupt handling. | |
231 | */ | |
232 | .macro irq_handler | |
8e23dacd | 233 | ldr_l x1, handle_arch_irq |
60ffc30d | 234 | mov x0, sp |
971c67ce | 235 | irq_stack_entry |
60ffc30d | 236 | blr x1 |
8e23dacd | 237 | irq_stack_exit |
60ffc30d CM |
238 | .endm |
239 | ||
240 | .text | |
241 | ||
242 | /* | |
243 | * Exception vectors. | |
244 | */ | |
60ffc30d CM |
245 | |
246 | .align 11 | |
247 | ENTRY(vectors) | |
248 | ventry el1_sync_invalid // Synchronous EL1t | |
249 | ventry el1_irq_invalid // IRQ EL1t | |
250 | ventry el1_fiq_invalid // FIQ EL1t | |
251 | ventry el1_error_invalid // Error EL1t | |
252 | ||
253 | ventry el1_sync // Synchronous EL1h | |
254 | ventry el1_irq // IRQ EL1h | |
255 | ventry el1_fiq_invalid // FIQ EL1h | |
256 | ventry el1_error_invalid // Error EL1h | |
257 | ||
258 | ventry el0_sync // Synchronous 64-bit EL0 | |
259 | ventry el0_irq // IRQ 64-bit EL0 | |
260 | ventry el0_fiq_invalid // FIQ 64-bit EL0 | |
261 | ventry el0_error_invalid // Error 64-bit EL0 | |
262 | ||
263 | #ifdef CONFIG_COMPAT | |
264 | ventry el0_sync_compat // Synchronous 32-bit EL0 | |
265 | ventry el0_irq_compat // IRQ 32-bit EL0 | |
266 | ventry el0_fiq_invalid_compat // FIQ 32-bit EL0 | |
267 | ventry el0_error_invalid_compat // Error 32-bit EL0 | |
268 | #else | |
269 | ventry el0_sync_invalid // Synchronous 32-bit EL0 | |
270 | ventry el0_irq_invalid // IRQ 32-bit EL0 | |
271 | ventry el0_fiq_invalid // FIQ 32-bit EL0 | |
272 | ventry el0_error_invalid // Error 32-bit EL0 | |
273 | #endif | |
274 | END(vectors) | |
275 | ||
276 | /* | |
277 | * Invalid mode handlers | |
278 | */ | |
279 | .macro inv_entry, el, reason, regsize = 64 | |
280 | kernel_entry el, \regsize | |
281 | mov x0, sp | |
282 | mov x1, #\reason | |
283 | mrs x2, esr_el1 | |
284 | b bad_mode | |
285 | .endm | |
286 | ||
287 | el0_sync_invalid: | |
288 | inv_entry 0, BAD_SYNC | |
289 | ENDPROC(el0_sync_invalid) | |
290 | ||
291 | el0_irq_invalid: | |
292 | inv_entry 0, BAD_IRQ | |
293 | ENDPROC(el0_irq_invalid) | |
294 | ||
295 | el0_fiq_invalid: | |
296 | inv_entry 0, BAD_FIQ | |
297 | ENDPROC(el0_fiq_invalid) | |
298 | ||
299 | el0_error_invalid: | |
300 | inv_entry 0, BAD_ERROR | |
301 | ENDPROC(el0_error_invalid) | |
302 | ||
303 | #ifdef CONFIG_COMPAT | |
304 | el0_fiq_invalid_compat: | |
305 | inv_entry 0, BAD_FIQ, 32 | |
306 | ENDPROC(el0_fiq_invalid_compat) | |
307 | ||
308 | el0_error_invalid_compat: | |
309 | inv_entry 0, BAD_ERROR, 32 | |
310 | ENDPROC(el0_error_invalid_compat) | |
311 | #endif | |
312 | ||
313 | el1_sync_invalid: | |
314 | inv_entry 1, BAD_SYNC | |
315 | ENDPROC(el1_sync_invalid) | |
316 | ||
317 | el1_irq_invalid: | |
318 | inv_entry 1, BAD_IRQ | |
319 | ENDPROC(el1_irq_invalid) | |
320 | ||
321 | el1_fiq_invalid: | |
322 | inv_entry 1, BAD_FIQ | |
323 | ENDPROC(el1_fiq_invalid) | |
324 | ||
325 | el1_error_invalid: | |
326 | inv_entry 1, BAD_ERROR | |
327 | ENDPROC(el1_error_invalid) | |
328 | ||
329 | /* | |
330 | * EL1 mode handlers. | |
331 | */ | |
332 | .align 6 | |
333 | el1_sync: | |
334 | kernel_entry 1 | |
335 | mrs x1, esr_el1 // read the syndrome register | |
aed40e01 MR |
336 | lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class |
337 | cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 | |
60ffc30d | 338 | b.eq el1_da |
aed40e01 | 339 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 340 | b.eq el1_undef |
aed40e01 | 341 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 342 | b.eq el1_sp_pc |
aed40e01 | 343 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 344 | b.eq el1_sp_pc |
aed40e01 | 345 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
60ffc30d | 346 | b.eq el1_undef |
aed40e01 | 347 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
60ffc30d CM |
348 | b.ge el1_dbg |
349 | b el1_inv | |
350 | el1_da: | |
351 | /* | |
352 | * Data abort handling | |
353 | */ | |
354 | mrs x0, far_el1 | |
2a283070 | 355 | enable_dbg |
60ffc30d CM |
356 | // re-enable interrupts if they were enabled in the aborted context |
357 | tbnz x23, #7, 1f // PSR_I_BIT | |
358 | enable_irq | |
359 | 1: | |
360 | mov x2, sp // struct pt_regs | |
361 | bl do_mem_abort | |
362 | ||
363 | // disable interrupts before pulling preserved data off the stack | |
364 | disable_irq | |
365 | kernel_exit 1 | |
366 | el1_sp_pc: | |
367 | /* | |
368 | * Stack or PC alignment exception handling | |
369 | */ | |
370 | mrs x0, far_el1 | |
2a283070 | 371 | enable_dbg |
60ffc30d CM |
372 | mov x2, sp |
373 | b do_sp_pc_abort | |
374 | el1_undef: | |
375 | /* | |
376 | * Undefined instruction | |
377 | */ | |
2a283070 | 378 | enable_dbg |
60ffc30d CM |
379 | mov x0, sp |
380 | b do_undefinstr | |
381 | el1_dbg: | |
382 | /* | |
383 | * Debug exception handling | |
384 | */ | |
aed40e01 | 385 | cmp x24, #ESR_ELx_EC_BRK64 // if BRK64 |
ee6214ce | 386 | cinc x24, x24, eq // set bit '0' |
60ffc30d CM |
387 | tbz x24, #0, el1_inv // EL1 only |
388 | mrs x0, far_el1 | |
389 | mov x2, sp // struct pt_regs | |
390 | bl do_debug_exception | |
60ffc30d CM |
391 | kernel_exit 1 |
392 | el1_inv: | |
393 | // TODO: add support for undefined instructions in kernel mode | |
2a283070 | 394 | enable_dbg |
60ffc30d | 395 | mov x0, sp |
1b42804d | 396 | mov x2, x1 |
60ffc30d | 397 | mov x1, #BAD_SYNC |
60ffc30d CM |
398 | b bad_mode |
399 | ENDPROC(el1_sync) | |
400 | ||
401 | .align 6 | |
402 | el1_irq: | |
403 | kernel_entry 1 | |
2a283070 | 404 | enable_dbg |
60ffc30d CM |
405 | #ifdef CONFIG_TRACE_IRQFLAGS |
406 | bl trace_hardirqs_off | |
407 | #endif | |
64681787 | 408 | |
d224a69e | 409 | get_thread_info tsk |
60ffc30d | 410 | irq_handler |
64681787 | 411 | |
60ffc30d | 412 | #ifdef CONFIG_PREEMPT |
883c0573 | 413 | ldr w24, [tsk, #TI_PREEMPT] // get preempt count |
717321fc | 414 | cbnz w24, 1f // preempt count != 0 |
60ffc30d CM |
415 | ldr x0, [tsk, #TI_FLAGS] // get flags |
416 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? | |
417 | bl el1_preempt | |
418 | 1: | |
419 | #endif | |
420 | #ifdef CONFIG_TRACE_IRQFLAGS | |
421 | bl trace_hardirqs_on | |
422 | #endif | |
423 | kernel_exit 1 | |
424 | ENDPROC(el1_irq) | |
425 | ||
426 | #ifdef CONFIG_PREEMPT | |
427 | el1_preempt: | |
428 | mov x24, lr | |
2a283070 | 429 | 1: bl preempt_schedule_irq // irq en/disable is done inside |
60ffc30d CM |
430 | ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS |
431 | tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? | |
432 | ret x24 | |
433 | #endif | |
434 | ||
435 | /* | |
436 | * EL0 mode handlers. | |
437 | */ | |
438 | .align 6 | |
439 | el0_sync: | |
440 | kernel_entry 0 | |
441 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
442 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
443 | cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state | |
60ffc30d | 444 | b.eq el0_svc |
aed40e01 | 445 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 446 | b.eq el0_da |
aed40e01 | 447 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 448 | b.eq el0_ia |
aed40e01 | 449 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 450 | b.eq el0_fpsimd_acc |
aed40e01 | 451 | cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception |
60ffc30d | 452 | b.eq el0_fpsimd_exc |
aed40e01 | 453 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
60ffc30d | 454 | b.eq el0_undef |
aed40e01 | 455 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
60ffc30d | 456 | b.eq el0_sp_pc |
aed40e01 | 457 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
60ffc30d | 458 | b.eq el0_sp_pc |
aed40e01 | 459 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 460 | b.eq el0_undef |
aed40e01 | 461 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
462 | b.ge el0_dbg |
463 | b el0_inv | |
464 | ||
465 | #ifdef CONFIG_COMPAT | |
466 | .align 6 | |
467 | el0_sync_compat: | |
468 | kernel_entry 0, 32 | |
469 | mrs x25, esr_el1 // read the syndrome register | |
aed40e01 MR |
470 | lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class |
471 | cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state | |
60ffc30d | 472 | b.eq el0_svc_compat |
aed40e01 | 473 | cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0 |
60ffc30d | 474 | b.eq el0_da |
aed40e01 | 475 | cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0 |
60ffc30d | 476 | b.eq el0_ia |
aed40e01 | 477 | cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access |
60ffc30d | 478 | b.eq el0_fpsimd_acc |
aed40e01 | 479 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
60ffc30d | 480 | b.eq el0_fpsimd_exc |
77f3228f MS |
481 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
482 | b.eq el0_sp_pc | |
aed40e01 | 483 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
60ffc30d | 484 | b.eq el0_undef |
aed40e01 | 485 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
381cc2b9 | 486 | b.eq el0_undef |
aed40e01 | 487 | cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap |
381cc2b9 | 488 | b.eq el0_undef |
aed40e01 | 489 | cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap |
381cc2b9 | 490 | b.eq el0_undef |
aed40e01 | 491 | cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap |
381cc2b9 | 492 | b.eq el0_undef |
aed40e01 | 493 | cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap |
381cc2b9 | 494 | b.eq el0_undef |
aed40e01 | 495 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
60ffc30d CM |
496 | b.ge el0_dbg |
497 | b el0_inv | |
498 | el0_svc_compat: | |
499 | /* | |
500 | * AArch32 syscall handling | |
501 | */ | |
0156411b | 502 | adrp stbl, compat_sys_call_table // load compat syscall table pointer |
60ffc30d CM |
503 | uxtw scno, w7 // syscall number in w7 (r7) |
504 | mov sc_nr, #__NR_compat_syscalls | |
505 | b el0_svc_naked | |
506 | ||
507 | .align 6 | |
508 | el0_irq_compat: | |
509 | kernel_entry 0, 32 | |
510 | b el0_irq_naked | |
511 | #endif | |
512 | ||
513 | el0_da: | |
514 | /* | |
515 | * Data abort handling | |
516 | */ | |
6ab6463a | 517 | mrs x26, far_el1 |
60ffc30d | 518 | // enable interrupts before calling the main handler |
2a283070 | 519 | enable_dbg_and_irq |
6c81fe79 | 520 | ct_user_exit |
6ab6463a | 521 | bic x0, x26, #(0xff << 56) |
60ffc30d CM |
522 | mov x1, x25 |
523 | mov x2, sp | |
d54e81f9 WD |
524 | bl do_mem_abort |
525 | b ret_to_user | |
60ffc30d CM |
526 | el0_ia: |
527 | /* | |
528 | * Instruction abort handling | |
529 | */ | |
6ab6463a | 530 | mrs x26, far_el1 |
60ffc30d | 531 | // enable interrupts before calling the main handler |
2a283070 | 532 | enable_dbg_and_irq |
6c81fe79 | 533 | ct_user_exit |
6ab6463a | 534 | mov x0, x26 |
60ffc30d CM |
535 | orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts |
536 | mov x2, sp | |
d54e81f9 WD |
537 | bl do_mem_abort |
538 | b ret_to_user | |
60ffc30d CM |
539 | el0_fpsimd_acc: |
540 | /* | |
541 | * Floating Point or Advanced SIMD access | |
542 | */ | |
2a283070 | 543 | enable_dbg |
6c81fe79 | 544 | ct_user_exit |
60ffc30d CM |
545 | mov x0, x25 |
546 | mov x1, sp | |
d54e81f9 WD |
547 | bl do_fpsimd_acc |
548 | b ret_to_user | |
60ffc30d CM |
549 | el0_fpsimd_exc: |
550 | /* | |
551 | * Floating Point or Advanced SIMD exception | |
552 | */ | |
2a283070 | 553 | enable_dbg |
6c81fe79 | 554 | ct_user_exit |
60ffc30d CM |
555 | mov x0, x25 |
556 | mov x1, sp | |
d54e81f9 WD |
557 | bl do_fpsimd_exc |
558 | b ret_to_user | |
60ffc30d CM |
559 | el0_sp_pc: |
560 | /* | |
561 | * Stack or PC alignment exception handling | |
562 | */ | |
6ab6463a | 563 | mrs x26, far_el1 |
60ffc30d | 564 | // enable interrupts before calling the main handler |
2a283070 | 565 | enable_dbg_and_irq |
46b0567c | 566 | ct_user_exit |
6ab6463a | 567 | mov x0, x26 |
60ffc30d CM |
568 | mov x1, x25 |
569 | mov x2, sp | |
d54e81f9 WD |
570 | bl do_sp_pc_abort |
571 | b ret_to_user | |
60ffc30d CM |
572 | el0_undef: |
573 | /* | |
574 | * Undefined instruction | |
575 | */ | |
2600e130 | 576 | // enable interrupts before calling the main handler |
2a283070 | 577 | enable_dbg_and_irq |
6c81fe79 | 578 | ct_user_exit |
2a283070 | 579 | mov x0, sp |
d54e81f9 WD |
580 | bl do_undefinstr |
581 | b ret_to_user | |
60ffc30d CM |
582 | el0_dbg: |
583 | /* | |
584 | * Debug exception handling | |
585 | */ | |
586 | tbnz x24, #0, el0_inv // EL0 only | |
587 | mrs x0, far_el1 | |
60ffc30d CM |
588 | mov x1, x25 |
589 | mov x2, sp | |
2a283070 WD |
590 | bl do_debug_exception |
591 | enable_dbg | |
6c81fe79 | 592 | ct_user_exit |
2a283070 | 593 | b ret_to_user |
60ffc30d | 594 | el0_inv: |
2a283070 | 595 | enable_dbg |
6c81fe79 | 596 | ct_user_exit |
60ffc30d CM |
597 | mov x0, sp |
598 | mov x1, #BAD_SYNC | |
1b42804d | 599 | mov x2, x25 |
d54e81f9 WD |
600 | bl bad_mode |
601 | b ret_to_user | |
60ffc30d CM |
602 | ENDPROC(el0_sync) |
603 | ||
604 | .align 6 | |
605 | el0_irq: | |
606 | kernel_entry 0 | |
607 | el0_irq_naked: | |
60ffc30d CM |
608 | enable_dbg |
609 | #ifdef CONFIG_TRACE_IRQFLAGS | |
610 | bl trace_hardirqs_off | |
611 | #endif | |
64681787 | 612 | |
6c81fe79 | 613 | ct_user_exit |
60ffc30d | 614 | irq_handler |
64681787 | 615 | |
60ffc30d CM |
616 | #ifdef CONFIG_TRACE_IRQFLAGS |
617 | bl trace_hardirqs_on | |
618 | #endif | |
619 | b ret_to_user | |
620 | ENDPROC(el0_irq) | |
621 | ||
60ffc30d CM |
622 | /* |
623 | * Register switch for AArch64. The callee-saved registers need to be saved | |
624 | * and restored. On entry: | |
625 | * x0 = previous task_struct (must be preserved across the switch) | |
626 | * x1 = next task_struct | |
627 | * Previous and next are guaranteed not to be the same. | |
628 | * | |
629 | */ | |
630 | ENTRY(cpu_switch_to) | |
c0d3fce5 WD |
631 | mov x10, #THREAD_CPU_CONTEXT |
632 | add x8, x0, x10 | |
60ffc30d CM |
633 | mov x9, sp |
634 | stp x19, x20, [x8], #16 // store callee-saved registers | |
635 | stp x21, x22, [x8], #16 | |
636 | stp x23, x24, [x8], #16 | |
637 | stp x25, x26, [x8], #16 | |
638 | stp x27, x28, [x8], #16 | |
639 | stp x29, x9, [x8], #16 | |
640 | str lr, [x8] | |
c0d3fce5 | 641 | add x8, x1, x10 |
60ffc30d CM |
642 | ldp x19, x20, [x8], #16 // restore callee-saved registers |
643 | ldp x21, x22, [x8], #16 | |
644 | ldp x23, x24, [x8], #16 | |
645 | ldp x25, x26, [x8], #16 | |
646 | ldp x27, x28, [x8], #16 | |
647 | ldp x29, x9, [x8], #16 | |
648 | ldr lr, [x8] | |
649 | mov sp, x9 | |
6cdf9c7c JL |
650 | and x9, x9, #~(THREAD_SIZE - 1) |
651 | msr sp_el0, x9 | |
60ffc30d CM |
652 | ret |
653 | ENDPROC(cpu_switch_to) | |
654 | ||
655 | /* | |
656 | * This is the fast syscall return path. We do as little as possible here, | |
657 | * and this includes saving x0 back into the kernel stack. | |
658 | */ | |
659 | ret_fast_syscall: | |
660 | disable_irq // disable interrupts | |
412fcb6c | 661 | str x0, [sp, #S_X0] // returned x0 |
04d7e098 JS |
662 | ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing |
663 | and x2, x1, #_TIF_SYSCALL_WORK | |
664 | cbnz x2, ret_fast_syscall_trace | |
60ffc30d | 665 | and x2, x1, #_TIF_WORK_MASK |
412fcb6c | 666 | cbnz x2, work_pending |
2a283070 | 667 | enable_step_tsk x1, x2 |
412fcb6c | 668 | kernel_exit 0 |
04d7e098 JS |
669 | ret_fast_syscall_trace: |
670 | enable_irq // enable interrupts | |
412fcb6c | 671 | b __sys_trace_return_skipped // we already saved x0 |
60ffc30d CM |
672 | |
673 | /* | |
674 | * Ok, we need to do extra processing, enter the slow path. | |
675 | */ | |
60ffc30d CM |
676 | work_pending: |
677 | tbnz x1, #TIF_NEED_RESCHED, work_resched | |
005f78cd | 678 | /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */ |
60ffc30d | 679 | mov x0, sp // 'regs' |
6916fd08 | 680 | enable_irq // enable interrupts for do_notify_resume() |
60ffc30d CM |
681 | bl do_notify_resume |
682 | b ret_to_user | |
683 | work_resched: | |
db3899a6 CM |
684 | #ifdef CONFIG_TRACE_IRQFLAGS |
685 | bl trace_hardirqs_off // the IRQs are off here, inform the tracing code | |
686 | #endif | |
60ffc30d CM |
687 | bl schedule |
688 | ||
689 | /* | |
690 | * "slow" syscall return path. | |
691 | */ | |
59dc67b0 | 692 | ret_to_user: |
60ffc30d CM |
693 | disable_irq // disable interrupts |
694 | ldr x1, [tsk, #TI_FLAGS] | |
695 | and x2, x1, #_TIF_WORK_MASK | |
696 | cbnz x2, work_pending | |
2a283070 | 697 | enable_step_tsk x1, x2 |
412fcb6c | 698 | kernel_exit 0 |
60ffc30d CM |
699 | ENDPROC(ret_to_user) |
700 | ||
701 | /* | |
702 | * This is how we return from a fork. | |
703 | */ | |
704 | ENTRY(ret_from_fork) | |
705 | bl schedule_tail | |
c34501d2 CM |
706 | cbz x19, 1f // not a kernel thread |
707 | mov x0, x20 | |
708 | blr x19 | |
709 | 1: get_thread_info tsk | |
60ffc30d CM |
710 | b ret_to_user |
711 | ENDPROC(ret_from_fork) | |
712 | ||
713 | /* | |
714 | * SVC handler. | |
715 | */ | |
716 | .align 6 | |
717 | el0_svc: | |
718 | adrp stbl, sys_call_table // load syscall table pointer | |
719 | uxtw scno, w8 // syscall number in w8 | |
720 | mov sc_nr, #__NR_syscalls | |
721 | el0_svc_naked: // compat entry point | |
722 | stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number | |
2a283070 | 723 | enable_dbg_and_irq |
6c81fe79 | 724 | ct_user_exit 1 |
60ffc30d | 725 | |
449f81a4 AT |
726 | ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks |
727 | tst x16, #_TIF_SYSCALL_WORK | |
728 | b.ne __sys_trace | |
60ffc30d CM |
729 | cmp scno, sc_nr // check upper syscall limit |
730 | b.hs ni_sys | |
731 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table | |
d54e81f9 WD |
732 | blr x16 // call sys_* routine |
733 | b ret_fast_syscall | |
60ffc30d CM |
734 | ni_sys: |
735 | mov x0, sp | |
d54e81f9 WD |
736 | bl do_ni_syscall |
737 | b ret_fast_syscall | |
60ffc30d CM |
738 | ENDPROC(el0_svc) |
739 | ||
740 | /* | |
741 | * This is the really slow path. We're going to be doing context | |
742 | * switches, and waiting for our parent to respond. | |
743 | */ | |
744 | __sys_trace: | |
1014c81d AT |
745 | mov w0, #-1 // set default errno for |
746 | cmp scno, x0 // user-issued syscall(-1) | |
747 | b.ne 1f | |
748 | mov x0, #-ENOSYS | |
749 | str x0, [sp, #S_X0] | |
750 | 1: mov x0, sp | |
3157858f | 751 | bl syscall_trace_enter |
1014c81d AT |
752 | cmp w0, #-1 // skip the syscall? |
753 | b.eq __sys_trace_return_skipped | |
60ffc30d CM |
754 | uxtw scno, w0 // syscall number (possibly new) |
755 | mov x1, sp // pointer to regs | |
756 | cmp scno, sc_nr // check upper syscall limit | |
d54e81f9 | 757 | b.hs __ni_sys_trace |
60ffc30d CM |
758 | ldp x0, x1, [sp] // restore the syscall args |
759 | ldp x2, x3, [sp, #S_X2] | |
760 | ldp x4, x5, [sp, #S_X4] | |
761 | ldp x6, x7, [sp, #S_X6] | |
762 | ldr x16, [stbl, scno, lsl #3] // address in the syscall table | |
d54e81f9 | 763 | blr x16 // call sys_* routine |
60ffc30d CM |
764 | |
765 | __sys_trace_return: | |
1014c81d AT |
766 | str x0, [sp, #S_X0] // save returned x0 |
767 | __sys_trace_return_skipped: | |
3157858f AT |
768 | mov x0, sp |
769 | bl syscall_trace_exit | |
60ffc30d CM |
770 | b ret_to_user |
771 | ||
d54e81f9 WD |
772 | __ni_sys_trace: |
773 | mov x0, sp | |
774 | bl do_ni_syscall | |
775 | b __sys_trace_return | |
776 | ||
60ffc30d CM |
777 | /* |
778 | * Special system call wrappers. | |
779 | */ | |
60ffc30d CM |
780 | ENTRY(sys_rt_sigreturn_wrapper) |
781 | mov x0, sp | |
782 | b sys_rt_sigreturn | |
783 | ENDPROC(sys_rt_sigreturn_wrapper) |