Commit | Line | Data |
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d329de3f MZ |
1 | /* |
2 | * Spin Table SMP initialisation | |
3 | * | |
4 | * Copyright (C) 2013 ARM Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
652af899 | 19 | #include <linux/delay.h> |
d329de3f MZ |
20 | #include <linux/init.h> |
21 | #include <linux/of.h> | |
22 | #include <linux/smp.h> | |
23 | ||
24 | #include <asm/cacheflush.h> | |
cd1aebf5 | 25 | #include <asm/cpu_ops.h> |
652af899 MR |
26 | #include <asm/cputype.h> |
27 | #include <asm/smp_plat.h> | |
28 | ||
29 | extern void secondary_holding_pen(void); | |
30 | volatile unsigned long secondary_holding_pen_release = INVALID_HWID; | |
d329de3f MZ |
31 | |
32 | static phys_addr_t cpu_release_addr[NR_CPUS]; | |
652af899 MR |
33 | static DEFINE_RAW_SPINLOCK(boot_lock); |
34 | ||
35 | /* | |
36 | * Write secondary_holding_pen_release in a way that is guaranteed to be | |
37 | * visible to all observers, irrespective of whether they're taking part | |
38 | * in coherency or not. This is necessary for the hotplug code to work | |
39 | * reliably. | |
40 | */ | |
41 | static void write_pen_release(u64 val) | |
42 | { | |
43 | void *start = (void *)&secondary_holding_pen_release; | |
44 | unsigned long size = sizeof(secondary_holding_pen_release); | |
45 | ||
46 | secondary_holding_pen_release = val; | |
47 | __flush_dcache_area(start, size); | |
48 | } | |
49 | ||
d329de3f | 50 | |
cd1aebf5 | 51 | static int smp_spin_table_cpu_init(struct device_node *dn, unsigned int cpu) |
d329de3f MZ |
52 | { |
53 | /* | |
54 | * Determine the address from which the CPU is polling. | |
55 | */ | |
56 | if (of_property_read_u64(dn, "cpu-release-addr", | |
57 | &cpu_release_addr[cpu])) { | |
58 | pr_err("CPU %d: missing or invalid cpu-release-addr property\n", | |
59 | cpu); | |
60 | ||
61 | return -1; | |
62 | } | |
63 | ||
64 | return 0; | |
65 | } | |
66 | ||
cd1aebf5 | 67 | static int smp_spin_table_cpu_prepare(unsigned int cpu) |
d329de3f MZ |
68 | { |
69 | void **release_addr; | |
70 | ||
71 | if (!cpu_release_addr[cpu]) | |
72 | return -ENODEV; | |
73 | ||
74 | release_addr = __va(cpu_release_addr[cpu]); | |
710be9ac ML |
75 | |
76 | /* | |
77 | * We write the release address as LE regardless of the native | |
78 | * endianess of the kernel. Therefore, any boot-loaders that | |
79 | * read this address need to convert this address to the | |
80 | * boot-loader's endianess before jumping. This is mandated by | |
81 | * the boot protocol. | |
82 | */ | |
83 | release_addr[0] = (void *) cpu_to_le64(__pa(secondary_holding_pen)); | |
84 | ||
d329de3f MZ |
85 | __flush_dcache_area(release_addr, sizeof(release_addr[0])); |
86 | ||
87 | /* | |
88 | * Send an event to wake up the secondary CPU. | |
89 | */ | |
90 | sev(); | |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
652af899 MR |
95 | static int smp_spin_table_cpu_boot(unsigned int cpu) |
96 | { | |
97 | unsigned long timeout; | |
98 | ||
99 | /* | |
100 | * Set synchronisation state between this boot processor | |
101 | * and the secondary one | |
102 | */ | |
103 | raw_spin_lock(&boot_lock); | |
104 | ||
105 | /* | |
106 | * Update the pen release flag. | |
107 | */ | |
108 | write_pen_release(cpu_logical_map(cpu)); | |
109 | ||
110 | /* | |
111 | * Send an event, causing the secondaries to read pen_release. | |
112 | */ | |
113 | sev(); | |
114 | ||
115 | timeout = jiffies + (1 * HZ); | |
116 | while (time_before(jiffies, timeout)) { | |
117 | if (secondary_holding_pen_release == INVALID_HWID) | |
118 | break; | |
119 | udelay(10); | |
120 | } | |
121 | ||
122 | /* | |
123 | * Now the secondary core is starting up let it run its | |
124 | * calibrations, then wait for it to finish | |
125 | */ | |
126 | raw_spin_unlock(&boot_lock); | |
127 | ||
128 | return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0; | |
129 | } | |
130 | ||
7184659b | 131 | static void smp_spin_table_cpu_postboot(void) |
652af899 MR |
132 | { |
133 | /* | |
134 | * Let the primary processor know we're out of the pen. | |
135 | */ | |
136 | write_pen_release(INVALID_HWID); | |
137 | ||
138 | /* | |
139 | * Synchronise with the boot thread. | |
140 | */ | |
141 | raw_spin_lock(&boot_lock); | |
142 | raw_spin_unlock(&boot_lock); | |
143 | } | |
144 | ||
cd1aebf5 | 145 | const struct cpu_operations smp_spin_table_ops = { |
d329de3f | 146 | .name = "spin-table", |
cd1aebf5 MR |
147 | .cpu_init = smp_spin_table_cpu_init, |
148 | .cpu_prepare = smp_spin_table_cpu_prepare, | |
652af899 MR |
149 | .cpu_boot = smp_spin_table_cpu_boot, |
150 | .cpu_postboot = smp_spin_table_cpu_postboot, | |
d329de3f | 151 | }; |