Commit | Line | Data |
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5f97f7f9 | 1 | /* |
7760989e | 2 | * Copyright (C) 2004-2007 Atmel Corporation |
5f97f7f9 | 3 | * |
5f97f7f9 HS |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
5f97f7f9 | 8 | #include <linux/clk.h> |
e723ff66 | 9 | #include <linux/clockchips.h> |
9dbef285 | 10 | #include <linux/init.h> |
5f97f7f9 HS |
11 | #include <linux/interrupt.h> |
12 | #include <linux/irq.h> | |
9dbef285 HS |
13 | #include <linux/kernel.h> |
14 | #include <linux/time.h> | |
01426478 | 15 | #include <linux/cpu.h> |
5f97f7f9 | 16 | |
5f97f7f9 | 17 | #include <asm/sysreg.h> |
5f97f7f9 | 18 | |
3663b736 | 19 | #include <mach/pm.h> |
7760989e | 20 | |
09adcdf2 | 21 | static bool disable_cpu_idle_poll; |
7760989e | 22 | |
8e19608e | 23 | static cycle_t read_cycle_count(struct clocksource *cs) |
5f97f7f9 HS |
24 | { |
25 | return (cycle_t)sysreg_read(COUNT); | |
26 | } | |
27 | ||
62c6df62 DB |
28 | /* |
29 | * The architectural cycle count registers are a fine clocksource unless | |
30 | * the system idle loop use sleep states like "idle": the CPU cycles | |
31 | * measured by COUNT (and COMPARE) don't happen during sleep states. | |
e723ff66 | 32 | * Their duration also changes if cpufreq changes the CPU clock rate. |
62c6df62 DB |
33 | * So we rate the clocksource using COUNT as very low quality. |
34 | */ | |
e723ff66 DB |
35 | static struct clocksource counter = { |
36 | .name = "avr32_counter", | |
62c6df62 | 37 | .rating = 50, |
5f97f7f9 HS |
38 | .read = read_cycle_count, |
39 | .mask = CLOCKSOURCE_MASK(32), | |
2693506c | 40 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
5f97f7f9 HS |
41 | }; |
42 | ||
e723ff66 | 43 | static irqreturn_t timer_interrupt(int irq, void *dev_id) |
5f97f7f9 | 44 | { |
e723ff66 | 45 | struct clock_event_device *evdev = dev_id; |
7760989e | 46 | |
56d3eef2 VN |
47 | if (unlikely(!(intc_get_pending(0) & 1))) |
48 | return IRQ_NONE; | |
49 | ||
e723ff66 DB |
50 | /* |
51 | * Disable the interrupt until the clockevent subsystem | |
52 | * reprograms it. | |
53 | */ | |
54 | sysreg_write(COMPARE, 0); | |
7760989e | 55 | |
e723ff66 DB |
56 | evdev->event_handler(evdev); |
57 | return IRQ_HANDLED; | |
58 | } | |
7760989e | 59 | |
e723ff66 DB |
60 | static struct irqaction timer_irqaction = { |
61 | .handler = timer_interrupt, | |
56d3eef2 | 62 | /* Oprofile uses the same irq as the timer, so allow it to be shared */ |
7155530d | 63 | .flags = IRQF_TIMER | IRQF_SHARED, |
e723ff66 DB |
64 | .name = "avr32_comparator", |
65 | }; | |
7760989e | 66 | |
e723ff66 DB |
67 | static int comparator_next_event(unsigned long delta, |
68 | struct clock_event_device *evdev) | |
69 | { | |
70 | unsigned long flags; | |
7760989e | 71 | |
e723ff66 | 72 | raw_local_irq_save(flags); |
7760989e | 73 | |
e723ff66 DB |
74 | /* The time to read COUNT then update COMPARE must be less |
75 | * than the min_delta_ns value for this clockevent source. | |
76 | */ | |
77 | sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1); | |
5f97f7f9 | 78 | |
e723ff66 | 79 | raw_local_irq_restore(flags); |
7760989e HCE |
80 | |
81 | return 0; | |
5f97f7f9 HS |
82 | } |
83 | ||
09adcdf2 | 84 | static int comparator_shutdown(struct clock_event_device *evdev) |
5f97f7f9 | 85 | { |
09adcdf2 VK |
86 | pr_debug("%s: %s\n", __func__, evdev->name); |
87 | sysreg_write(COMPARE, 0); | |
88 | ||
89 | if (disable_cpu_idle_poll) { | |
90 | disable_cpu_idle_poll = false; | |
01426478 | 91 | /* |
09adcdf2 VK |
92 | * Only disable idle poll if we have forced that |
93 | * in a previous call. | |
01426478 | 94 | */ |
09adcdf2 | 95 | cpu_idle_poll_ctrl(false); |
e723ff66 | 96 | } |
09adcdf2 VK |
97 | return 0; |
98 | } | |
99 | ||
100 | static int comparator_set_oneshot(struct clock_event_device *evdev) | |
101 | { | |
102 | pr_debug("%s: %s\n", __func__, evdev->name); | |
103 | ||
104 | disable_cpu_idle_poll = true; | |
105 | /* | |
106 | * If we're using the COUNT and COMPARE registers we | |
107 | * need to force idle poll. | |
108 | */ | |
109 | cpu_idle_poll_ctrl(true); | |
110 | ||
111 | return 0; | |
5f97f7f9 HS |
112 | } |
113 | ||
e723ff66 | 114 | static struct clock_event_device comparator = { |
09adcdf2 VK |
115 | .name = "avr32_comparator", |
116 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
117 | .shift = 16, | |
118 | .rating = 50, | |
119 | .set_next_event = comparator_next_event, | |
120 | .set_state_shutdown = comparator_shutdown, | |
121 | .set_state_oneshot = comparator_set_oneshot, | |
122 | .tick_resume = comparator_set_oneshot, | |
e723ff66 | 123 | }; |
5f97f7f9 | 124 | |
e2032a4a JS |
125 | void read_persistent_clock(struct timespec *ts) |
126 | { | |
e9ddbc07 | 127 | ts->tv_sec = mktime(2007, 1, 1, 0, 0, 0); |
e2032a4a JS |
128 | ts->tv_nsec = 0; |
129 | } | |
130 | ||
5f97f7f9 HS |
131 | void __init time_init(void) |
132 | { | |
e723ff66 | 133 | unsigned long counter_hz; |
5f97f7f9 HS |
134 | int ret; |
135 | ||
e723ff66 DB |
136 | /* figure rate for counter */ |
137 | counter_hz = clk_get_rate(boot_cpu_data.clk); | |
1e2de47c | 138 | ret = clocksource_register_hz(&counter, counter_hz); |
5f97f7f9 | 139 | if (ret) |
7760989e | 140 | pr_debug("timer: could not register clocksource: %d\n", ret); |
5f97f7f9 | 141 | |
e723ff66 DB |
142 | /* setup COMPARE clockevent */ |
143 | comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift); | |
144 | comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator); | |
145 | comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1; | |
320ab2b0 | 146 | comparator.cpumask = cpumask_of(0); |
e723ff66 DB |
147 | |
148 | sysreg_write(COMPARE, 0); | |
149 | timer_irqaction.dev_id = &comparator; | |
150 | ||
151 | ret = setup_irq(0, &timer_irqaction); | |
152 | if (ret) | |
153 | pr_debug("timer: could not request IRQ 0: %d\n", ret); | |
154 | else { | |
155 | clockevents_register_device(&comparator); | |
156 | ||
157 | pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name, | |
158 | ((counter_hz + 500) / 1000) / 1000, | |
159 | ((counter_hz + 500) / 1000) % 1000); | |
7760989e | 160 | } |
5f97f7f9 | 161 | } |