Commit | Line | Data |
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5f97f7f9 HS |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | #include <linux/clk.h> | |
35bf50cc | 9 | #include <linux/delay.h> |
3bfb1d20 | 10 | #include <linux/dw_dmac.h> |
d0a2b7af | 11 | #include <linux/fb.h> |
5f97f7f9 HS |
12 | #include <linux/init.h> |
13 | #include <linux/platform_device.h> | |
6b84bbfc | 14 | #include <linux/dma-mapping.h> |
3c26e170 | 15 | #include <linux/gpio.h> |
41d8ca45 | 16 | #include <linux/spi/spi.h> |
8d855317 | 17 | #include <linux/usb/atmel_usba_udc.h> |
5f97f7f9 | 18 | |
7d2be074 | 19 | #include <asm/atmel-mci.h> |
5f97f7f9 | 20 | #include <asm/io.h> |
e7ba176b | 21 | #include <asm/irq.h> |
5f97f7f9 | 22 | |
3663b736 HS |
23 | #include <mach/at32ap700x.h> |
24 | #include <mach/board.h> | |
b47eb409 | 25 | #include <mach/hmatrix.h> |
3663b736 HS |
26 | #include <mach/portmux.h> |
27 | #include <mach/sram.h> | |
5f97f7f9 | 28 | |
d0a2b7af HS |
29 | #include <video/atmel_lcdc.h> |
30 | ||
5f97f7f9 HS |
31 | #include "clock.h" |
32 | #include "pio.h" | |
7a5b8059 HS |
33 | #include "pm.h" |
34 | ||
5f97f7f9 HS |
35 | |
36 | #define PBMEM(base) \ | |
37 | { \ | |
38 | .start = base, \ | |
39 | .end = base + 0x3ff, \ | |
40 | .flags = IORESOURCE_MEM, \ | |
41 | } | |
42 | #define IRQ(num) \ | |
43 | { \ | |
44 | .start = num, \ | |
45 | .end = num, \ | |
46 | .flags = IORESOURCE_IRQ, \ | |
47 | } | |
48 | #define NAMED_IRQ(num, _name) \ | |
49 | { \ | |
50 | .start = num, \ | |
51 | .end = num, \ | |
52 | .name = _name, \ | |
53 | .flags = IORESOURCE_IRQ, \ | |
54 | } | |
55 | ||
6b84bbfc DB |
56 | /* REVISIT these assume *every* device supports DMA, but several |
57 | * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more. | |
58 | */ | |
5f97f7f9 | 59 | #define DEFINE_DEV(_name, _id) \ |
6b84bbfc | 60 | static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \ |
5f97f7f9 HS |
61 | static struct platform_device _name##_id##_device = { \ |
62 | .name = #_name, \ | |
63 | .id = _id, \ | |
6b84bbfc DB |
64 | .dev = { \ |
65 | .dma_mask = &_name##_id##_dma_mask, \ | |
66 | .coherent_dma_mask = DMA_32BIT_MASK, \ | |
67 | }, \ | |
5f97f7f9 HS |
68 | .resource = _name##_id##_resource, \ |
69 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
70 | } | |
71 | #define DEFINE_DEV_DATA(_name, _id) \ | |
6b84bbfc | 72 | static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \ |
5f97f7f9 HS |
73 | static struct platform_device _name##_id##_device = { \ |
74 | .name = #_name, \ | |
75 | .id = _id, \ | |
76 | .dev = { \ | |
6b84bbfc | 77 | .dma_mask = &_name##_id##_dma_mask, \ |
5f97f7f9 | 78 | .platform_data = &_name##_id##_data, \ |
6b84bbfc | 79 | .coherent_dma_mask = DMA_32BIT_MASK, \ |
5f97f7f9 HS |
80 | }, \ |
81 | .resource = _name##_id##_resource, \ | |
82 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
83 | } | |
84 | ||
caf18f19 JM |
85 | #define select_peripheral(port, pin_mask, periph, flags) \ |
86 | at32_select_periph(GPIO_##port##_BASE, pin_mask, \ | |
87 | GPIO_##periph, flags) | |
c3e2a79c | 88 | |
5f97f7f9 HS |
89 | #define DEV_CLK(_name, devname, bus, _index) \ |
90 | static struct clk devname##_##_name = { \ | |
91 | .name = #_name, \ | |
92 | .dev = &devname##_device.dev, \ | |
93 | .parent = &bus##_clk, \ | |
94 | .mode = bus##_clk_mode, \ | |
95 | .get_rate = bus##_clk_get_rate, \ | |
96 | .index = _index, \ | |
97 | } | |
98 | ||
7a5b8059 HS |
99 | static DEFINE_SPINLOCK(pm_lock); |
100 | ||
35bf50cc HCE |
101 | static struct clk osc0; |
102 | static struct clk osc1; | |
103 | ||
5f97f7f9 HS |
104 | static unsigned long osc_get_rate(struct clk *clk) |
105 | { | |
60ed7951 | 106 | return at32_board_osc_rates[clk->index]; |
5f97f7f9 HS |
107 | } |
108 | ||
109 | static unsigned long pll_get_rate(struct clk *clk, unsigned long control) | |
110 | { | |
111 | unsigned long div, mul, rate; | |
112 | ||
7a5b8059 HS |
113 | div = PM_BFEXT(PLLDIV, control) + 1; |
114 | mul = PM_BFEXT(PLLMUL, control) + 1; | |
5f97f7f9 HS |
115 | |
116 | rate = clk->parent->get_rate(clk->parent); | |
117 | rate = (rate + div / 2) / div; | |
118 | rate *= mul; | |
119 | ||
120 | return rate; | |
121 | } | |
122 | ||
35bf50cc HCE |
123 | static long pll_set_rate(struct clk *clk, unsigned long rate, |
124 | u32 *pll_ctrl) | |
125 | { | |
126 | unsigned long mul; | |
127 | unsigned long mul_best_fit = 0; | |
128 | unsigned long div; | |
129 | unsigned long div_min; | |
130 | unsigned long div_max; | |
131 | unsigned long div_best_fit = 0; | |
132 | unsigned long base; | |
133 | unsigned long pll_in; | |
134 | unsigned long actual = 0; | |
135 | unsigned long rate_error; | |
136 | unsigned long rate_error_prev = ~0UL; | |
137 | u32 ctrl; | |
138 | ||
139 | /* Rate must be between 80 MHz and 200 Mhz. */ | |
140 | if (rate < 80000000UL || rate > 200000000UL) | |
141 | return -EINVAL; | |
142 | ||
143 | ctrl = PM_BF(PLLOPT, 4); | |
144 | base = clk->parent->get_rate(clk->parent); | |
145 | ||
146 | /* PLL input frequency must be between 6 MHz and 32 MHz. */ | |
147 | div_min = DIV_ROUND_UP(base, 32000000UL); | |
148 | div_max = base / 6000000UL; | |
149 | ||
150 | if (div_max < div_min) | |
151 | return -EINVAL; | |
152 | ||
153 | for (div = div_min; div <= div_max; div++) { | |
154 | pll_in = (base + div / 2) / div; | |
155 | mul = (rate + pll_in / 2) / pll_in; | |
156 | ||
157 | if (mul == 0) | |
158 | continue; | |
159 | ||
160 | actual = pll_in * mul; | |
161 | rate_error = abs(actual - rate); | |
162 | ||
163 | if (rate_error < rate_error_prev) { | |
164 | mul_best_fit = mul; | |
165 | div_best_fit = div; | |
166 | rate_error_prev = rate_error; | |
167 | } | |
168 | ||
169 | if (rate_error == 0) | |
170 | break; | |
171 | } | |
172 | ||
173 | if (div_best_fit == 0) | |
174 | return -EINVAL; | |
175 | ||
176 | ctrl |= PM_BF(PLLMUL, mul_best_fit - 1); | |
177 | ctrl |= PM_BF(PLLDIV, div_best_fit - 1); | |
178 | ctrl |= PM_BF(PLLCOUNT, 16); | |
179 | ||
180 | if (clk->parent == &osc1) | |
181 | ctrl |= PM_BIT(PLLOSC); | |
182 | ||
183 | *pll_ctrl = ctrl; | |
184 | ||
185 | return actual; | |
186 | } | |
187 | ||
5f97f7f9 HS |
188 | static unsigned long pll0_get_rate(struct clk *clk) |
189 | { | |
190 | u32 control; | |
191 | ||
7a5b8059 | 192 | control = pm_readl(PLL0); |
5f97f7f9 HS |
193 | |
194 | return pll_get_rate(clk, control); | |
195 | } | |
196 | ||
35bf50cc HCE |
197 | static void pll1_mode(struct clk *clk, int enabled) |
198 | { | |
199 | unsigned long timeout; | |
200 | u32 status; | |
201 | u32 ctrl; | |
202 | ||
203 | ctrl = pm_readl(PLL1); | |
204 | ||
205 | if (enabled) { | |
206 | if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) { | |
207 | pr_debug("clk %s: failed to enable, rate not set\n", | |
208 | clk->name); | |
209 | return; | |
210 | } | |
211 | ||
212 | ctrl |= PM_BIT(PLLEN); | |
213 | pm_writel(PLL1, ctrl); | |
214 | ||
215 | /* Wait for PLL lock. */ | |
216 | for (timeout = 10000; timeout; timeout--) { | |
217 | status = pm_readl(ISR); | |
218 | if (status & PM_BIT(LOCK1)) | |
219 | break; | |
220 | udelay(10); | |
221 | } | |
222 | ||
223 | if (!(status & PM_BIT(LOCK1))) | |
224 | printk(KERN_ERR "clk %s: timeout waiting for lock\n", | |
225 | clk->name); | |
226 | } else { | |
227 | ctrl &= ~PM_BIT(PLLEN); | |
228 | pm_writel(PLL1, ctrl); | |
229 | } | |
230 | } | |
231 | ||
5f97f7f9 HS |
232 | static unsigned long pll1_get_rate(struct clk *clk) |
233 | { | |
234 | u32 control; | |
235 | ||
7a5b8059 | 236 | control = pm_readl(PLL1); |
5f97f7f9 HS |
237 | |
238 | return pll_get_rate(clk, control); | |
239 | } | |
240 | ||
35bf50cc HCE |
241 | static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply) |
242 | { | |
243 | u32 ctrl = 0; | |
244 | unsigned long actual_rate; | |
245 | ||
246 | actual_rate = pll_set_rate(clk, rate, &ctrl); | |
247 | ||
248 | if (apply) { | |
249 | if (actual_rate != rate) | |
250 | return -EINVAL; | |
251 | if (clk->users > 0) | |
252 | return -EBUSY; | |
253 | pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n", | |
254 | clk->name, rate, actual_rate); | |
255 | pm_writel(PLL1, ctrl); | |
256 | } | |
257 | ||
258 | return actual_rate; | |
259 | } | |
260 | ||
261 | static int pll1_set_parent(struct clk *clk, struct clk *parent) | |
262 | { | |
263 | u32 ctrl; | |
264 | ||
265 | if (clk->users > 0) | |
266 | return -EBUSY; | |
267 | ||
268 | ctrl = pm_readl(PLL1); | |
269 | WARN_ON(ctrl & PM_BIT(PLLEN)); | |
270 | ||
271 | if (parent == &osc0) | |
272 | ctrl &= ~PM_BIT(PLLOSC); | |
273 | else if (parent == &osc1) | |
274 | ctrl |= PM_BIT(PLLOSC); | |
275 | else | |
276 | return -EINVAL; | |
277 | ||
278 | pm_writel(PLL1, ctrl); | |
279 | clk->parent = parent; | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
5f97f7f9 HS |
284 | /* |
285 | * The AT32AP7000 has five primary clock sources: One 32kHz | |
286 | * oscillator, two crystal oscillators and two PLLs. | |
287 | */ | |
288 | static struct clk osc32k = { | |
289 | .name = "osc32k", | |
290 | .get_rate = osc_get_rate, | |
291 | .users = 1, | |
292 | .index = 0, | |
293 | }; | |
294 | static struct clk osc0 = { | |
295 | .name = "osc0", | |
296 | .get_rate = osc_get_rate, | |
297 | .users = 1, | |
298 | .index = 1, | |
299 | }; | |
300 | static struct clk osc1 = { | |
301 | .name = "osc1", | |
302 | .get_rate = osc_get_rate, | |
303 | .index = 2, | |
304 | }; | |
305 | static struct clk pll0 = { | |
306 | .name = "pll0", | |
307 | .get_rate = pll0_get_rate, | |
308 | .parent = &osc0, | |
309 | }; | |
310 | static struct clk pll1 = { | |
311 | .name = "pll1", | |
35bf50cc | 312 | .mode = pll1_mode, |
5f97f7f9 | 313 | .get_rate = pll1_get_rate, |
35bf50cc HCE |
314 | .set_rate = pll1_set_rate, |
315 | .set_parent = pll1_set_parent, | |
5f97f7f9 HS |
316 | .parent = &osc0, |
317 | }; | |
318 | ||
319 | /* | |
320 | * The main clock can be either osc0 or pll0. The boot loader may | |
321 | * have chosen one for us, so we don't really know which one until we | |
322 | * have a look at the SM. | |
323 | */ | |
324 | static struct clk *main_clock; | |
325 | ||
326 | /* | |
327 | * Synchronous clocks are generated from the main clock. The clocks | |
328 | * must satisfy the constraint | |
329 | * fCPU >= fHSB >= fPB | |
330 | * i.e. each clock must not be faster than its parent. | |
331 | */ | |
332 | static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift) | |
333 | { | |
334 | return main_clock->get_rate(main_clock) >> shift; | |
335 | }; | |
336 | ||
337 | static void cpu_clk_mode(struct clk *clk, int enabled) | |
338 | { | |
5f97f7f9 HS |
339 | unsigned long flags; |
340 | u32 mask; | |
341 | ||
7a5b8059 HS |
342 | spin_lock_irqsave(&pm_lock, flags); |
343 | mask = pm_readl(CPU_MASK); | |
5f97f7f9 HS |
344 | if (enabled) |
345 | mask |= 1 << clk->index; | |
346 | else | |
347 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
348 | pm_writel(CPU_MASK, mask); |
349 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
350 | } |
351 | ||
352 | static unsigned long cpu_clk_get_rate(struct clk *clk) | |
353 | { | |
354 | unsigned long cksel, shift = 0; | |
355 | ||
7a5b8059 HS |
356 | cksel = pm_readl(CKSEL); |
357 | if (cksel & PM_BIT(CPUDIV)) | |
358 | shift = PM_BFEXT(CPUSEL, cksel) + 1; | |
5f97f7f9 HS |
359 | |
360 | return bus_clk_get_rate(clk, shift); | |
361 | } | |
362 | ||
9e58e185 HCE |
363 | static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply) |
364 | { | |
365 | u32 control; | |
366 | unsigned long parent_rate, child_div, actual_rate, div; | |
367 | ||
368 | parent_rate = clk->parent->get_rate(clk->parent); | |
369 | control = pm_readl(CKSEL); | |
370 | ||
371 | if (control & PM_BIT(HSBDIV)) | |
372 | child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1); | |
373 | else | |
374 | child_div = 1; | |
375 | ||
376 | if (rate > 3 * (parent_rate / 4) || child_div == 1) { | |
377 | actual_rate = parent_rate; | |
378 | control &= ~PM_BIT(CPUDIV); | |
379 | } else { | |
380 | unsigned int cpusel; | |
381 | div = (parent_rate + rate / 2) / rate; | |
382 | if (div > child_div) | |
383 | div = child_div; | |
384 | cpusel = (div > 1) ? (fls(div) - 2) : 0; | |
385 | control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control); | |
386 | actual_rate = parent_rate / (1 << (cpusel + 1)); | |
387 | } | |
388 | ||
389 | pr_debug("clk %s: new rate %lu (actual rate %lu)\n", | |
390 | clk->name, rate, actual_rate); | |
391 | ||
392 | if (apply) | |
393 | pm_writel(CKSEL, control); | |
394 | ||
395 | return actual_rate; | |
396 | } | |
397 | ||
5f97f7f9 HS |
398 | static void hsb_clk_mode(struct clk *clk, int enabled) |
399 | { | |
5f97f7f9 HS |
400 | unsigned long flags; |
401 | u32 mask; | |
402 | ||
7a5b8059 HS |
403 | spin_lock_irqsave(&pm_lock, flags); |
404 | mask = pm_readl(HSB_MASK); | |
5f97f7f9 HS |
405 | if (enabled) |
406 | mask |= 1 << clk->index; | |
407 | else | |
408 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
409 | pm_writel(HSB_MASK, mask); |
410 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
411 | } |
412 | ||
413 | static unsigned long hsb_clk_get_rate(struct clk *clk) | |
414 | { | |
415 | unsigned long cksel, shift = 0; | |
416 | ||
7a5b8059 HS |
417 | cksel = pm_readl(CKSEL); |
418 | if (cksel & PM_BIT(HSBDIV)) | |
419 | shift = PM_BFEXT(HSBSEL, cksel) + 1; | |
5f97f7f9 HS |
420 | |
421 | return bus_clk_get_rate(clk, shift); | |
422 | } | |
423 | ||
424 | static void pba_clk_mode(struct clk *clk, int enabled) | |
425 | { | |
5f97f7f9 HS |
426 | unsigned long flags; |
427 | u32 mask; | |
428 | ||
7a5b8059 HS |
429 | spin_lock_irqsave(&pm_lock, flags); |
430 | mask = pm_readl(PBA_MASK); | |
5f97f7f9 HS |
431 | if (enabled) |
432 | mask |= 1 << clk->index; | |
433 | else | |
434 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
435 | pm_writel(PBA_MASK, mask); |
436 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
437 | } |
438 | ||
439 | static unsigned long pba_clk_get_rate(struct clk *clk) | |
440 | { | |
441 | unsigned long cksel, shift = 0; | |
442 | ||
7a5b8059 HS |
443 | cksel = pm_readl(CKSEL); |
444 | if (cksel & PM_BIT(PBADIV)) | |
445 | shift = PM_BFEXT(PBASEL, cksel) + 1; | |
5f97f7f9 HS |
446 | |
447 | return bus_clk_get_rate(clk, shift); | |
448 | } | |
449 | ||
450 | static void pbb_clk_mode(struct clk *clk, int enabled) | |
451 | { | |
5f97f7f9 HS |
452 | unsigned long flags; |
453 | u32 mask; | |
454 | ||
7a5b8059 HS |
455 | spin_lock_irqsave(&pm_lock, flags); |
456 | mask = pm_readl(PBB_MASK); | |
5f97f7f9 HS |
457 | if (enabled) |
458 | mask |= 1 << clk->index; | |
459 | else | |
460 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
461 | pm_writel(PBB_MASK, mask); |
462 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
463 | } |
464 | ||
465 | static unsigned long pbb_clk_get_rate(struct clk *clk) | |
466 | { | |
467 | unsigned long cksel, shift = 0; | |
468 | ||
7a5b8059 HS |
469 | cksel = pm_readl(CKSEL); |
470 | if (cksel & PM_BIT(PBBDIV)) | |
471 | shift = PM_BFEXT(PBBSEL, cksel) + 1; | |
5f97f7f9 HS |
472 | |
473 | return bus_clk_get_rate(clk, shift); | |
474 | } | |
475 | ||
476 | static struct clk cpu_clk = { | |
477 | .name = "cpu", | |
478 | .get_rate = cpu_clk_get_rate, | |
9e58e185 | 479 | .set_rate = cpu_clk_set_rate, |
5f97f7f9 HS |
480 | .users = 1, |
481 | }; | |
482 | static struct clk hsb_clk = { | |
483 | .name = "hsb", | |
484 | .parent = &cpu_clk, | |
485 | .get_rate = hsb_clk_get_rate, | |
486 | }; | |
487 | static struct clk pba_clk = { | |
488 | .name = "pba", | |
489 | .parent = &hsb_clk, | |
490 | .mode = hsb_clk_mode, | |
491 | .get_rate = pba_clk_get_rate, | |
492 | .index = 1, | |
493 | }; | |
494 | static struct clk pbb_clk = { | |
495 | .name = "pbb", | |
496 | .parent = &hsb_clk, | |
497 | .mode = hsb_clk_mode, | |
498 | .get_rate = pbb_clk_get_rate, | |
499 | .users = 1, | |
500 | .index = 2, | |
501 | }; | |
502 | ||
503 | /* -------------------------------------------------------------------- | |
504 | * Generic Clock operations | |
505 | * -------------------------------------------------------------------- */ | |
506 | ||
507 | static void genclk_mode(struct clk *clk, int enabled) | |
508 | { | |
509 | u32 control; | |
510 | ||
7a5b8059 | 511 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 | 512 | if (enabled) |
7a5b8059 | 513 | control |= PM_BIT(CEN); |
5f97f7f9 | 514 | else |
7a5b8059 HS |
515 | control &= ~PM_BIT(CEN); |
516 | pm_writel(GCCTRL(clk->index), control); | |
5f97f7f9 HS |
517 | } |
518 | ||
519 | static unsigned long genclk_get_rate(struct clk *clk) | |
520 | { | |
521 | u32 control; | |
522 | unsigned long div = 1; | |
523 | ||
7a5b8059 HS |
524 | control = pm_readl(GCCTRL(clk->index)); |
525 | if (control & PM_BIT(DIVEN)) | |
526 | div = 2 * (PM_BFEXT(DIV, control) + 1); | |
5f97f7f9 HS |
527 | |
528 | return clk->parent->get_rate(clk->parent) / div; | |
529 | } | |
530 | ||
531 | static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply) | |
532 | { | |
533 | u32 control; | |
534 | unsigned long parent_rate, actual_rate, div; | |
535 | ||
5f97f7f9 | 536 | parent_rate = clk->parent->get_rate(clk->parent); |
7a5b8059 | 537 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
538 | |
539 | if (rate > 3 * parent_rate / 4) { | |
540 | actual_rate = parent_rate; | |
7a5b8059 | 541 | control &= ~PM_BIT(DIVEN); |
5f97f7f9 HS |
542 | } else { |
543 | div = (parent_rate + rate) / (2 * rate) - 1; | |
7a5b8059 | 544 | control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN); |
5f97f7f9 HS |
545 | actual_rate = parent_rate / (2 * (div + 1)); |
546 | } | |
547 | ||
7a5b8059 HS |
548 | dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n", |
549 | clk->name, rate, actual_rate); | |
5f97f7f9 HS |
550 | |
551 | if (apply) | |
7a5b8059 | 552 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
553 | |
554 | return actual_rate; | |
555 | } | |
556 | ||
557 | int genclk_set_parent(struct clk *clk, struct clk *parent) | |
558 | { | |
559 | u32 control; | |
560 | ||
7a5b8059 HS |
561 | dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n", |
562 | clk->name, parent->name, clk->parent->name); | |
5f97f7f9 | 563 | |
7a5b8059 | 564 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
565 | |
566 | if (parent == &osc1 || parent == &pll1) | |
7a5b8059 | 567 | control |= PM_BIT(OSCSEL); |
5f97f7f9 | 568 | else if (parent == &osc0 || parent == &pll0) |
7a5b8059 | 569 | control &= ~PM_BIT(OSCSEL); |
5f97f7f9 HS |
570 | else |
571 | return -EINVAL; | |
572 | ||
573 | if (parent == &pll0 || parent == &pll1) | |
7a5b8059 | 574 | control |= PM_BIT(PLLSEL); |
5f97f7f9 | 575 | else |
7a5b8059 | 576 | control &= ~PM_BIT(PLLSEL); |
5f97f7f9 | 577 | |
7a5b8059 | 578 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
579 | clk->parent = parent; |
580 | ||
581 | return 0; | |
582 | } | |
583 | ||
7a5fe238 HS |
584 | static void __init genclk_init_parent(struct clk *clk) |
585 | { | |
586 | u32 control; | |
587 | struct clk *parent; | |
588 | ||
589 | BUG_ON(clk->index > 7); | |
590 | ||
7a5b8059 HS |
591 | control = pm_readl(GCCTRL(clk->index)); |
592 | if (control & PM_BIT(OSCSEL)) | |
593 | parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1; | |
7a5fe238 | 594 | else |
7a5b8059 | 595 | parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0; |
7a5fe238 HS |
596 | |
597 | clk->parent = parent; | |
598 | } | |
599 | ||
3bfb1d20 HS |
600 | static struct dw_dma_platform_data dw_dmac0_data = { |
601 | .nr_channels = 3, | |
602 | }; | |
603 | ||
604 | static struct resource dw_dmac0_resource[] = { | |
605 | PBMEM(0xff200000), | |
606 | IRQ(2), | |
607 | }; | |
608 | DEFINE_DEV_DATA(dw_dmac, 0); | |
609 | DEV_CLK(hclk, dw_dmac0, hsb, 10); | |
610 | ||
5f97f7f9 HS |
611 | /* -------------------------------------------------------------------- |
612 | * System peripherals | |
613 | * -------------------------------------------------------------------- */ | |
7a5b8059 HS |
614 | static struct resource at32_pm0_resource[] = { |
615 | { | |
616 | .start = 0xfff00000, | |
617 | .end = 0xfff0007f, | |
618 | .flags = IORESOURCE_MEM, | |
619 | }, | |
620 | IRQ(20), | |
5f97f7f9 | 621 | }; |
7a5b8059 HS |
622 | |
623 | static struct resource at32ap700x_rtc0_resource[] = { | |
624 | { | |
625 | .start = 0xfff00080, | |
626 | .end = 0xfff000af, | |
627 | .flags = IORESOURCE_MEM, | |
628 | }, | |
629 | IRQ(21), | |
5f97f7f9 | 630 | }; |
7a5b8059 HS |
631 | |
632 | static struct resource at32_wdt0_resource[] = { | |
633 | { | |
634 | .start = 0xfff000b0, | |
9797bed2 | 635 | .end = 0xfff000cf, |
7a5b8059 HS |
636 | .flags = IORESOURCE_MEM, |
637 | }, | |
638 | }; | |
639 | ||
640 | static struct resource at32_eic0_resource[] = { | |
641 | { | |
642 | .start = 0xfff00100, | |
643 | .end = 0xfff0013f, | |
644 | .flags = IORESOURCE_MEM, | |
645 | }, | |
646 | IRQ(19), | |
647 | }; | |
648 | ||
649 | DEFINE_DEV(at32_pm, 0); | |
650 | DEFINE_DEV(at32ap700x_rtc, 0); | |
651 | DEFINE_DEV(at32_wdt, 0); | |
652 | DEFINE_DEV(at32_eic, 0); | |
653 | ||
654 | /* | |
655 | * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this | |
656 | * is always running. | |
657 | */ | |
658 | static struct clk at32_pm_pclk = { | |
188ff65d | 659 | .name = "pclk", |
7a5b8059 | 660 | .dev = &at32_pm0_device.dev, |
188ff65d HS |
661 | .parent = &pbb_clk, |
662 | .mode = pbb_clk_mode, | |
663 | .get_rate = pbb_clk_get_rate, | |
664 | .users = 1, | |
665 | .index = 0, | |
666 | }; | |
5f97f7f9 HS |
667 | |
668 | static struct resource intc0_resource[] = { | |
669 | PBMEM(0xfff00400), | |
670 | }; | |
671 | struct platform_device at32_intc0_device = { | |
672 | .name = "intc", | |
673 | .id = 0, | |
674 | .resource = intc0_resource, | |
675 | .num_resources = ARRAY_SIZE(intc0_resource), | |
676 | }; | |
677 | DEV_CLK(pclk, at32_intc0, pbb, 1); | |
678 | ||
679 | static struct clk ebi_clk = { | |
680 | .name = "ebi", | |
681 | .parent = &hsb_clk, | |
682 | .mode = hsb_clk_mode, | |
683 | .get_rate = hsb_clk_get_rate, | |
684 | .users = 1, | |
685 | }; | |
686 | static struct clk hramc_clk = { | |
687 | .name = "hramc", | |
688 | .parent = &hsb_clk, | |
689 | .mode = hsb_clk_mode, | |
690 | .get_rate = hsb_clk_get_rate, | |
691 | .users = 1, | |
188ff65d | 692 | .index = 3, |
5f97f7f9 | 693 | }; |
7951f188 HS |
694 | static struct clk sdramc_clk = { |
695 | .name = "sdramc_clk", | |
696 | .parent = &pbb_clk, | |
697 | .mode = pbb_clk_mode, | |
698 | .get_rate = pbb_clk_get_rate, | |
699 | .users = 1, | |
700 | .index = 14, | |
701 | }; | |
5f97f7f9 | 702 | |
bc157b75 HS |
703 | static struct resource smc0_resource[] = { |
704 | PBMEM(0xfff03400), | |
705 | }; | |
706 | DEFINE_DEV(smc, 0); | |
707 | DEV_CLK(pclk, smc0, pbb, 13); | |
708 | DEV_CLK(mck, smc0, hsb, 0); | |
709 | ||
5f97f7f9 HS |
710 | static struct platform_device pdc_device = { |
711 | .name = "pdc", | |
712 | .id = 0, | |
713 | }; | |
714 | DEV_CLK(hclk, pdc, hsb, 4); | |
715 | DEV_CLK(pclk, pdc, pba, 16); | |
716 | ||
717 | static struct clk pico_clk = { | |
718 | .name = "pico", | |
719 | .parent = &cpu_clk, | |
720 | .mode = cpu_clk_mode, | |
721 | .get_rate = cpu_clk_get_rate, | |
722 | .users = 1, | |
723 | }; | |
724 | ||
9c8f8e75 HS |
725 | /* -------------------------------------------------------------------- |
726 | * HMATRIX | |
727 | * -------------------------------------------------------------------- */ | |
728 | ||
b47eb409 | 729 | struct clk at32_hmatrix_clk = { |
9c8f8e75 HS |
730 | .name = "hmatrix_clk", |
731 | .parent = &pbb_clk, | |
732 | .mode = pbb_clk_mode, | |
733 | .get_rate = pbb_clk_get_rate, | |
734 | .index = 2, | |
735 | .users = 1, | |
736 | }; | |
9c8f8e75 HS |
737 | |
738 | /* | |
739 | * Set bits in the HMATRIX Special Function Register (SFR) used by the | |
740 | * External Bus Interface (EBI). This can be used to enable special | |
741 | * features like CompactFlash support, NAND Flash support, etc. on | |
742 | * certain chipselects. | |
743 | */ | |
744 | static inline void set_ebi_sfr_bits(u32 mask) | |
745 | { | |
b47eb409 | 746 | hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask); |
9c8f8e75 HS |
747 | } |
748 | ||
7760989e | 749 | /* -------------------------------------------------------------------- |
e723ff66 | 750 | * Timer/Counter (TC) |
7760989e | 751 | * -------------------------------------------------------------------- */ |
e723ff66 DB |
752 | |
753 | static struct resource at32_tcb0_resource[] = { | |
7760989e HCE |
754 | PBMEM(0xfff00c00), |
755 | IRQ(22), | |
756 | }; | |
e723ff66 DB |
757 | static struct platform_device at32_tcb0_device = { |
758 | .name = "atmel_tcb", | |
7760989e | 759 | .id = 0, |
e723ff66 DB |
760 | .resource = at32_tcb0_resource, |
761 | .num_resources = ARRAY_SIZE(at32_tcb0_resource), | |
762 | }; | |
763 | DEV_CLK(t0_clk, at32_tcb0, pbb, 3); | |
764 | ||
765 | static struct resource at32_tcb1_resource[] = { | |
766 | PBMEM(0xfff01000), | |
767 | IRQ(23), | |
768 | }; | |
769 | static struct platform_device at32_tcb1_device = { | |
770 | .name = "atmel_tcb", | |
771 | .id = 1, | |
772 | .resource = at32_tcb1_resource, | |
773 | .num_resources = ARRAY_SIZE(at32_tcb1_resource), | |
7760989e | 774 | }; |
e723ff66 | 775 | DEV_CLK(t0_clk, at32_tcb1, pbb, 4); |
7760989e | 776 | |
5f97f7f9 HS |
777 | /* -------------------------------------------------------------------- |
778 | * PIO | |
779 | * -------------------------------------------------------------------- */ | |
780 | ||
781 | static struct resource pio0_resource[] = { | |
782 | PBMEM(0xffe02800), | |
783 | IRQ(13), | |
784 | }; | |
785 | DEFINE_DEV(pio, 0); | |
786 | DEV_CLK(mck, pio0, pba, 10); | |
787 | ||
788 | static struct resource pio1_resource[] = { | |
789 | PBMEM(0xffe02c00), | |
790 | IRQ(14), | |
791 | }; | |
792 | DEFINE_DEV(pio, 1); | |
793 | DEV_CLK(mck, pio1, pba, 11); | |
794 | ||
795 | static struct resource pio2_resource[] = { | |
796 | PBMEM(0xffe03000), | |
797 | IRQ(15), | |
798 | }; | |
799 | DEFINE_DEV(pio, 2); | |
800 | DEV_CLK(mck, pio2, pba, 12); | |
801 | ||
802 | static struct resource pio3_resource[] = { | |
803 | PBMEM(0xffe03400), | |
804 | IRQ(16), | |
805 | }; | |
806 | DEFINE_DEV(pio, 3); | |
807 | DEV_CLK(mck, pio3, pba, 13); | |
808 | ||
7f9f4678 HS |
809 | static struct resource pio4_resource[] = { |
810 | PBMEM(0xffe03800), | |
811 | IRQ(17), | |
812 | }; | |
813 | DEFINE_DEV(pio, 4); | |
814 | DEV_CLK(mck, pio4, pba, 14); | |
815 | ||
e82c6106 | 816 | static int __init system_device_init(void) |
5f97f7f9 | 817 | { |
7a5b8059 | 818 | platform_device_register(&at32_pm0_device); |
5f97f7f9 | 819 | platform_device_register(&at32_intc0_device); |
7a5b8059 HS |
820 | platform_device_register(&at32ap700x_rtc0_device); |
821 | platform_device_register(&at32_wdt0_device); | |
822 | platform_device_register(&at32_eic0_device); | |
bc157b75 | 823 | platform_device_register(&smc0_device); |
5f97f7f9 | 824 | platform_device_register(&pdc_device); |
3bfb1d20 | 825 | platform_device_register(&dw_dmac0_device); |
5f97f7f9 | 826 | |
e723ff66 DB |
827 | platform_device_register(&at32_tcb0_device); |
828 | platform_device_register(&at32_tcb1_device); | |
7760989e | 829 | |
5f97f7f9 HS |
830 | platform_device_register(&pio0_device); |
831 | platform_device_register(&pio1_device); | |
832 | platform_device_register(&pio2_device); | |
833 | platform_device_register(&pio3_device); | |
7f9f4678 | 834 | platform_device_register(&pio4_device); |
e82c6106 HS |
835 | |
836 | return 0; | |
5f97f7f9 | 837 | } |
e82c6106 | 838 | core_initcall(system_device_init); |
5f97f7f9 | 839 | |
d86d314f HCE |
840 | /* -------------------------------------------------------------------- |
841 | * PSIF | |
842 | * -------------------------------------------------------------------- */ | |
843 | static struct resource atmel_psif0_resource[] __initdata = { | |
844 | { | |
845 | .start = 0xffe03c00, | |
846 | .end = 0xffe03cff, | |
847 | .flags = IORESOURCE_MEM, | |
848 | }, | |
849 | IRQ(18), | |
850 | }; | |
851 | static struct clk atmel_psif0_pclk = { | |
852 | .name = "pclk", | |
853 | .parent = &pba_clk, | |
854 | .mode = pba_clk_mode, | |
855 | .get_rate = pba_clk_get_rate, | |
856 | .index = 15, | |
857 | }; | |
858 | ||
859 | static struct resource atmel_psif1_resource[] __initdata = { | |
860 | { | |
861 | .start = 0xffe03d00, | |
862 | .end = 0xffe03dff, | |
863 | .flags = IORESOURCE_MEM, | |
864 | }, | |
865 | IRQ(18), | |
866 | }; | |
867 | static struct clk atmel_psif1_pclk = { | |
868 | .name = "pclk", | |
869 | .parent = &pba_clk, | |
870 | .mode = pba_clk_mode, | |
871 | .get_rate = pba_clk_get_rate, | |
872 | .index = 15, | |
873 | }; | |
874 | ||
875 | struct platform_device *__init at32_add_device_psif(unsigned int id) | |
876 | { | |
877 | struct platform_device *pdev; | |
caf18f19 | 878 | u32 pin_mask; |
d86d314f HCE |
879 | |
880 | if (!(id == 0 || id == 1)) | |
881 | return NULL; | |
882 | ||
883 | pdev = platform_device_alloc("atmel_psif", id); | |
884 | if (!pdev) | |
885 | return NULL; | |
886 | ||
887 | switch (id) { | |
888 | case 0: | |
caf18f19 JM |
889 | pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */ |
890 | ||
d86d314f HCE |
891 | if (platform_device_add_resources(pdev, atmel_psif0_resource, |
892 | ARRAY_SIZE(atmel_psif0_resource))) | |
893 | goto err_add_resources; | |
894 | atmel_psif0_pclk.dev = &pdev->dev; | |
caf18f19 | 895 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); |
d86d314f HCE |
896 | break; |
897 | case 1: | |
caf18f19 JM |
898 | pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */ |
899 | ||
d86d314f HCE |
900 | if (platform_device_add_resources(pdev, atmel_psif1_resource, |
901 | ARRAY_SIZE(atmel_psif1_resource))) | |
902 | goto err_add_resources; | |
903 | atmel_psif1_pclk.dev = &pdev->dev; | |
caf18f19 | 904 | select_peripheral(PIOB, pin_mask, PERIPH_A, 0); |
d86d314f HCE |
905 | break; |
906 | default: | |
907 | return NULL; | |
908 | } | |
909 | ||
910 | platform_device_add(pdev); | |
911 | return pdev; | |
912 | ||
913 | err_add_resources: | |
914 | platform_device_put(pdev); | |
915 | return NULL; | |
916 | } | |
917 | ||
5f97f7f9 HS |
918 | /* -------------------------------------------------------------------- |
919 | * USART | |
920 | * -------------------------------------------------------------------- */ | |
921 | ||
75d35213 HS |
922 | static struct atmel_uart_data atmel_usart0_data = { |
923 | .use_dma_tx = 1, | |
924 | .use_dma_rx = 1, | |
925 | }; | |
1e8ea802 | 926 | static struct resource atmel_usart0_resource[] = { |
5f97f7f9 | 927 | PBMEM(0xffe00c00), |
a3d912c8 | 928 | IRQ(6), |
5f97f7f9 | 929 | }; |
75d35213 | 930 | DEFINE_DEV_DATA(atmel_usart, 0); |
80f76c54 | 931 | DEV_CLK(usart, atmel_usart0, pba, 3); |
5f97f7f9 | 932 | |
75d35213 HS |
933 | static struct atmel_uart_data atmel_usart1_data = { |
934 | .use_dma_tx = 1, | |
935 | .use_dma_rx = 1, | |
936 | }; | |
1e8ea802 | 937 | static struct resource atmel_usart1_resource[] = { |
5f97f7f9 HS |
938 | PBMEM(0xffe01000), |
939 | IRQ(7), | |
940 | }; | |
75d35213 | 941 | DEFINE_DEV_DATA(atmel_usart, 1); |
1e8ea802 | 942 | DEV_CLK(usart, atmel_usart1, pba, 4); |
5f97f7f9 | 943 | |
75d35213 HS |
944 | static struct atmel_uart_data atmel_usart2_data = { |
945 | .use_dma_tx = 1, | |
946 | .use_dma_rx = 1, | |
947 | }; | |
1e8ea802 | 948 | static struct resource atmel_usart2_resource[] = { |
5f97f7f9 HS |
949 | PBMEM(0xffe01400), |
950 | IRQ(8), | |
951 | }; | |
75d35213 | 952 | DEFINE_DEV_DATA(atmel_usart, 2); |
1e8ea802 | 953 | DEV_CLK(usart, atmel_usart2, pba, 5); |
5f97f7f9 | 954 | |
75d35213 HS |
955 | static struct atmel_uart_data atmel_usart3_data = { |
956 | .use_dma_tx = 1, | |
957 | .use_dma_rx = 1, | |
958 | }; | |
1e8ea802 | 959 | static struct resource atmel_usart3_resource[] = { |
5f97f7f9 HS |
960 | PBMEM(0xffe01800), |
961 | IRQ(9), | |
962 | }; | |
75d35213 | 963 | DEFINE_DEV_DATA(atmel_usart, 3); |
1e8ea802 | 964 | DEV_CLK(usart, atmel_usart3, pba, 6); |
5f97f7f9 HS |
965 | |
966 | static inline void configure_usart0_pins(void) | |
967 | { | |
caf18f19 JM |
968 | u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */ |
969 | ||
10546263 | 970 | select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); |
5f97f7f9 HS |
971 | } |
972 | ||
973 | static inline void configure_usart1_pins(void) | |
974 | { | |
caf18f19 JM |
975 | u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */ |
976 | ||
10546263 | 977 | select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP); |
5f97f7f9 HS |
978 | } |
979 | ||
980 | static inline void configure_usart2_pins(void) | |
981 | { | |
caf18f19 JM |
982 | u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */ |
983 | ||
10546263 | 984 | select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); |
5f97f7f9 HS |
985 | } |
986 | ||
987 | static inline void configure_usart3_pins(void) | |
988 | { | |
caf18f19 JM |
989 | u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */ |
990 | ||
10546263 | 991 | select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); |
5f97f7f9 HS |
992 | } |
993 | ||
a3d912c8 | 994 | static struct platform_device *__initdata at32_usarts[4]; |
c194588d HS |
995 | |
996 | void __init at32_map_usart(unsigned int hw_id, unsigned int line) | |
5f97f7f9 HS |
997 | { |
998 | struct platform_device *pdev; | |
999 | ||
c194588d | 1000 | switch (hw_id) { |
5f97f7f9 | 1001 | case 0: |
1e8ea802 | 1002 | pdev = &atmel_usart0_device; |
5f97f7f9 HS |
1003 | configure_usart0_pins(); |
1004 | break; | |
1005 | case 1: | |
1e8ea802 | 1006 | pdev = &atmel_usart1_device; |
5f97f7f9 HS |
1007 | configure_usart1_pins(); |
1008 | break; | |
1009 | case 2: | |
1e8ea802 | 1010 | pdev = &atmel_usart2_device; |
5f97f7f9 HS |
1011 | configure_usart2_pins(); |
1012 | break; | |
1013 | case 3: | |
1e8ea802 | 1014 | pdev = &atmel_usart3_device; |
5f97f7f9 HS |
1015 | configure_usart3_pins(); |
1016 | break; | |
1017 | default: | |
c194588d | 1018 | return; |
75d35213 HS |
1019 | } |
1020 | ||
1021 | if (PXSEG(pdev->resource[0].start) == P4SEG) { | |
1022 | /* Addresses in the P4 segment are permanently mapped 1:1 */ | |
1023 | struct atmel_uart_data *data = pdev->dev.platform_data; | |
1024 | data->regs = (void __iomem *)pdev->resource[0].start; | |
5f97f7f9 HS |
1025 | } |
1026 | ||
c194588d HS |
1027 | pdev->id = line; |
1028 | at32_usarts[line] = pdev; | |
5f97f7f9 HS |
1029 | } |
1030 | ||
1031 | struct platform_device *__init at32_add_device_usart(unsigned int id) | |
1032 | { | |
c194588d HS |
1033 | platform_device_register(at32_usarts[id]); |
1034 | return at32_usarts[id]; | |
5f97f7f9 HS |
1035 | } |
1036 | ||
73e2798b | 1037 | struct platform_device *atmel_default_console_device; |
5f97f7f9 HS |
1038 | |
1039 | void __init at32_setup_serial_console(unsigned int usart_id) | |
1040 | { | |
c194588d | 1041 | atmel_default_console_device = at32_usarts[usart_id]; |
5f97f7f9 HS |
1042 | } |
1043 | ||
1044 | /* -------------------------------------------------------------------- | |
1045 | * Ethernet | |
1046 | * -------------------------------------------------------------------- */ | |
1047 | ||
438ff3f3 | 1048 | #ifdef CONFIG_CPU_AT32AP7000 |
5f97f7f9 HS |
1049 | static struct eth_platform_data macb0_data; |
1050 | static struct resource macb0_resource[] = { | |
1051 | PBMEM(0xfff01800), | |
1052 | IRQ(25), | |
1053 | }; | |
1054 | DEFINE_DEV_DATA(macb, 0); | |
1055 | DEV_CLK(hclk, macb0, hsb, 8); | |
1056 | DEV_CLK(pclk, macb0, pbb, 6); | |
1057 | ||
cfcb3a89 HS |
1058 | static struct eth_platform_data macb1_data; |
1059 | static struct resource macb1_resource[] = { | |
1060 | PBMEM(0xfff01c00), | |
1061 | IRQ(26), | |
1062 | }; | |
1063 | DEFINE_DEV_DATA(macb, 1); | |
1064 | DEV_CLK(hclk, macb1, hsb, 9); | |
1065 | DEV_CLK(pclk, macb1, pbb, 7); | |
1066 | ||
5f97f7f9 HS |
1067 | struct platform_device *__init |
1068 | at32_add_device_eth(unsigned int id, struct eth_platform_data *data) | |
1069 | { | |
1070 | struct platform_device *pdev; | |
caf18f19 | 1071 | u32 pin_mask; |
5f97f7f9 HS |
1072 | |
1073 | switch (id) { | |
1074 | case 0: | |
1075 | pdev = &macb0_device; | |
1076 | ||
caf18f19 JM |
1077 | pin_mask = (1 << 3); /* TXD0 */ |
1078 | pin_mask |= (1 << 4); /* TXD1 */ | |
1079 | pin_mask |= (1 << 7); /* TXEN */ | |
1080 | pin_mask |= (1 << 8); /* TXCK */ | |
1081 | pin_mask |= (1 << 9); /* RXD0 */ | |
1082 | pin_mask |= (1 << 10); /* RXD1 */ | |
1083 | pin_mask |= (1 << 13); /* RXER */ | |
1084 | pin_mask |= (1 << 15); /* RXDV */ | |
1085 | pin_mask |= (1 << 16); /* MDC */ | |
1086 | pin_mask |= (1 << 17); /* MDIO */ | |
5f97f7f9 HS |
1087 | |
1088 | if (!data->is_rmii) { | |
caf18f19 JM |
1089 | pin_mask |= (1 << 0); /* COL */ |
1090 | pin_mask |= (1 << 1); /* CRS */ | |
1091 | pin_mask |= (1 << 2); /* TXER */ | |
1092 | pin_mask |= (1 << 5); /* TXD2 */ | |
1093 | pin_mask |= (1 << 6); /* TXD3 */ | |
1094 | pin_mask |= (1 << 11); /* RXD2 */ | |
1095 | pin_mask |= (1 << 12); /* RXD3 */ | |
1096 | pin_mask |= (1 << 14); /* RXCK */ | |
198f2935 | 1097 | #ifndef CONFIG_BOARD_MIMC200 |
caf18f19 | 1098 | pin_mask |= (1 << 18); /* SPD */ |
198f2935 | 1099 | #endif |
5f97f7f9 | 1100 | } |
caf18f19 JM |
1101 | |
1102 | select_peripheral(PIOC, pin_mask, PERIPH_A, 0); | |
1103 | ||
5f97f7f9 HS |
1104 | break; |
1105 | ||
cfcb3a89 HS |
1106 | case 1: |
1107 | pdev = &macb1_device; | |
1108 | ||
caf18f19 JM |
1109 | pin_mask = (1 << 13); /* TXD0 */ |
1110 | pin_mask |= (1 << 14); /* TXD1 */ | |
1111 | pin_mask |= (1 << 11); /* TXEN */ | |
1112 | pin_mask |= (1 << 12); /* TXCK */ | |
1113 | pin_mask |= (1 << 10); /* RXD0 */ | |
1114 | pin_mask |= (1 << 6); /* RXD1 */ | |
1115 | pin_mask |= (1 << 5); /* RXER */ | |
1116 | pin_mask |= (1 << 4); /* RXDV */ | |
1117 | pin_mask |= (1 << 3); /* MDC */ | |
1118 | pin_mask |= (1 << 2); /* MDIO */ | |
1119 | ||
198f2935 | 1120 | #ifndef CONFIG_BOARD_MIMC200 |
caf18f19 JM |
1121 | if (!data->is_rmii) |
1122 | pin_mask |= (1 << 15); /* SPD */ | |
198f2935 | 1123 | #endif |
caf18f19 JM |
1124 | |
1125 | select_peripheral(PIOD, pin_mask, PERIPH_B, 0); | |
cfcb3a89 HS |
1126 | |
1127 | if (!data->is_rmii) { | |
caf18f19 JM |
1128 | pin_mask = (1 << 19); /* COL */ |
1129 | pin_mask |= (1 << 23); /* CRS */ | |
1130 | pin_mask |= (1 << 26); /* TXER */ | |
1131 | pin_mask |= (1 << 27); /* TXD2 */ | |
1132 | pin_mask |= (1 << 28); /* TXD3 */ | |
1133 | pin_mask |= (1 << 29); /* RXD2 */ | |
1134 | pin_mask |= (1 << 30); /* RXD3 */ | |
1135 | pin_mask |= (1 << 24); /* RXCK */ | |
1136 | ||
1137 | select_peripheral(PIOC, pin_mask, PERIPH_B, 0); | |
cfcb3a89 HS |
1138 | } |
1139 | break; | |
1140 | ||
5f97f7f9 HS |
1141 | default: |
1142 | return NULL; | |
1143 | } | |
1144 | ||
1145 | memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data)); | |
1146 | platform_device_register(pdev); | |
1147 | ||
1148 | return pdev; | |
1149 | } | |
438ff3f3 | 1150 | #endif |
5f97f7f9 HS |
1151 | |
1152 | /* -------------------------------------------------------------------- | |
1153 | * SPI | |
1154 | * -------------------------------------------------------------------- */ | |
3d60ee1b | 1155 | static struct resource atmel_spi0_resource[] = { |
5f97f7f9 HS |
1156 | PBMEM(0xffe00000), |
1157 | IRQ(3), | |
1158 | }; | |
3d60ee1b HS |
1159 | DEFINE_DEV(atmel_spi, 0); |
1160 | DEV_CLK(spi_clk, atmel_spi0, pba, 0); | |
1161 | ||
1162 | static struct resource atmel_spi1_resource[] = { | |
1163 | PBMEM(0xffe00400), | |
1164 | IRQ(4), | |
1165 | }; | |
1166 | DEFINE_DEV(atmel_spi, 1); | |
1167 | DEV_CLK(spi_clk, atmel_spi1, pba, 1); | |
5f97f7f9 | 1168 | |
9a596a62 | 1169 | static void __init |
41d8ca45 HS |
1170 | at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, |
1171 | unsigned int n, const u8 *pins) | |
5f97f7f9 | 1172 | { |
41d8ca45 HS |
1173 | unsigned int pin, mode; |
1174 | ||
1175 | for (; n; n--, b++) { | |
1176 | b->bus_num = bus_num; | |
1177 | if (b->chip_select >= 4) | |
1178 | continue; | |
1179 | pin = (unsigned)b->controller_data; | |
1180 | if (!pin) { | |
1181 | pin = pins[b->chip_select]; | |
1182 | b->controller_data = (void *)pin; | |
1183 | } | |
1184 | mode = AT32_GPIOF_OUTPUT; | |
1185 | if (!(b->mode & SPI_CS_HIGH)) | |
1186 | mode |= AT32_GPIOF_HIGH; | |
1187 | at32_select_gpio(pin, mode); | |
1188 | } | |
1189 | } | |
1190 | ||
1191 | struct platform_device *__init | |
1192 | at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n) | |
1193 | { | |
1194 | /* | |
1195 | * Manage the chipselects as GPIOs, normally using the same pins | |
1196 | * the SPI controller expects; but boards can use other pins. | |
1197 | */ | |
1198 | static u8 __initdata spi0_pins[] = | |
1199 | { GPIO_PIN_PA(3), GPIO_PIN_PA(4), | |
1200 | GPIO_PIN_PA(5), GPIO_PIN_PA(20), }; | |
1201 | static u8 __initdata spi1_pins[] = | |
1202 | { GPIO_PIN_PB(2), GPIO_PIN_PB(3), | |
1203 | GPIO_PIN_PB(4), GPIO_PIN_PA(27), }; | |
5f97f7f9 | 1204 | struct platform_device *pdev; |
caf18f19 | 1205 | u32 pin_mask; |
5f97f7f9 HS |
1206 | |
1207 | switch (id) { | |
1208 | case 0: | |
3d60ee1b | 1209 | pdev = &atmel_spi0_device; |
caf18f19 JM |
1210 | pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */ |
1211 | ||
9c2baf78 | 1212 | /* pullup MISO so a level is always defined */ |
caf18f19 JM |
1213 | select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP); |
1214 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); | |
1215 | ||
41d8ca45 | 1216 | at32_spi_setup_slaves(0, b, n, spi0_pins); |
3d60ee1b HS |
1217 | break; |
1218 | ||
1219 | case 1: | |
1220 | pdev = &atmel_spi1_device; | |
caf18f19 JM |
1221 | pin_mask = (1 << 1) | (1 << 5); /* MOSI */ |
1222 | ||
9c2baf78 | 1223 | /* pullup MISO so a level is always defined */ |
caf18f19 JM |
1224 | select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP); |
1225 | select_peripheral(PIOB, pin_mask, PERIPH_B, 0); | |
1226 | ||
41d8ca45 | 1227 | at32_spi_setup_slaves(1, b, n, spi1_pins); |
5f97f7f9 HS |
1228 | break; |
1229 | ||
1230 | default: | |
1231 | return NULL; | |
1232 | } | |
1233 | ||
41d8ca45 | 1234 | spi_register_board_info(b, n); |
5f97f7f9 HS |
1235 | platform_device_register(pdev); |
1236 | return pdev; | |
1237 | } | |
1238 | ||
2042c1c4 HS |
1239 | /* -------------------------------------------------------------------- |
1240 | * TWI | |
1241 | * -------------------------------------------------------------------- */ | |
1242 | static struct resource atmel_twi0_resource[] __initdata = { | |
1243 | PBMEM(0xffe00800), | |
1244 | IRQ(5), | |
1245 | }; | |
1246 | static struct clk atmel_twi0_pclk = { | |
1247 | .name = "twi_pclk", | |
1248 | .parent = &pba_clk, | |
1249 | .mode = pba_clk_mode, | |
1250 | .get_rate = pba_clk_get_rate, | |
1251 | .index = 2, | |
1252 | }; | |
1253 | ||
040b28fc BN |
1254 | struct platform_device *__init at32_add_device_twi(unsigned int id, |
1255 | struct i2c_board_info *b, | |
1256 | unsigned int n) | |
2042c1c4 HS |
1257 | { |
1258 | struct platform_device *pdev; | |
caf18f19 | 1259 | u32 pin_mask; |
2042c1c4 HS |
1260 | |
1261 | if (id != 0) | |
1262 | return NULL; | |
1263 | ||
1264 | pdev = platform_device_alloc("atmel_twi", id); | |
1265 | if (!pdev) | |
1266 | return NULL; | |
1267 | ||
1268 | if (platform_device_add_resources(pdev, atmel_twi0_resource, | |
1269 | ARRAY_SIZE(atmel_twi0_resource))) | |
1270 | goto err_add_resources; | |
1271 | ||
caf18f19 JM |
1272 | pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */ |
1273 | ||
1274 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); | |
2042c1c4 HS |
1275 | |
1276 | atmel_twi0_pclk.dev = &pdev->dev; | |
1277 | ||
040b28fc BN |
1278 | if (b) |
1279 | i2c_register_board_info(id, b, n); | |
1280 | ||
2042c1c4 HS |
1281 | platform_device_add(pdev); |
1282 | return pdev; | |
1283 | ||
1284 | err_add_resources: | |
1285 | platform_device_put(pdev); | |
1286 | return NULL; | |
1287 | } | |
1288 | ||
1289 | /* -------------------------------------------------------------------- | |
1290 | * MMC | |
1291 | * -------------------------------------------------------------------- */ | |
1292 | static struct resource atmel_mci0_resource[] __initdata = { | |
1293 | PBMEM(0xfff02400), | |
1294 | IRQ(28), | |
1295 | }; | |
1296 | static struct clk atmel_mci0_pclk = { | |
1297 | .name = "mci_clk", | |
1298 | .parent = &pbb_clk, | |
1299 | .mode = pbb_clk_mode, | |
1300 | .get_rate = pbb_clk_get_rate, | |
1301 | .index = 9, | |
1302 | }; | |
1303 | ||
7d2be074 HS |
1304 | struct platform_device *__init |
1305 | at32_add_device_mci(unsigned int id, struct mci_platform_data *data) | |
2042c1c4 | 1306 | { |
7d2be074 | 1307 | struct platform_device *pdev; |
65e8b083 | 1308 | struct dw_dma_slave *dws; |
caf18f19 JM |
1309 | u32 pioa_mask; |
1310 | u32 piob_mask; | |
2042c1c4 | 1311 | |
6b918657 HS |
1312 | if (id != 0 || !data) |
1313 | return NULL; | |
1314 | ||
1315 | /* Must have at least one usable slot */ | |
1316 | if (!data->slot[0].bus_width && !data->slot[1].bus_width) | |
2042c1c4 HS |
1317 | return NULL; |
1318 | ||
1319 | pdev = platform_device_alloc("atmel_mci", id); | |
1320 | if (!pdev) | |
7d2be074 | 1321 | goto fail; |
2042c1c4 HS |
1322 | |
1323 | if (platform_device_add_resources(pdev, atmel_mci0_resource, | |
1324 | ARRAY_SIZE(atmel_mci0_resource))) | |
7d2be074 HS |
1325 | goto fail; |
1326 | ||
65e8b083 HS |
1327 | if (data->dma_slave) |
1328 | dws = kmemdup(to_dw_dma_slave(data->dma_slave), | |
1329 | sizeof(struct dw_dma_slave), GFP_KERNEL); | |
1330 | else | |
1331 | dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL); | |
1332 | ||
1333 | dws->slave.dev = &pdev->dev; | |
1334 | dws->slave.dma_dev = &dw_dmac0_device.dev; | |
1335 | dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT; | |
1336 | dws->cfg_hi = (DWC_CFGH_SRC_PER(0) | |
1337 | | DWC_CFGH_DST_PER(1)); | |
1338 | dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | |
1339 | | DWC_CFGL_HS_SRC_POL); | |
1340 | ||
1341 | data->dma_slave = &dws->slave; | |
7d2be074 HS |
1342 | |
1343 | if (platform_device_add_data(pdev, data, | |
1344 | sizeof(struct mci_platform_data))) | |
1345 | goto fail; | |
2042c1c4 | 1346 | |
6b918657 | 1347 | /* CLK line is common to both slots */ |
caf18f19 | 1348 | pioa_mask = 1 << 10; |
6b918657 HS |
1349 | |
1350 | switch (data->slot[0].bus_width) { | |
1351 | case 4: | |
caf18f19 JM |
1352 | pioa_mask |= 1 << 13; /* DATA1 */ |
1353 | pioa_mask |= 1 << 14; /* DATA2 */ | |
1354 | pioa_mask |= 1 << 15; /* DATA3 */ | |
6b918657 HS |
1355 | /* fall through */ |
1356 | case 1: | |
caf18f19 JM |
1357 | pioa_mask |= 1 << 11; /* CMD */ |
1358 | pioa_mask |= 1 << 12; /* DATA0 */ | |
6b918657 HS |
1359 | |
1360 | if (gpio_is_valid(data->slot[0].detect_pin)) | |
1361 | at32_select_gpio(data->slot[0].detect_pin, 0); | |
1362 | if (gpio_is_valid(data->slot[0].wp_pin)) | |
1363 | at32_select_gpio(data->slot[0].wp_pin, 0); | |
1364 | break; | |
1365 | case 0: | |
1366 | /* Slot is unused */ | |
1367 | break; | |
1368 | default: | |
1369 | goto fail; | |
1370 | } | |
1371 | ||
caf18f19 JM |
1372 | select_peripheral(PIOA, pioa_mask, PERIPH_A, 0); |
1373 | piob_mask = 0; | |
1374 | ||
6b918657 HS |
1375 | switch (data->slot[1].bus_width) { |
1376 | case 4: | |
caf18f19 JM |
1377 | piob_mask |= 1 << 8; /* DATA1 */ |
1378 | piob_mask |= 1 << 9; /* DATA2 */ | |
1379 | piob_mask |= 1 << 10; /* DATA3 */ | |
6b918657 HS |
1380 | /* fall through */ |
1381 | case 1: | |
caf18f19 JM |
1382 | piob_mask |= 1 << 6; /* CMD */ |
1383 | piob_mask |= 1 << 7; /* DATA0 */ | |
1384 | select_peripheral(PIOB, piob_mask, PERIPH_B, 0); | |
6b918657 HS |
1385 | |
1386 | if (gpio_is_valid(data->slot[1].detect_pin)) | |
1387 | at32_select_gpio(data->slot[1].detect_pin, 0); | |
1388 | if (gpio_is_valid(data->slot[1].wp_pin)) | |
1389 | at32_select_gpio(data->slot[1].wp_pin, 0); | |
1390 | break; | |
1391 | case 0: | |
1392 | /* Slot is unused */ | |
1393 | break; | |
1394 | default: | |
1395 | if (!data->slot[0].bus_width) | |
1396 | goto fail; | |
1397 | ||
1398 | data->slot[1].bus_width = 0; | |
1399 | break; | |
1400 | } | |
7d2be074 | 1401 | |
2042c1c4 HS |
1402 | atmel_mci0_pclk.dev = &pdev->dev; |
1403 | ||
1404 | platform_device_add(pdev); | |
1405 | return pdev; | |
1406 | ||
7d2be074 | 1407 | fail: |
2042c1c4 HS |
1408 | platform_device_put(pdev); |
1409 | return NULL; | |
1410 | } | |
1411 | ||
5f97f7f9 HS |
1412 | /* -------------------------------------------------------------------- |
1413 | * LCDC | |
1414 | * -------------------------------------------------------------------- */ | |
438ff3f3 | 1415 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af HS |
1416 | static struct atmel_lcdfb_info atmel_lcdfb0_data; |
1417 | static struct resource atmel_lcdfb0_resource[] = { | |
5f97f7f9 HS |
1418 | { |
1419 | .start = 0xff000000, | |
1420 | .end = 0xff000fff, | |
1421 | .flags = IORESOURCE_MEM, | |
1422 | }, | |
1423 | IRQ(1), | |
d0a2b7af HS |
1424 | { |
1425 | /* Placeholder for pre-allocated fb memory */ | |
1426 | .start = 0x00000000, | |
1427 | .end = 0x00000000, | |
1428 | .flags = 0, | |
1429 | }, | |
5f97f7f9 | 1430 | }; |
d0a2b7af HS |
1431 | DEFINE_DEV_DATA(atmel_lcdfb, 0); |
1432 | DEV_CLK(hck1, atmel_lcdfb0, hsb, 7); | |
1433 | static struct clk atmel_lcdfb0_pixclk = { | |
1434 | .name = "lcdc_clk", | |
1435 | .dev = &atmel_lcdfb0_device.dev, | |
5f97f7f9 HS |
1436 | .mode = genclk_mode, |
1437 | .get_rate = genclk_get_rate, | |
1438 | .set_rate = genclk_set_rate, | |
1439 | .set_parent = genclk_set_parent, | |
1440 | .index = 7, | |
1441 | }; | |
1442 | ||
1443 | struct platform_device *__init | |
d0a2b7af | 1444 | at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, |
47882cf6 | 1445 | unsigned long fbmem_start, unsigned long fbmem_len, |
70664124 | 1446 | u64 pin_mask) |
5f97f7f9 HS |
1447 | { |
1448 | struct platform_device *pdev; | |
d0a2b7af HS |
1449 | struct atmel_lcdfb_info *info; |
1450 | struct fb_monspecs *monspecs; | |
1451 | struct fb_videomode *modedb; | |
1452 | unsigned int modedb_size; | |
caf18f19 | 1453 | u32 portc_mask, portd_mask, porte_mask; |
d0a2b7af HS |
1454 | |
1455 | /* | |
1456 | * Do a deep copy of the fb data, monspecs and modedb. Make | |
1457 | * sure all allocations are done before setting up the | |
1458 | * portmux. | |
1459 | */ | |
1460 | monspecs = kmemdup(data->default_monspecs, | |
1461 | sizeof(struct fb_monspecs), GFP_KERNEL); | |
1462 | if (!monspecs) | |
1463 | return NULL; | |
1464 | ||
1465 | modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len; | |
1466 | modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL); | |
1467 | if (!modedb) | |
1468 | goto err_dup_modedb; | |
1469 | monspecs->modedb = modedb; | |
5f97f7f9 HS |
1470 | |
1471 | switch (id) { | |
1472 | case 0: | |
d0a2b7af | 1473 | pdev = &atmel_lcdfb0_device; |
47882cf6 | 1474 | |
70664124 JM |
1475 | if (pin_mask == 0ULL) |
1476 | /* Default to "full" lcdc control signals and 24bit */ | |
1477 | pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL; | |
1478 | ||
1479 | /* LCDC on port C */ | |
60900656 | 1480 | portc_mask = pin_mask & 0xfff80000; |
caf18f19 | 1481 | select_peripheral(PIOC, portc_mask, PERIPH_A, 0); |
70664124 JM |
1482 | |
1483 | /* LCDC on port D */ | |
caf18f19 JM |
1484 | portd_mask = pin_mask & 0x0003ffff; |
1485 | select_peripheral(PIOD, portd_mask, PERIPH_A, 0); | |
70664124 JM |
1486 | |
1487 | /* LCDC on port E */ | |
caf18f19 JM |
1488 | porte_mask = (pin_mask >> 32) & 0x0007ffff; |
1489 | select_peripheral(PIOE, porte_mask, PERIPH_B, 0); | |
5f97f7f9 | 1490 | |
d0a2b7af HS |
1491 | clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); |
1492 | clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); | |
5f97f7f9 HS |
1493 | break; |
1494 | ||
1495 | default: | |
d0a2b7af | 1496 | goto err_invalid_id; |
5f97f7f9 HS |
1497 | } |
1498 | ||
d0a2b7af HS |
1499 | if (fbmem_len) { |
1500 | pdev->resource[2].start = fbmem_start; | |
1501 | pdev->resource[2].end = fbmem_start + fbmem_len - 1; | |
1502 | pdev->resource[2].flags = IORESOURCE_MEM; | |
1503 | } | |
1504 | ||
1505 | info = pdev->dev.platform_data; | |
1506 | memcpy(info, data, sizeof(struct atmel_lcdfb_info)); | |
1507 | info->default_monspecs = monspecs; | |
5f97f7f9 HS |
1508 | |
1509 | platform_device_register(pdev); | |
1510 | return pdev; | |
d0a2b7af HS |
1511 | |
1512 | err_invalid_id: | |
1513 | kfree(modedb); | |
1514 | err_dup_modedb: | |
1515 | kfree(monspecs); | |
1516 | return NULL; | |
5f97f7f9 | 1517 | } |
438ff3f3 | 1518 | #endif |
5f97f7f9 | 1519 | |
9a1e8eb1 DB |
1520 | /* -------------------------------------------------------------------- |
1521 | * PWM | |
1522 | * -------------------------------------------------------------------- */ | |
1523 | static struct resource atmel_pwm0_resource[] __initdata = { | |
1524 | PBMEM(0xfff01400), | |
1525 | IRQ(24), | |
1526 | }; | |
1527 | static struct clk atmel_pwm0_mck = { | |
8405996f | 1528 | .name = "pwm_clk", |
9a1e8eb1 DB |
1529 | .parent = &pbb_clk, |
1530 | .mode = pbb_clk_mode, | |
1531 | .get_rate = pbb_clk_get_rate, | |
1532 | .index = 5, | |
1533 | }; | |
1534 | ||
1535 | struct platform_device *__init at32_add_device_pwm(u32 mask) | |
1536 | { | |
1537 | struct platform_device *pdev; | |
caf18f19 | 1538 | u32 pin_mask; |
9a1e8eb1 DB |
1539 | |
1540 | if (!mask) | |
1541 | return NULL; | |
1542 | ||
1543 | pdev = platform_device_alloc("atmel_pwm", 0); | |
1544 | if (!pdev) | |
1545 | return NULL; | |
1546 | ||
1547 | if (platform_device_add_resources(pdev, atmel_pwm0_resource, | |
1548 | ARRAY_SIZE(atmel_pwm0_resource))) | |
1549 | goto out_free_pdev; | |
1550 | ||
1551 | if (platform_device_add_data(pdev, &mask, sizeof(mask))) | |
1552 | goto out_free_pdev; | |
1553 | ||
caf18f19 | 1554 | pin_mask = 0; |
9a1e8eb1 | 1555 | if (mask & (1 << 0)) |
caf18f19 | 1556 | pin_mask |= (1 << 28); |
9a1e8eb1 | 1557 | if (mask & (1 << 1)) |
caf18f19 JM |
1558 | pin_mask |= (1 << 29); |
1559 | if (pin_mask > 0) | |
1560 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); | |
1561 | ||
1562 | pin_mask = 0; | |
9a1e8eb1 | 1563 | if (mask & (1 << 2)) |
caf18f19 | 1564 | pin_mask |= (1 << 21); |
9a1e8eb1 | 1565 | if (mask & (1 << 3)) |
caf18f19 JM |
1566 | pin_mask |= (1 << 22); |
1567 | if (pin_mask > 0) | |
1568 | select_peripheral(PIOA, pin_mask, PERIPH_B, 0); | |
9a1e8eb1 DB |
1569 | |
1570 | atmel_pwm0_mck.dev = &pdev->dev; | |
1571 | ||
1572 | platform_device_add(pdev); | |
1573 | ||
1574 | return pdev; | |
1575 | ||
1576 | out_free_pdev: | |
1577 | platform_device_put(pdev); | |
1578 | return NULL; | |
1579 | } | |
1580 | ||
9cf6cf58 HCE |
1581 | /* -------------------------------------------------------------------- |
1582 | * SSC | |
1583 | * -------------------------------------------------------------------- */ | |
1584 | static struct resource ssc0_resource[] = { | |
1585 | PBMEM(0xffe01c00), | |
1586 | IRQ(10), | |
1587 | }; | |
1588 | DEFINE_DEV(ssc, 0); | |
1589 | DEV_CLK(pclk, ssc0, pba, 7); | |
1590 | ||
1591 | static struct resource ssc1_resource[] = { | |
1592 | PBMEM(0xffe02000), | |
1593 | IRQ(11), | |
1594 | }; | |
1595 | DEFINE_DEV(ssc, 1); | |
1596 | DEV_CLK(pclk, ssc1, pba, 8); | |
1597 | ||
1598 | static struct resource ssc2_resource[] = { | |
1599 | PBMEM(0xffe02400), | |
1600 | IRQ(12), | |
1601 | }; | |
1602 | DEFINE_DEV(ssc, 2); | |
1603 | DEV_CLK(pclk, ssc2, pba, 9); | |
1604 | ||
1605 | struct platform_device *__init | |
1606 | at32_add_device_ssc(unsigned int id, unsigned int flags) | |
1607 | { | |
1608 | struct platform_device *pdev; | |
caf18f19 | 1609 | u32 pin_mask = 0; |
9cf6cf58 HCE |
1610 | |
1611 | switch (id) { | |
1612 | case 0: | |
1613 | pdev = &ssc0_device; | |
1614 | if (flags & ATMEL_SSC_RF) | |
caf18f19 | 1615 | pin_mask |= (1 << 21); /* RF */ |
9cf6cf58 | 1616 | if (flags & ATMEL_SSC_RK) |
caf18f19 | 1617 | pin_mask |= (1 << 22); /* RK */ |
9cf6cf58 | 1618 | if (flags & ATMEL_SSC_TK) |
caf18f19 | 1619 | pin_mask |= (1 << 23); /* TK */ |
9cf6cf58 | 1620 | if (flags & ATMEL_SSC_TF) |
caf18f19 | 1621 | pin_mask |= (1 << 24); /* TF */ |
9cf6cf58 | 1622 | if (flags & ATMEL_SSC_TD) |
caf18f19 | 1623 | pin_mask |= (1 << 25); /* TD */ |
9cf6cf58 | 1624 | if (flags & ATMEL_SSC_RD) |
caf18f19 JM |
1625 | pin_mask |= (1 << 26); /* RD */ |
1626 | ||
1627 | if (pin_mask > 0) | |
1628 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); | |
1629 | ||
9cf6cf58 HCE |
1630 | break; |
1631 | case 1: | |
1632 | pdev = &ssc1_device; | |
1633 | if (flags & ATMEL_SSC_RF) | |
caf18f19 | 1634 | pin_mask |= (1 << 0); /* RF */ |
9cf6cf58 | 1635 | if (flags & ATMEL_SSC_RK) |
caf18f19 | 1636 | pin_mask |= (1 << 1); /* RK */ |
9cf6cf58 | 1637 | if (flags & ATMEL_SSC_TK) |
caf18f19 | 1638 | pin_mask |= (1 << 2); /* TK */ |
9cf6cf58 | 1639 | if (flags & ATMEL_SSC_TF) |
caf18f19 | 1640 | pin_mask |= (1 << 3); /* TF */ |
9cf6cf58 | 1641 | if (flags & ATMEL_SSC_TD) |
caf18f19 | 1642 | pin_mask |= (1 << 4); /* TD */ |
9cf6cf58 | 1643 | if (flags & ATMEL_SSC_RD) |
caf18f19 JM |
1644 | pin_mask |= (1 << 5); /* RD */ |
1645 | ||
1646 | if (pin_mask > 0) | |
1647 | select_peripheral(PIOA, pin_mask, PERIPH_B, 0); | |
1648 | ||
9cf6cf58 HCE |
1649 | break; |
1650 | case 2: | |
1651 | pdev = &ssc2_device; | |
1652 | if (flags & ATMEL_SSC_TD) | |
caf18f19 | 1653 | pin_mask |= (1 << 13); /* TD */ |
9cf6cf58 | 1654 | if (flags & ATMEL_SSC_RD) |
caf18f19 | 1655 | pin_mask |= (1 << 14); /* RD */ |
9cf6cf58 | 1656 | if (flags & ATMEL_SSC_TK) |
caf18f19 | 1657 | pin_mask |= (1 << 15); /* TK */ |
9cf6cf58 | 1658 | if (flags & ATMEL_SSC_TF) |
caf18f19 | 1659 | pin_mask |= (1 << 16); /* TF */ |
9cf6cf58 | 1660 | if (flags & ATMEL_SSC_RF) |
caf18f19 | 1661 | pin_mask |= (1 << 17); /* RF */ |
9cf6cf58 | 1662 | if (flags & ATMEL_SSC_RK) |
caf18f19 JM |
1663 | pin_mask |= (1 << 18); /* RK */ |
1664 | ||
1665 | if (pin_mask > 0) | |
1666 | select_peripheral(PIOB, pin_mask, PERIPH_A, 0); | |
1667 | ||
9cf6cf58 HCE |
1668 | break; |
1669 | default: | |
1670 | return NULL; | |
1671 | } | |
1672 | ||
1673 | platform_device_register(pdev); | |
1674 | return pdev; | |
1675 | } | |
1676 | ||
6fcf0615 HS |
1677 | /* -------------------------------------------------------------------- |
1678 | * USB Device Controller | |
1679 | * -------------------------------------------------------------------- */ | |
1680 | static struct resource usba0_resource[] __initdata = { | |
1681 | { | |
1682 | .start = 0xff300000, | |
1683 | .end = 0xff3fffff, | |
1684 | .flags = IORESOURCE_MEM, | |
1685 | }, { | |
1686 | .start = 0xfff03000, | |
1687 | .end = 0xfff033ff, | |
1688 | .flags = IORESOURCE_MEM, | |
1689 | }, | |
1690 | IRQ(31), | |
1691 | }; | |
1692 | static struct clk usba0_pclk = { | |
1693 | .name = "pclk", | |
1694 | .parent = &pbb_clk, | |
1695 | .mode = pbb_clk_mode, | |
1696 | .get_rate = pbb_clk_get_rate, | |
1697 | .index = 12, | |
1698 | }; | |
1699 | static struct clk usba0_hclk = { | |
1700 | .name = "hclk", | |
1701 | .parent = &hsb_clk, | |
1702 | .mode = hsb_clk_mode, | |
1703 | .get_rate = hsb_clk_get_rate, | |
1704 | .index = 6, | |
1705 | }; | |
1706 | ||
8d855317 SP |
1707 | #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ |
1708 | [idx] = { \ | |
1709 | .name = nam, \ | |
1710 | .index = idx, \ | |
1711 | .fifo_size = maxpkt, \ | |
1712 | .nr_banks = maxbk, \ | |
1713 | .can_dma = dma, \ | |
1714 | .can_isoc = isoc, \ | |
1715 | } | |
1716 | ||
1717 | static struct usba_ep_data at32_usba_ep[] __initdata = { | |
1718 | EP("ep0", 0, 64, 1, 0, 0), | |
1719 | EP("ep1", 1, 512, 2, 1, 1), | |
1720 | EP("ep2", 2, 512, 2, 1, 1), | |
1721 | EP("ep3-int", 3, 64, 3, 1, 0), | |
1722 | EP("ep4-int", 4, 64, 3, 1, 0), | |
1723 | EP("ep5", 5, 1024, 3, 1, 1), | |
1724 | EP("ep6", 6, 1024, 3, 1, 1), | |
1725 | }; | |
1726 | ||
1727 | #undef EP | |
1728 | ||
6fcf0615 HS |
1729 | struct platform_device *__init |
1730 | at32_add_device_usba(unsigned int id, struct usba_platform_data *data) | |
1731 | { | |
8d855317 SP |
1732 | /* |
1733 | * pdata doesn't have room for any endpoints, so we need to | |
1734 | * append room for the ones we need right after it. | |
1735 | */ | |
1736 | struct { | |
1737 | struct usba_platform_data pdata; | |
1738 | struct usba_ep_data ep[7]; | |
1739 | } usba_data; | |
6fcf0615 HS |
1740 | struct platform_device *pdev; |
1741 | ||
1742 | if (id != 0) | |
1743 | return NULL; | |
1744 | ||
1745 | pdev = platform_device_alloc("atmel_usba_udc", 0); | |
1746 | if (!pdev) | |
1747 | return NULL; | |
1748 | ||
1749 | if (platform_device_add_resources(pdev, usba0_resource, | |
1750 | ARRAY_SIZE(usba0_resource))) | |
1751 | goto out_free_pdev; | |
1752 | ||
8d855317 SP |
1753 | if (data) |
1754 | usba_data.pdata.vbus_pin = data->vbus_pin; | |
1755 | else | |
1756 | usba_data.pdata.vbus_pin = -EINVAL; | |
6fcf0615 | 1757 | |
8d855317 SP |
1758 | data = &usba_data.pdata; |
1759 | data->num_ep = ARRAY_SIZE(at32_usba_ep); | |
1760 | memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep)); | |
1761 | ||
1762 | if (platform_device_add_data(pdev, data, sizeof(usba_data))) | |
1763 | goto out_free_pdev; | |
1764 | ||
1765 | if (data->vbus_pin >= 0) | |
1766 | at32_select_gpio(data->vbus_pin, 0); | |
6fcf0615 HS |
1767 | |
1768 | usba0_pclk.dev = &pdev->dev; | |
1769 | usba0_hclk.dev = &pdev->dev; | |
1770 | ||
1771 | platform_device_add(pdev); | |
1772 | ||
1773 | return pdev; | |
1774 | ||
1775 | out_free_pdev: | |
1776 | platform_device_put(pdev); | |
1777 | return NULL; | |
1778 | } | |
1779 | ||
48021bd9 | 1780 | /* -------------------------------------------------------------------- |
eaf5f925 | 1781 | * IDE / CompactFlash |
48021bd9 | 1782 | * -------------------------------------------------------------------- */ |
438ff3f3 | 1783 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001) |
eaf5f925 | 1784 | static struct resource at32_smc_cs4_resource[] __initdata = { |
48021bd9 KNG |
1785 | { |
1786 | .start = 0x04000000, | |
1787 | .end = 0x07ffffff, | |
1788 | .flags = IORESOURCE_MEM, | |
1789 | }, | |
1790 | IRQ(~0UL), /* Magic IRQ will be overridden */ | |
1791 | }; | |
eaf5f925 HS |
1792 | static struct resource at32_smc_cs5_resource[] __initdata = { |
1793 | { | |
1794 | .start = 0x20000000, | |
1795 | .end = 0x23ffffff, | |
1796 | .flags = IORESOURCE_MEM, | |
1797 | }, | |
1798 | IRQ(~0UL), /* Magic IRQ will be overridden */ | |
1799 | }; | |
48021bd9 | 1800 | |
eaf5f925 HS |
1801 | static int __init at32_init_ide_or_cf(struct platform_device *pdev, |
1802 | unsigned int cs, unsigned int extint) | |
48021bd9 | 1803 | { |
eaf5f925 | 1804 | static unsigned int extint_pin_map[4] __initdata = { |
caf18f19 JM |
1805 | (1 << 25), |
1806 | (1 << 26), | |
1807 | (1 << 27), | |
1808 | (1 << 28), | |
eaf5f925 HS |
1809 | }; |
1810 | static bool common_pins_initialized __initdata = false; | |
48021bd9 | 1811 | unsigned int extint_pin; |
eaf5f925 | 1812 | int ret; |
caf18f19 | 1813 | u32 pin_mask; |
48021bd9 | 1814 | |
eaf5f925 HS |
1815 | if (extint >= ARRAY_SIZE(extint_pin_map)) |
1816 | return -EINVAL; | |
1817 | extint_pin = extint_pin_map[extint]; | |
1818 | ||
1819 | switch (cs) { | |
1820 | case 4: | |
1821 | ret = platform_device_add_resources(pdev, | |
1822 | at32_smc_cs4_resource, | |
1823 | ARRAY_SIZE(at32_smc_cs4_resource)); | |
1824 | if (ret) | |
1825 | return ret; | |
1826 | ||
caf18f19 JM |
1827 | /* NCS4 -> OE_N */ |
1828 | select_peripheral(PIOE, (1 << 21), PERIPH_A, 0); | |
b47eb409 | 1829 | hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE); |
48021bd9 | 1830 | break; |
eaf5f925 HS |
1831 | case 5: |
1832 | ret = platform_device_add_resources(pdev, | |
1833 | at32_smc_cs5_resource, | |
1834 | ARRAY_SIZE(at32_smc_cs5_resource)); | |
1835 | if (ret) | |
1836 | return ret; | |
1837 | ||
caf18f19 JM |
1838 | /* NCS5 -> OE_N */ |
1839 | select_peripheral(PIOE, (1 << 22), PERIPH_A, 0); | |
b47eb409 | 1840 | hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE); |
48021bd9 KNG |
1841 | break; |
1842 | default: | |
eaf5f925 | 1843 | return -EINVAL; |
48021bd9 KNG |
1844 | } |
1845 | ||
eaf5f925 | 1846 | if (!common_pins_initialized) { |
caf18f19 JM |
1847 | pin_mask = (1 << 19); /* CFCE1 -> CS0_N */ |
1848 | pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */ | |
1849 | pin_mask |= (1 << 23); /* CFRNW -> DIR */ | |
1850 | pin_mask |= (1 << 24); /* NWAIT <- IORDY */ | |
1851 | ||
1852 | select_peripheral(PIOE, pin_mask, PERIPH_A, 0); | |
1853 | ||
eaf5f925 | 1854 | common_pins_initialized = true; |
48021bd9 KNG |
1855 | } |
1856 | ||
caf18f19 | 1857 | select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH); |
48021bd9 KNG |
1858 | |
1859 | pdev->resource[1].start = EIM_IRQ_BASE + extint; | |
1860 | pdev->resource[1].end = pdev->resource[1].start; | |
1861 | ||
eaf5f925 HS |
1862 | return 0; |
1863 | } | |
48021bd9 | 1864 | |
eaf5f925 HS |
1865 | struct platform_device *__init |
1866 | at32_add_device_ide(unsigned int id, unsigned int extint, | |
1867 | struct ide_platform_data *data) | |
1868 | { | |
1869 | struct platform_device *pdev; | |
1870 | ||
1871 | pdev = platform_device_alloc("at32_ide", id); | |
1872 | if (!pdev) | |
1873 | goto fail; | |
1874 | ||
1875 | if (platform_device_add_data(pdev, data, | |
1876 | sizeof(struct ide_platform_data))) | |
1877 | goto fail; | |
1878 | ||
1879 | if (at32_init_ide_or_cf(pdev, data->cs, extint)) | |
1880 | goto fail; | |
1881 | ||
1882 | platform_device_add(pdev); | |
1883 | return pdev; | |
1884 | ||
1885 | fail: | |
1886 | platform_device_put(pdev); | |
1887 | return NULL; | |
1888 | } | |
1889 | ||
1890 | struct platform_device *__init | |
1891 | at32_add_device_cf(unsigned int id, unsigned int extint, | |
1892 | struct cf_platform_data *data) | |
1893 | { | |
1894 | struct platform_device *pdev; | |
1895 | ||
1896 | pdev = platform_device_alloc("at32_cf", id); | |
1897 | if (!pdev) | |
1898 | goto fail; | |
48021bd9 | 1899 | |
eaf5f925 HS |
1900 | if (platform_device_add_data(pdev, data, |
1901 | sizeof(struct cf_platform_data))) | |
1902 | goto fail; | |
1903 | ||
1904 | if (at32_init_ide_or_cf(pdev, data->cs, extint)) | |
1905 | goto fail; | |
1906 | ||
3c26e170 | 1907 | if (gpio_is_valid(data->detect_pin)) |
eaf5f925 | 1908 | at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH); |
3c26e170 | 1909 | if (gpio_is_valid(data->reset_pin)) |
eaf5f925 | 1910 | at32_select_gpio(data->reset_pin, 0); |
3c26e170 | 1911 | if (gpio_is_valid(data->vcc_pin)) |
eaf5f925 HS |
1912 | at32_select_gpio(data->vcc_pin, 0); |
1913 | /* READY is used as extint, so we can't select it as gpio */ | |
1914 | ||
1915 | platform_device_add(pdev); | |
48021bd9 | 1916 | return pdev; |
eaf5f925 HS |
1917 | |
1918 | fail: | |
1919 | platform_device_put(pdev); | |
1920 | return NULL; | |
48021bd9 | 1921 | } |
438ff3f3 | 1922 | #endif |
48021bd9 | 1923 | |
62090a08 HS |
1924 | /* -------------------------------------------------------------------- |
1925 | * NAND Flash / SmartMedia | |
1926 | * -------------------------------------------------------------------- */ | |
1927 | static struct resource smc_cs3_resource[] __initdata = { | |
1928 | { | |
1929 | .start = 0x0c000000, | |
1930 | .end = 0x0fffffff, | |
1931 | .flags = IORESOURCE_MEM, | |
1932 | }, { | |
1933 | .start = 0xfff03c00, | |
1934 | .end = 0xfff03fff, | |
1935 | .flags = IORESOURCE_MEM, | |
1936 | }, | |
1937 | }; | |
1938 | ||
1939 | struct platform_device *__init | |
1940 | at32_add_device_nand(unsigned int id, struct atmel_nand_data *data) | |
1941 | { | |
1942 | struct platform_device *pdev; | |
1943 | ||
1944 | if (id != 0 || !data) | |
1945 | return NULL; | |
1946 | ||
1947 | pdev = platform_device_alloc("atmel_nand", id); | |
1948 | if (!pdev) | |
1949 | goto fail; | |
1950 | ||
1951 | if (platform_device_add_resources(pdev, smc_cs3_resource, | |
1952 | ARRAY_SIZE(smc_cs3_resource))) | |
1953 | goto fail; | |
1954 | ||
1955 | if (platform_device_add_data(pdev, data, | |
1956 | sizeof(struct atmel_nand_data))) | |
1957 | goto fail; | |
1958 | ||
b47eb409 | 1959 | hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE); |
62090a08 HS |
1960 | if (data->enable_pin) |
1961 | at32_select_gpio(data->enable_pin, | |
1962 | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH); | |
1963 | if (data->rdy_pin) | |
1964 | at32_select_gpio(data->rdy_pin, 0); | |
1965 | if (data->det_pin) | |
1966 | at32_select_gpio(data->det_pin, 0); | |
1967 | ||
1968 | platform_device_add(pdev); | |
1969 | return pdev; | |
1970 | ||
1971 | fail: | |
1972 | platform_device_put(pdev); | |
1973 | return NULL; | |
1974 | } | |
1975 | ||
2042c1c4 HS |
1976 | /* -------------------------------------------------------------------- |
1977 | * AC97C | |
1978 | * -------------------------------------------------------------------- */ | |
1979 | static struct resource atmel_ac97c0_resource[] __initdata = { | |
1980 | PBMEM(0xfff02800), | |
1981 | IRQ(29), | |
1982 | }; | |
1983 | static struct clk atmel_ac97c0_pclk = { | |
1984 | .name = "pclk", | |
1985 | .parent = &pbb_clk, | |
1986 | .mode = pbb_clk_mode, | |
1987 | .get_rate = pbb_clk_get_rate, | |
1988 | .index = 10, | |
1989 | }; | |
1990 | ||
218df4a2 HCE |
1991 | struct platform_device *__init |
1992 | at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data) | |
2042c1c4 HS |
1993 | { |
1994 | struct platform_device *pdev; | |
218df4a2 | 1995 | struct ac97c_platform_data _data; |
caf18f19 | 1996 | u32 pin_mask; |
2042c1c4 HS |
1997 | |
1998 | if (id != 0) | |
1999 | return NULL; | |
2000 | ||
2001 | pdev = platform_device_alloc("atmel_ac97c", id); | |
2002 | if (!pdev) | |
2003 | return NULL; | |
2004 | ||
2005 | if (platform_device_add_resources(pdev, atmel_ac97c0_resource, | |
2006 | ARRAY_SIZE(atmel_ac97c0_resource))) | |
218df4a2 HCE |
2007 | goto fail; |
2008 | ||
2009 | if (!data) { | |
2010 | data = &_data; | |
2011 | memset(data, 0, sizeof(struct ac97c_platform_data)); | |
2012 | data->reset_pin = GPIO_PIN_NONE; | |
2013 | } | |
2014 | ||
2015 | data->dma_rx_periph_id = 3; | |
2016 | data->dma_tx_periph_id = 4; | |
2017 | data->dma_controller_id = 0; | |
2042c1c4 | 2018 | |
218df4a2 HCE |
2019 | if (platform_device_add_data(pdev, data, |
2020 | sizeof(struct ac97c_platform_data))) | |
2021 | goto fail; | |
2022 | ||
caf18f19 JM |
2023 | pin_mask = (1 << 20) | (1 << 21); /* SDO & SYNC */ |
2024 | pin_mask |= (1 << 22) | (1 << 23); /* SCLK & SDI */ | |
2025 | ||
2026 | select_peripheral(PIOB, pin_mask, PERIPH_B, 0); | |
218df4a2 HCE |
2027 | |
2028 | /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */ | |
2029 | if (data->reset_pin != GPIO_PIN_NONE) | |
2030 | at32_select_gpio(data->reset_pin, 0); | |
2042c1c4 HS |
2031 | |
2032 | atmel_ac97c0_pclk.dev = &pdev->dev; | |
2033 | ||
2034 | platform_device_add(pdev); | |
2035 | return pdev; | |
2036 | ||
218df4a2 | 2037 | fail: |
2042c1c4 HS |
2038 | platform_device_put(pdev); |
2039 | return NULL; | |
2040 | } | |
2041 | ||
2042 | /* -------------------------------------------------------------------- | |
2043 | * ABDAC | |
2044 | * -------------------------------------------------------------------- */ | |
2045 | static struct resource abdac0_resource[] __initdata = { | |
2046 | PBMEM(0xfff02000), | |
2047 | IRQ(27), | |
2048 | }; | |
2049 | static struct clk abdac0_pclk = { | |
2050 | .name = "pclk", | |
2051 | .parent = &pbb_clk, | |
2052 | .mode = pbb_clk_mode, | |
2053 | .get_rate = pbb_clk_get_rate, | |
2054 | .index = 8, | |
2055 | }; | |
2056 | static struct clk abdac0_sample_clk = { | |
2057 | .name = "sample_clk", | |
2058 | .mode = genclk_mode, | |
2059 | .get_rate = genclk_get_rate, | |
2060 | .set_rate = genclk_set_rate, | |
2061 | .set_parent = genclk_set_parent, | |
2062 | .index = 6, | |
2063 | }; | |
2064 | ||
2065 | struct platform_device *__init at32_add_device_abdac(unsigned int id) | |
2066 | { | |
2067 | struct platform_device *pdev; | |
caf18f19 | 2068 | u32 pin_mask; |
2042c1c4 HS |
2069 | |
2070 | if (id != 0) | |
2071 | return NULL; | |
2072 | ||
2073 | pdev = platform_device_alloc("abdac", id); | |
2074 | if (!pdev) | |
2075 | return NULL; | |
2076 | ||
2077 | if (platform_device_add_resources(pdev, abdac0_resource, | |
2078 | ARRAY_SIZE(abdac0_resource))) | |
2079 | goto err_add_resources; | |
2080 | ||
caf18f19 JM |
2081 | pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */ |
2082 | pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */ | |
2083 | ||
2084 | select_peripheral(PIOB, pin_mask, PERIPH_A, 0); | |
2042c1c4 HS |
2085 | |
2086 | abdac0_pclk.dev = &pdev->dev; | |
2087 | abdac0_sample_clk.dev = &pdev->dev; | |
2088 | ||
2089 | platform_device_add(pdev); | |
2090 | return pdev; | |
2091 | ||
2092 | err_add_resources: | |
2093 | platform_device_put(pdev); | |
2094 | return NULL; | |
2095 | } | |
2096 | ||
7a5fe238 HS |
2097 | /* -------------------------------------------------------------------- |
2098 | * GCLK | |
2099 | * -------------------------------------------------------------------- */ | |
2100 | static struct clk gclk0 = { | |
2101 | .name = "gclk0", | |
2102 | .mode = genclk_mode, | |
2103 | .get_rate = genclk_get_rate, | |
2104 | .set_rate = genclk_set_rate, | |
2105 | .set_parent = genclk_set_parent, | |
2106 | .index = 0, | |
2107 | }; | |
2108 | static struct clk gclk1 = { | |
2109 | .name = "gclk1", | |
2110 | .mode = genclk_mode, | |
2111 | .get_rate = genclk_get_rate, | |
2112 | .set_rate = genclk_set_rate, | |
2113 | .set_parent = genclk_set_parent, | |
2114 | .index = 1, | |
2115 | }; | |
2116 | static struct clk gclk2 = { | |
2117 | .name = "gclk2", | |
2118 | .mode = genclk_mode, | |
2119 | .get_rate = genclk_get_rate, | |
2120 | .set_rate = genclk_set_rate, | |
2121 | .set_parent = genclk_set_parent, | |
2122 | .index = 2, | |
2123 | }; | |
2124 | static struct clk gclk3 = { | |
2125 | .name = "gclk3", | |
2126 | .mode = genclk_mode, | |
2127 | .get_rate = genclk_get_rate, | |
2128 | .set_rate = genclk_set_rate, | |
2129 | .set_parent = genclk_set_parent, | |
2130 | .index = 3, | |
2131 | }; | |
2132 | static struct clk gclk4 = { | |
2133 | .name = "gclk4", | |
2134 | .mode = genclk_mode, | |
2135 | .get_rate = genclk_get_rate, | |
2136 | .set_rate = genclk_set_rate, | |
2137 | .set_parent = genclk_set_parent, | |
2138 | .index = 4, | |
2139 | }; | |
2140 | ||
300bb762 | 2141 | static __initdata struct clk *init_clocks[] = { |
5f97f7f9 HS |
2142 | &osc32k, |
2143 | &osc0, | |
2144 | &osc1, | |
2145 | &pll0, | |
2146 | &pll1, | |
2147 | &cpu_clk, | |
2148 | &hsb_clk, | |
2149 | &pba_clk, | |
2150 | &pbb_clk, | |
7a5b8059 | 2151 | &at32_pm_pclk, |
5f97f7f9 | 2152 | &at32_intc0_pclk, |
b47eb409 | 2153 | &at32_hmatrix_clk, |
5f97f7f9 HS |
2154 | &ebi_clk, |
2155 | &hramc_clk, | |
7951f188 | 2156 | &sdramc_clk, |
bc157b75 HS |
2157 | &smc0_pclk, |
2158 | &smc0_mck, | |
5f97f7f9 HS |
2159 | &pdc_hclk, |
2160 | &pdc_pclk, | |
3bfb1d20 | 2161 | &dw_dmac0_hclk, |
5f97f7f9 HS |
2162 | &pico_clk, |
2163 | &pio0_mck, | |
2164 | &pio1_mck, | |
2165 | &pio2_mck, | |
2166 | &pio3_mck, | |
7f9f4678 | 2167 | &pio4_mck, |
e723ff66 DB |
2168 | &at32_tcb0_t0_clk, |
2169 | &at32_tcb1_t0_clk, | |
d86d314f HCE |
2170 | &atmel_psif0_pclk, |
2171 | &atmel_psif1_pclk, | |
1e8ea802 HS |
2172 | &atmel_usart0_usart, |
2173 | &atmel_usart1_usart, | |
2174 | &atmel_usart2_usart, | |
2175 | &atmel_usart3_usart, | |
9a1e8eb1 | 2176 | &atmel_pwm0_mck, |
438ff3f3 | 2177 | #if defined(CONFIG_CPU_AT32AP7000) |
5f97f7f9 HS |
2178 | &macb0_hclk, |
2179 | &macb0_pclk, | |
cfcb3a89 HS |
2180 | &macb1_hclk, |
2181 | &macb1_pclk, | |
438ff3f3 | 2182 | #endif |
3d60ee1b HS |
2183 | &atmel_spi0_spi_clk, |
2184 | &atmel_spi1_spi_clk, | |
2042c1c4 HS |
2185 | &atmel_twi0_pclk, |
2186 | &atmel_mci0_pclk, | |
438ff3f3 | 2187 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af HS |
2188 | &atmel_lcdfb0_hck1, |
2189 | &atmel_lcdfb0_pixclk, | |
438ff3f3 | 2190 | #endif |
9cf6cf58 HCE |
2191 | &ssc0_pclk, |
2192 | &ssc1_pclk, | |
2193 | &ssc2_pclk, | |
6fcf0615 HS |
2194 | &usba0_hclk, |
2195 | &usba0_pclk, | |
2042c1c4 HS |
2196 | &atmel_ac97c0_pclk, |
2197 | &abdac0_pclk, | |
2198 | &abdac0_sample_clk, | |
7a5fe238 HS |
2199 | &gclk0, |
2200 | &gclk1, | |
2201 | &gclk2, | |
2202 | &gclk3, | |
2203 | &gclk4, | |
5f97f7f9 | 2204 | }; |
5f97f7f9 | 2205 | |
65033ed7 | 2206 | void __init setup_platform(void) |
5f97f7f9 | 2207 | { |
5f97f7f9 HS |
2208 | u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0; |
2209 | int i; | |
2210 | ||
9e58e185 | 2211 | if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) { |
5f97f7f9 | 2212 | main_clock = &pll0; |
9e58e185 HCE |
2213 | cpu_clk.parent = &pll0; |
2214 | } else { | |
5f97f7f9 | 2215 | main_clock = &osc0; |
9e58e185 HCE |
2216 | cpu_clk.parent = &osc0; |
2217 | } | |
5f97f7f9 | 2218 | |
7a5b8059 | 2219 | if (pm_readl(PLL0) & PM_BIT(PLLOSC)) |
5f97f7f9 | 2220 | pll0.parent = &osc1; |
7a5b8059 | 2221 | if (pm_readl(PLL1) & PM_BIT(PLLOSC)) |
5f97f7f9 HS |
2222 | pll1.parent = &osc1; |
2223 | ||
7a5fe238 HS |
2224 | genclk_init_parent(&gclk0); |
2225 | genclk_init_parent(&gclk1); | |
2226 | genclk_init_parent(&gclk2); | |
2227 | genclk_init_parent(&gclk3); | |
2228 | genclk_init_parent(&gclk4); | |
438ff3f3 | 2229 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af | 2230 | genclk_init_parent(&atmel_lcdfb0_pixclk); |
438ff3f3 | 2231 | #endif |
2042c1c4 | 2232 | genclk_init_parent(&abdac0_sample_clk); |
7a5fe238 | 2233 | |
5f97f7f9 | 2234 | /* |
300bb762 AR |
2235 | * Build initial dynamic clock list by registering all clocks |
2236 | * from the array. | |
2237 | * At the same time, turn on all clocks that have at least one | |
2238 | * user already, and turn off everything else. We only do this | |
2239 | * for module clocks, and even though it isn't particularly | |
2240 | * pretty to check the address of the mode function, it should | |
2241 | * do the trick... | |
5f97f7f9 | 2242 | */ |
300bb762 AR |
2243 | for (i = 0; i < ARRAY_SIZE(init_clocks); i++) { |
2244 | struct clk *clk = init_clocks[i]; | |
2245 | ||
2246 | /* first, register clock */ | |
2247 | at32_clk_register(clk); | |
5f97f7f9 | 2248 | |
188ff65d HS |
2249 | if (clk->users == 0) |
2250 | continue; | |
2251 | ||
5f97f7f9 HS |
2252 | if (clk->mode == &cpu_clk_mode) |
2253 | cpu_mask |= 1 << clk->index; | |
2254 | else if (clk->mode == &hsb_clk_mode) | |
2255 | hsb_mask |= 1 << clk->index; | |
2256 | else if (clk->mode == &pba_clk_mode) | |
2257 | pba_mask |= 1 << clk->index; | |
2258 | else if (clk->mode == &pbb_clk_mode) | |
2259 | pbb_mask |= 1 << clk->index; | |
2260 | } | |
2261 | ||
7a5b8059 HS |
2262 | pm_writel(CPU_MASK, cpu_mask); |
2263 | pm_writel(HSB_MASK, hsb_mask); | |
2264 | pm_writel(PBA_MASK, pba_mask); | |
2265 | pm_writel(PBB_MASK, pbb_mask); | |
65033ed7 HS |
2266 | |
2267 | /* Initialize the port muxes */ | |
2268 | at32_init_pio(&pio0_device); | |
2269 | at32_init_pio(&pio1_device); | |
2270 | at32_init_pio(&pio2_device); | |
2271 | at32_init_pio(&pio3_device); | |
2272 | at32_init_pio(&pio4_device); | |
5f97f7f9 | 2273 | } |
b83d6ee1 HS |
2274 | |
2275 | struct gen_pool *sram_pool; | |
2276 | ||
2277 | static int __init sram_init(void) | |
2278 | { | |
2279 | struct gen_pool *pool; | |
2280 | ||
2281 | /* 1KiB granularity */ | |
2282 | pool = gen_pool_create(10, -1); | |
2283 | if (!pool) | |
2284 | goto fail; | |
2285 | ||
2286 | if (gen_pool_add(pool, 0x24000000, 0x8000, -1)) | |
2287 | goto err_pool_add; | |
2288 | ||
2289 | sram_pool = pool; | |
2290 | return 0; | |
2291 | ||
2292 | err_pool_add: | |
2293 | gen_pool_destroy(pool); | |
2294 | fail: | |
2295 | pr_err("Failed to create SRAM pool\n"); | |
2296 | return -ENOMEM; | |
2297 | } | |
2298 | core_initcall(sram_init); |