Commit | Line | Data |
---|---|---|
9e1b9b80 AJ |
1 | config SYMBOL_PREFIX |
2 | string | |
3 | default "_" | |
4 | ||
1394f032 | 5 | config MMU |
bac7d89e | 6 | def_bool n |
1394f032 BW |
7 | |
8 | config FPU | |
bac7d89e | 9 | def_bool n |
1394f032 BW |
10 | |
11 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 12 | def_bool y |
1394f032 BW |
13 | |
14 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 15 | def_bool n |
1394f032 BW |
16 | |
17 | config BLACKFIN | |
bac7d89e | 18 | def_bool y |
652afdc3 | 19 | select HAVE_ARCH_KGDB |
e8f263df | 20 | select HAVE_ARCH_TRACEHOOK |
f5074429 MF |
21 | select HAVE_DYNAMIC_FTRACE |
22 | select HAVE_FTRACE_MCOUNT_RECORD | |
1ee76d7e | 23 | select HAVE_FUNCTION_GRAPH_TRACER |
1c873be7 | 24 | select HAVE_FUNCTION_TRACER |
aebfef03 | 25 | select HAVE_FUNCTION_TRACE_MCOUNT_TEST |
ec7748b5 | 26 | select HAVE_IDE |
7db79172 | 27 | select HAVE_IRQ_WORK |
d86bfb16 BS |
28 | select HAVE_KERNEL_GZIP if RAMKERNEL |
29 | select HAVE_KERNEL_BZIP2 if RAMKERNEL | |
30 | select HAVE_KERNEL_LZMA if RAMKERNEL | |
67df6cc6 | 31 | select HAVE_KERNEL_LZO if RAMKERNEL |
42d4b839 | 32 | select HAVE_OPROFILE |
7db79172 | 33 | select HAVE_PERF_EVENTS |
7563bbf8 | 34 | select ARCH_HAVE_CUSTOM_GPIO_H |
a4f0b32c | 35 | select ARCH_WANT_OPTIONAL_GPIOLIB |
c1d7e01d | 36 | select ARCH_WANT_IPC_PARSE_VERSION |
7b028863 | 37 | select HAVE_GENERIC_HARDIRQS |
bee18beb | 38 | select GENERIC_ATOMIC64 |
7b028863 TG |
39 | select GENERIC_IRQ_PROBE |
40 | select IRQ_PER_CPU if SMP | |
d314d74c | 41 | select HAVE_NMI_WATCHDOG if NMI_WATCHDOG |
6bba2682 | 42 | select GENERIC_SMP_IDLE_THREAD |
dfbaec06 | 43 | select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS |
1394f032 | 44 | |
ddf9ddac MF |
45 | config GENERIC_CSUM |
46 | def_bool y | |
47 | ||
70f12567 MF |
48 | config GENERIC_BUG |
49 | def_bool y | |
50 | depends on BUG | |
51 | ||
e3defffe | 52 | config ZONE_DMA |
bac7d89e | 53 | def_bool y |
e3defffe | 54 | |
b2d1583f | 55 | config GENERIC_GPIO |
bac7d89e | 56 | def_bool y |
1394f032 BW |
57 | |
58 | config FORCE_MAX_ZONEORDER | |
59 | int | |
60 | default "14" | |
61 | ||
62 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 63 | def_bool y |
1394f032 | 64 | |
6fa68e7a MF |
65 | config LOCKDEP_SUPPORT |
66 | def_bool y | |
67 | ||
c7b412f4 MF |
68 | config STACKTRACE_SUPPORT |
69 | def_bool y | |
70 | ||
8f86001f MF |
71 | config TRACE_IRQFLAGS_SUPPORT |
72 | def_bool y | |
1394f032 | 73 | |
1394f032 | 74 | source "init/Kconfig" |
dc52ddc0 | 75 | |
1394f032 BW |
76 | source "kernel/Kconfig.preempt" |
77 | ||
dc52ddc0 MH |
78 | source "kernel/Kconfig.freezer" |
79 | ||
1394f032 BW |
80 | menu "Blackfin Processor Options" |
81 | ||
82 | comment "Processor and Board Settings" | |
83 | ||
84 | choice | |
85 | prompt "CPU" | |
86 | default BF533 | |
87 | ||
2f6f4bcd BW |
88 | config BF512 |
89 | bool "BF512" | |
90 | help | |
91 | BF512 Processor Support. | |
92 | ||
93 | config BF514 | |
94 | bool "BF514" | |
95 | help | |
96 | BF514 Processor Support. | |
97 | ||
98 | config BF516 | |
99 | bool "BF516" | |
100 | help | |
101 | BF516 Processor Support. | |
102 | ||
103 | config BF518 | |
104 | bool "BF518" | |
105 | help | |
106 | BF518 Processor Support. | |
107 | ||
59003145 MH |
108 | config BF522 |
109 | bool "BF522" | |
110 | help | |
111 | BF522 Processor Support. | |
112 | ||
1545a111 MF |
113 | config BF523 |
114 | bool "BF523" | |
115 | help | |
116 | BF523 Processor Support. | |
117 | ||
118 | config BF524 | |
119 | bool "BF524" | |
120 | help | |
121 | BF524 Processor Support. | |
122 | ||
59003145 MH |
123 | config BF525 |
124 | bool "BF525" | |
125 | help | |
126 | BF525 Processor Support. | |
127 | ||
1545a111 MF |
128 | config BF526 |
129 | bool "BF526" | |
130 | help | |
131 | BF526 Processor Support. | |
132 | ||
59003145 MH |
133 | config BF527 |
134 | bool "BF527" | |
135 | help | |
136 | BF527 Processor Support. | |
137 | ||
1394f032 BW |
138 | config BF531 |
139 | bool "BF531" | |
140 | help | |
141 | BF531 Processor Support. | |
142 | ||
143 | config BF532 | |
144 | bool "BF532" | |
145 | help | |
146 | BF532 Processor Support. | |
147 | ||
148 | config BF533 | |
149 | bool "BF533" | |
150 | help | |
151 | BF533 Processor Support. | |
152 | ||
153 | config BF534 | |
154 | bool "BF534" | |
155 | help | |
156 | BF534 Processor Support. | |
157 | ||
158 | config BF536 | |
159 | bool "BF536" | |
160 | help | |
161 | BF536 Processor Support. | |
162 | ||
163 | config BF537 | |
164 | bool "BF537" | |
165 | help | |
166 | BF537 Processor Support. | |
167 | ||
dc26aec2 MH |
168 | config BF538 |
169 | bool "BF538" | |
170 | help | |
171 | BF538 Processor Support. | |
172 | ||
173 | config BF539 | |
174 | bool "BF539" | |
175 | help | |
176 | BF539 Processor Support. | |
177 | ||
5df326ac | 178 | config BF542_std |
24a07a12 RH |
179 | bool "BF542" |
180 | help | |
181 | BF542 Processor Support. | |
182 | ||
2f89c063 MF |
183 | config BF542M |
184 | bool "BF542m" | |
185 | help | |
186 | BF542 Processor Support. | |
187 | ||
5df326ac | 188 | config BF544_std |
24a07a12 RH |
189 | bool "BF544" |
190 | help | |
191 | BF544 Processor Support. | |
192 | ||
2f89c063 MF |
193 | config BF544M |
194 | bool "BF544m" | |
195 | help | |
196 | BF544 Processor Support. | |
197 | ||
5df326ac | 198 | config BF547_std |
7c7fd170 MF |
199 | bool "BF547" |
200 | help | |
201 | BF547 Processor Support. | |
202 | ||
2f89c063 MF |
203 | config BF547M |
204 | bool "BF547m" | |
205 | help | |
206 | BF547 Processor Support. | |
207 | ||
5df326ac | 208 | config BF548_std |
24a07a12 RH |
209 | bool "BF548" |
210 | help | |
211 | BF548 Processor Support. | |
212 | ||
2f89c063 MF |
213 | config BF548M |
214 | bool "BF548m" | |
215 | help | |
216 | BF548 Processor Support. | |
217 | ||
5df326ac | 218 | config BF549_std |
24a07a12 RH |
219 | bool "BF549" |
220 | help | |
221 | BF549 Processor Support. | |
222 | ||
2f89c063 MF |
223 | config BF549M |
224 | bool "BF549m" | |
225 | help | |
226 | BF549 Processor Support. | |
227 | ||
1394f032 BW |
228 | config BF561 |
229 | bool "BF561" | |
230 | help | |
cd88b4dc | 231 | BF561 Processor Support. |
1394f032 | 232 | |
b5affb01 BL |
233 | config BF609 |
234 | bool "BF609" | |
235 | select CLKDEV_LOOKUP | |
236 | help | |
237 | BF609 Processor Support. | |
238 | ||
1394f032 BW |
239 | endchoice |
240 | ||
46fa5eec GY |
241 | config SMP |
242 | depends on BF561 | |
0d152c27 | 243 | select TICKSOURCE_CORETMR |
46fa5eec GY |
244 | bool "Symmetric multi-processing support" |
245 | ---help--- | |
246 | This enables support for systems with more than one CPU, | |
247 | like the dual core BF561. If you have a system with only one | |
248 | CPU, say N. If you have a system with more than one CPU, say Y. | |
249 | ||
250 | If you don't know what to do here, say N. | |
251 | ||
252 | config NR_CPUS | |
253 | int | |
254 | depends on SMP | |
255 | default 2 if BF561 | |
256 | ||
0b39db28 GY |
257 | config HOTPLUG_CPU |
258 | bool "Support for hot-pluggable CPUs" | |
259 | depends on SMP && HOTPLUG | |
260 | default y | |
261 | ||
0c0497c2 MF |
262 | config BF_REV_MIN |
263 | int | |
b5affb01 | 264 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x |
0c0497c2 | 265 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 266 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 267 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
268 | |
269 | config BF_REV_MAX | |
270 | int | |
b5affb01 | 271 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x |
2f89c063 | 272 | default 3 if (BF537 || BF536 || BF534 || BF54xM) |
2f6f4bcd | 273 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
274 | default 6 if (BF533 || BF532 || BF531) |
275 | ||
1394f032 BW |
276 | choice |
277 | prompt "Silicon Rev" | |
b5affb01 | 278 | default BF_REV_0_0 if (BF51x || BF52x || BF60x) |
f8b55651 | 279 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) |
2f89c063 | 280 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
281 | |
282 | config BF_REV_0_0 | |
283 | bool "0.0" | |
b5affb01 | 284 | depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) |
59003145 MH |
285 | |
286 | config BF_REV_0_1 | |
d07f4380 | 287 | bool "0.1" |
3d15f302 | 288 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
289 | |
290 | config BF_REV_0_2 | |
291 | bool "0.2" | |
8060bb6f | 292 | depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
293 | |
294 | config BF_REV_0_3 | |
295 | bool "0.3" | |
2f89c063 | 296 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
297 | |
298 | config BF_REV_0_4 | |
299 | bool "0.4" | |
dc26aec2 | 300 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
301 | |
302 | config BF_REV_0_5 | |
303 | bool "0.5" | |
dc26aec2 | 304 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 305 | |
49f7253c MF |
306 | config BF_REV_0_6 |
307 | bool "0.6" | |
308 | depends on (BF533 || BF532 || BF531) | |
309 | ||
de3025f4 JZ |
310 | config BF_REV_ANY |
311 | bool "any" | |
312 | ||
313 | config BF_REV_NONE | |
314 | bool "none" | |
315 | ||
1394f032 BW |
316 | endchoice |
317 | ||
24a07a12 RH |
318 | config BF53x |
319 | bool | |
320 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
321 | default y | |
322 | ||
1394f032 BW |
323 | config MEM_MT48LC64M4A2FB_7E |
324 | bool | |
325 | depends on (BFIN533_STAMP) | |
326 | default y | |
327 | ||
328 | config MEM_MT48LC16M16A2TG_75 | |
329 | bool | |
330 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
60584344 HK |
331 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
332 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ | |
333 | || BFIN527_BLUETECHNIX_CM) | |
1394f032 BW |
334 | default y |
335 | ||
336 | config MEM_MT48LC32M8A2_75 | |
337 | bool | |
084f9ebf | 338 | depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
339 | default y |
340 | ||
341 | config MEM_MT48LC8M32B2B5_7 | |
342 | bool | |
343 | depends on (BFIN561_BLUETECHNIX_CM) | |
344 | default y | |
345 | ||
59003145 MH |
346 | config MEM_MT48LC32M16A2TG_75 |
347 | bool | |
8effc4a6 | 348 | depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) |
59003145 MH |
349 | default y |
350 | ||
ee48efb5 GY |
351 | config MEM_MT48H32M16LFCJ_75 |
352 | bool | |
353 | depends on (BFIN526_EZBRD) | |
354 | default y | |
355 | ||
f82f16d2 BL |
356 | config MEM_MT47H64M16 |
357 | bool | |
358 | depends on (BFIN609_EZKIT) | |
359 | default y | |
360 | ||
2f6f4bcd | 361 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 362 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
363 | source "arch/blackfin/mach-bf533/Kconfig" |
364 | source "arch/blackfin/mach-bf561/Kconfig" | |
365 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 366 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 367 | source "arch/blackfin/mach-bf548/Kconfig" |
b5affb01 | 368 | source "arch/blackfin/mach-bf609/Kconfig" |
1394f032 BW |
369 | |
370 | menu "Board customizations" | |
371 | ||
372 | config CMDLINE_BOOL | |
373 | bool "Default bootloader kernel arguments" | |
374 | ||
375 | config CMDLINE | |
376 | string "Initial kernel command string" | |
377 | depends on CMDLINE_BOOL | |
378 | default "console=ttyBF0,57600" | |
379 | help | |
380 | If you don't have a boot loader capable of passing a command line string | |
381 | to the kernel, you may specify one here. As a minimum, you should specify | |
382 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
383 | ||
5f004c20 MF |
384 | config BOOT_LOAD |
385 | hex "Kernel load address for booting" | |
386 | default "0x1000" | |
387 | range 0x1000 0x20000000 | |
388 | help | |
389 | This option allows you to set the load address of the kernel. | |
390 | This can be useful if you are on a board which has a small amount | |
391 | of memory or you wish to reserve some memory at the beginning of | |
392 | the address space. | |
393 | ||
394 | Note that you need to keep this value above 4k (0x1000) as this | |
395 | memory region is used to capture NULL pointer references as well | |
396 | as some core kernel functions. | |
397 | ||
b5affb01 BL |
398 | config PHY_RAM_BASE_ADDRESS |
399 | hex "Physical RAM Base" | |
400 | default 0x0 | |
401 | help | |
402 | set BF609 FPGA physical SRAM base address | |
403 | ||
8cc7117e MH |
404 | config ROM_BASE |
405 | hex "Kernel ROM Base" | |
86249911 | 406 | depends on ROMKERNEL |
d86bfb16 | 407 | default "0x20040040" |
3003668c | 408 | range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x) |
8cc7117e | 409 | range 0x20000000 0x30000000 if (BF54x || BF561) |
3003668c | 410 | range 0xB0000000 0xC0000000 if (BF60x) |
8cc7117e | 411 | help |
d86bfb16 BS |
412 | Make sure your ROM base does not include any file-header |
413 | information that is prepended to the kernel. | |
414 | ||
415 | For example, the bootable U-Boot format (created with | |
416 | mkimage) has a 64 byte header (0x40). So while the image | |
417 | you write to flash might start at say 0x20080000, you have | |
418 | to add 0x40 to get the kernel's ROM base as it will come | |
419 | after the header. | |
8cc7117e | 420 | |
f16295e7 | 421 | comment "Clock/PLL Setup" |
1394f032 BW |
422 | |
423 | config CLKIN_HZ | |
2fb6cb41 | 424 | int "Frequency of the crystal on the board in Hz" |
d0cb9b4e | 425 | default "10000000" if BFIN532_IP0X |
1394f032 | 426 | default "11059200" if BFIN533_STAMP |
d0cb9b4e MF |
427 | default "24576000" if PNAV10 |
428 | default "25000000" # most people use this | |
1394f032 | 429 | default "27000000" if BFIN533_EZKIT |
1394f032 | 430 | default "30000000" if BFIN561_EZKIT |
8effc4a6 | 431 | default "24000000" if BFIN527_AD7160EVAL |
1394f032 BW |
432 | help |
433 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
434 | Warning: This value should match the crystal on the board. Otherwise, |
435 | peripherals won't work properly. | |
1394f032 | 436 | |
f16295e7 RG |
437 | config BFIN_KERNEL_CLOCK |
438 | bool "Re-program Clocks while Kernel boots?" | |
439 | default n | |
440 | help | |
441 | This option decides if kernel clocks are re-programed from the | |
442 | bootloader settings. If the clocks are not set, the SDRAM settings | |
443 | are also not changed, and the Bootloader does 100% of the hardware | |
444 | configuration. | |
445 | ||
446 | config PLL_BYPASS | |
e4e9a7ad | 447 | bool "Bypass PLL" |
7c141c1c | 448 | depends on BFIN_KERNEL_CLOCK && (!BF60x) |
e4e9a7ad | 449 | default n |
f16295e7 RG |
450 | |
451 | config CLKIN_HALF | |
452 | bool "Half Clock In" | |
453 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
454 | default n | |
455 | help | |
456 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
457 | ||
458 | config VCO_MULT | |
459 | int "VCO Multiplier" | |
460 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
461 | range 1 64 | |
462 | default "22" if BFIN533_EZKIT | |
463 | default "45" if BFIN533_STAMP | |
6924dfb0 | 464 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 465 | default "22" if BFIN533_BLUETECHNIX_CM |
60584344 | 466 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
7c141c1c | 467 | default "20" if (BFIN561_EZKIT || BF609) |
2f6f4bcd | 468 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
8effc4a6 | 469 | default "25" if BFIN527_AD7160EVAL |
f16295e7 RG |
470 | help |
471 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
472 | PLL Frequency = (Crystal Frequency) * (this setting) | |
473 | ||
474 | choice | |
475 | prompt "Core Clock Divider" | |
476 | depends on BFIN_KERNEL_CLOCK | |
477 | default CCLK_DIV_1 | |
478 | help | |
479 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
480 | Core Frequency = (PLL frequency) / (this setting) | |
481 | ||
482 | config CCLK_DIV_1 | |
483 | bool "1" | |
484 | ||
485 | config CCLK_DIV_2 | |
486 | bool "2" | |
487 | ||
488 | config CCLK_DIV_4 | |
489 | bool "4" | |
490 | ||
491 | config CCLK_DIV_8 | |
492 | bool "8" | |
493 | endchoice | |
494 | ||
495 | config SCLK_DIV | |
496 | int "System Clock Divider" | |
497 | depends on BFIN_KERNEL_CLOCK | |
498 | range 1 15 | |
7c141c1c | 499 | default 4 |
f16295e7 | 500 | help |
7c141c1c BL |
501 | This sets the frequency of the system clock (including SDRAM or DDR) on |
502 | !BF60x else it set the clock for system buses and provides the | |
503 | source from which SCLK0 and SCLK1 are derived. | |
f16295e7 RG |
504 | This can be between 1 and 15 |
505 | System Clock = (PLL frequency) / (this setting) | |
506 | ||
7c141c1c BL |
507 | config SCLK0_DIV |
508 | int "System Clock0 Divider" | |
509 | depends on BFIN_KERNEL_CLOCK && BF60x | |
510 | range 1 15 | |
511 | default 1 | |
512 | help | |
513 | This sets the frequency of the system clock0 for PVP and all other | |
514 | peripherals not clocked by SCLK1. | |
515 | This can be between 1 and 15 | |
516 | System Clock0 = (System Clock) / (this setting) | |
517 | ||
518 | config SCLK1_DIV | |
519 | int "System Clock1 Divider" | |
520 | depends on BFIN_KERNEL_CLOCK && BF60x | |
521 | range 1 15 | |
522 | default 1 | |
523 | help | |
524 | This sets the frequency of the system clock1 (including SPORT, SPI and ACM). | |
525 | This can be between 1 and 15 | |
526 | System Clock1 = (System Clock) / (this setting) | |
527 | ||
528 | config DCLK_DIV | |
529 | int "DDR Clock Divider" | |
530 | depends on BFIN_KERNEL_CLOCK && BF60x | |
531 | range 1 15 | |
532 | default 2 | |
533 | help | |
534 | This sets the frequency of the DDR memory. | |
535 | This can be between 1 and 15 | |
536 | DDR Clock = (PLL frequency) / (this setting) | |
537 | ||
5f004c20 MF |
538 | choice |
539 | prompt "DDR SDRAM Chip Type" | |
540 | depends on BFIN_KERNEL_CLOCK | |
541 | depends on BF54x | |
542 | default MEM_MT46V32M16_5B | |
543 | ||
544 | config MEM_MT46V32M16_6T | |
545 | bool "MT46V32M16_6T" | |
546 | ||
547 | config MEM_MT46V32M16_5B | |
548 | bool "MT46V32M16_5B" | |
549 | endchoice | |
550 | ||
73feb5c0 MH |
551 | choice |
552 | prompt "DDR/SDRAM Timing" | |
7c141c1c | 553 | depends on BFIN_KERNEL_CLOCK && !BF60x |
73feb5c0 MH |
554 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC |
555 | help | |
556 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
557 | The calculated SDRAM timing parameters may not be 100% | |
558 | accurate - This option is therefore marked experimental. | |
559 | ||
560 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
561 | bool "Calculate Timings (EXPERIMENTAL)" | |
562 | depends on EXPERIMENTAL | |
563 | ||
564 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
565 | bool "Provide accurate Timings based on target SCLK" | |
566 | help | |
567 | Please consult the Blackfin Hardware Reference Manuals as well | |
568 | as the memory device datasheet. | |
569 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
570 | endchoice | |
571 | ||
572 | menu "Memory Init Control" | |
573 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
574 | ||
575 | config MEM_DDRCTL0 | |
576 | depends on BF54x | |
577 | hex "DDRCTL0" | |
578 | default 0x0 | |
579 | ||
580 | config MEM_DDRCTL1 | |
581 | depends on BF54x | |
582 | hex "DDRCTL1" | |
583 | default 0x0 | |
584 | ||
585 | config MEM_DDRCTL2 | |
586 | depends on BF54x | |
587 | hex "DDRCTL2" | |
588 | default 0x0 | |
589 | ||
590 | config MEM_EBIU_DDRQUE | |
591 | depends on BF54x | |
592 | hex "DDRQUE" | |
593 | default 0x0 | |
594 | ||
595 | config MEM_SDRRC | |
596 | depends on !BF54x | |
597 | hex "SDRRC" | |
598 | default 0x0 | |
599 | ||
600 | config MEM_SDGCTL | |
601 | depends on !BF54x | |
602 | hex "SDGCTL" | |
603 | default 0x0 | |
604 | endmenu | |
605 | ||
f16295e7 RG |
606 | # |
607 | # Max & Min Speeds for various Chips | |
608 | # | |
609 | config MAX_VCO_HZ | |
610 | int | |
2f6f4bcd BW |
611 | default 400000000 if BF512 |
612 | default 400000000 if BF514 | |
613 | default 400000000 if BF516 | |
614 | default 400000000 if BF518 | |
7b06263b MF |
615 | default 400000000 if BF522 |
616 | default 600000000 if BF523 | |
1545a111 | 617 | default 400000000 if BF524 |
f16295e7 | 618 | default 600000000 if BF525 |
1545a111 | 619 | default 400000000 if BF526 |
f16295e7 RG |
620 | default 600000000 if BF527 |
621 | default 400000000 if BF531 | |
622 | default 400000000 if BF532 | |
623 | default 750000000 if BF533 | |
624 | default 500000000 if BF534 | |
625 | default 400000000 if BF536 | |
626 | default 600000000 if BF537 | |
f72eecb9 RG |
627 | default 533333333 if BF538 |
628 | default 533333333 if BF539 | |
f16295e7 | 629 | default 600000000 if BF542 |
f72eecb9 | 630 | default 533333333 if BF544 |
1545a111 MF |
631 | default 600000000 if BF547 |
632 | default 600000000 if BF548 | |
f72eecb9 | 633 | default 533333333 if BF549 |
f16295e7 | 634 | default 600000000 if BF561 |
7c141c1c | 635 | default 800000000 if BF609 |
f16295e7 RG |
636 | |
637 | config MIN_VCO_HZ | |
638 | int | |
639 | default 50000000 | |
640 | ||
641 | config MAX_SCLK_HZ | |
642 | int | |
7c141c1c | 643 | default 200000000 if BF609 |
f72eecb9 | 644 | default 133333333 |
f16295e7 RG |
645 | |
646 | config MIN_SCLK_HZ | |
647 | int | |
648 | default 27000000 | |
649 | ||
650 | comment "Kernel Timer/Scheduler" | |
651 | ||
652 | source kernel/Kconfig.hz | |
653 | ||
dfbaec06 | 654 | config SET_GENERIC_CLOCKEVENTS |
8b5f79f9 | 655 | bool "Generic clock events" |
8b5f79f9 | 656 | default y |
dfbaec06 | 657 | select GENERIC_CLOCKEVENTS |
8b5f79f9 | 658 | |
0d152c27 | 659 | menu "Clock event device" |
1fa9be72 | 660 | depends on GENERIC_CLOCKEVENTS |
1fa9be72 | 661 | config TICKSOURCE_GPTMR0 |
0d152c27 YL |
662 | bool "GPTimer0" |
663 | depends on !SMP | |
1fa9be72 | 664 | select BFIN_GPTIMERS |
1fa9be72 GY |
665 | |
666 | config TICKSOURCE_CORETMR | |
0d152c27 YL |
667 | bool "Core timer" |
668 | default y | |
669 | endmenu | |
1fa9be72 | 670 | |
0d152c27 | 671 | menu "Clock souce" |
8b5f79f9 | 672 | depends on GENERIC_CLOCKEVENTS |
0d152c27 YL |
673 | config CYCLES_CLOCKSOURCE |
674 | bool "CYCLES" | |
675 | default y | |
8b5f79f9 | 676 | depends on !BFIN_SCRATCH_REG_CYCLES |
1fa9be72 | 677 | depends on !SMP |
8b5f79f9 VM |
678 | help |
679 | If you say Y here, you will enable support for using the 'cycles' | |
680 | registers as a clock source. Doing so means you will be unable to | |
681 | safely write to the 'cycles' register during runtime. You will | |
682 | still be able to read it (such as for performance monitoring), but | |
683 | writing the registers will most likely crash the kernel. | |
684 | ||
1fa9be72 | 685 | config GPTMR0_CLOCKSOURCE |
0d152c27 | 686 | bool "GPTimer0" |
3aca47c0 | 687 | select BFIN_GPTIMERS |
1fa9be72 | 688 | depends on !TICKSOURCE_GPTMR0 |
0d152c27 | 689 | endmenu |
1fa9be72 | 690 | |
5f004c20 | 691 | comment "Misc" |
971d5bc4 | 692 | |
f0b5d12f MF |
693 | choice |
694 | prompt "Blackfin Exception Scratch Register" | |
695 | default BFIN_SCRATCH_REG_RETN | |
696 | help | |
697 | Select the resource to reserve for the Exception handler: | |
698 | - RETN: Non-Maskable Interrupt (NMI) | |
699 | - RETE: Exception Return (JTAG/ICE) | |
700 | - CYCLES: Performance counter | |
701 | ||
702 | If you are unsure, please select "RETN". | |
703 | ||
704 | config BFIN_SCRATCH_REG_RETN | |
705 | bool "RETN" | |
706 | help | |
707 | Use the RETN register in the Blackfin exception handler | |
708 | as a stack scratch register. This means you cannot | |
709 | safely use NMI on the Blackfin while running Linux, but | |
710 | you can debug the system with a JTAG ICE and use the | |
711 | CYCLES performance registers. | |
712 | ||
713 | If you are unsure, please select "RETN". | |
714 | ||
715 | config BFIN_SCRATCH_REG_RETE | |
716 | bool "RETE" | |
717 | help | |
718 | Use the RETE register in the Blackfin exception handler | |
719 | as a stack scratch register. This means you cannot | |
720 | safely use a JTAG ICE while debugging a Blackfin board, | |
721 | but you can safely use the CYCLES performance registers | |
722 | and the NMI. | |
723 | ||
724 | If you are unsure, please select "RETN". | |
725 | ||
726 | config BFIN_SCRATCH_REG_CYCLES | |
727 | bool "CYCLES" | |
728 | help | |
729 | Use the CYCLES register in the Blackfin exception handler | |
730 | as a stack scratch register. This means you cannot | |
731 | safely use the CYCLES performance registers on a Blackfin | |
732 | board at anytime, but you can debug the system with a JTAG | |
733 | ICE and use the NMI. | |
734 | ||
735 | If you are unsure, please select "RETN". | |
736 | ||
737 | endchoice | |
738 | ||
1394f032 BW |
739 | endmenu |
740 | ||
741 | ||
742 | menu "Blackfin Kernel Optimizations" | |
743 | ||
1394f032 BW |
744 | comment "Memory Optimizations" |
745 | ||
746 | config I_ENTRY_L1 | |
747 | bool "Locate interrupt entry code in L1 Memory" | |
748 | default y | |
820b127d | 749 | depends on !SMP |
1394f032 | 750 | help |
01dd2fbf ML |
751 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
752 | into L1 instruction memory. (less latency) | |
1394f032 BW |
753 | |
754 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 755 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 | 756 | default y |
820b127d | 757 | depends on !SMP |
1394f032 | 758 | help |
01dd2fbf | 759 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 760 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 761 | (less latency) |
1394f032 BW |
762 | |
763 | config DO_IRQ_L1 | |
764 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
765 | default y | |
820b127d | 766 | depends on !SMP |
1394f032 | 767 | help |
01dd2fbf ML |
768 | If enabled, the frequently called do_irq dispatcher function is linked |
769 | into L1 instruction memory. (less latency) | |
1394f032 BW |
770 | |
771 | config CORE_TIMER_IRQ_L1 | |
772 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
773 | default y | |
820b127d | 774 | depends on !SMP |
1394f032 | 775 | help |
01dd2fbf ML |
776 | If enabled, the frequently called timer_interrupt() function is linked |
777 | into L1 instruction memory. (less latency) | |
1394f032 BW |
778 | |
779 | config IDLE_L1 | |
780 | bool "Locate frequently idle function in L1 Memory" | |
781 | default y | |
820b127d | 782 | depends on !SMP |
1394f032 | 783 | help |
01dd2fbf ML |
784 | If enabled, the frequently called idle function is linked |
785 | into L1 instruction memory. (less latency) | |
1394f032 BW |
786 | |
787 | config SCHEDULE_L1 | |
788 | bool "Locate kernel schedule function in L1 Memory" | |
789 | default y | |
820b127d | 790 | depends on !SMP |
1394f032 | 791 | help |
01dd2fbf ML |
792 | If enabled, the frequently called kernel schedule is linked |
793 | into L1 instruction memory. (less latency) | |
1394f032 BW |
794 | |
795 | config ARITHMETIC_OPS_L1 | |
796 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
797 | default y | |
820b127d | 798 | depends on !SMP |
1394f032 | 799 | help |
01dd2fbf ML |
800 | If enabled, arithmetic functions are linked |
801 | into L1 instruction memory. (less latency) | |
1394f032 BW |
802 | |
803 | config ACCESS_OK_L1 | |
804 | bool "Locate access_ok function in L1 Memory" | |
805 | default y | |
820b127d | 806 | depends on !SMP |
1394f032 | 807 | help |
01dd2fbf ML |
808 | If enabled, the access_ok function is linked |
809 | into L1 instruction memory. (less latency) | |
1394f032 BW |
810 | |
811 | config MEMSET_L1 | |
812 | bool "Locate memset function in L1 Memory" | |
813 | default y | |
820b127d | 814 | depends on !SMP |
1394f032 | 815 | help |
01dd2fbf ML |
816 | If enabled, the memset function is linked |
817 | into L1 instruction memory. (less latency) | |
1394f032 BW |
818 | |
819 | config MEMCPY_L1 | |
820 | bool "Locate memcpy function in L1 Memory" | |
821 | default y | |
820b127d | 822 | depends on !SMP |
1394f032 | 823 | help |
01dd2fbf ML |
824 | If enabled, the memcpy function is linked |
825 | into L1 instruction memory. (less latency) | |
1394f032 | 826 | |
479ba603 RG |
827 | config STRCMP_L1 |
828 | bool "locate strcmp function in L1 Memory" | |
829 | default y | |
820b127d | 830 | depends on !SMP |
479ba603 RG |
831 | help |
832 | If enabled, the strcmp function is linked | |
833 | into L1 instruction memory (less latency). | |
834 | ||
835 | config STRNCMP_L1 | |
836 | bool "locate strncmp function in L1 Memory" | |
837 | default y | |
820b127d | 838 | depends on !SMP |
479ba603 RG |
839 | help |
840 | If enabled, the strncmp function is linked | |
841 | into L1 instruction memory (less latency). | |
842 | ||
843 | config STRCPY_L1 | |
844 | bool "locate strcpy function in L1 Memory" | |
845 | default y | |
820b127d | 846 | depends on !SMP |
479ba603 RG |
847 | help |
848 | If enabled, the strcpy function is linked | |
849 | into L1 instruction memory (less latency). | |
850 | ||
851 | config STRNCPY_L1 | |
852 | bool "locate strncpy function in L1 Memory" | |
853 | default y | |
820b127d | 854 | depends on !SMP |
479ba603 RG |
855 | help |
856 | If enabled, the strncpy function is linked | |
857 | into L1 instruction memory (less latency). | |
858 | ||
1394f032 BW |
859 | config SYS_BFIN_SPINLOCK_L1 |
860 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
861 | default y | |
820b127d | 862 | depends on !SMP |
1394f032 | 863 | help |
01dd2fbf ML |
864 | If enabled, sys_bfin_spinlock function is linked |
865 | into L1 instruction memory. (less latency) | |
1394f032 BW |
866 | |
867 | config IP_CHECKSUM_L1 | |
868 | bool "Locate IP Checksum function in L1 Memory" | |
869 | default n | |
820b127d | 870 | depends on !SMP |
1394f032 | 871 | help |
01dd2fbf ML |
872 | If enabled, the IP Checksum function is linked |
873 | into L1 instruction memory. (less latency) | |
1394f032 BW |
874 | |
875 | config CACHELINE_ALIGNED_L1 | |
876 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
877 | default y if !BF54x |
878 | default n if BF54x | |
95fc2d8f | 879 | depends on !SMP && !BF531 && !CRC32 |
1394f032 | 880 | help |
692105b8 | 881 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 882 | into L1 data memory. (less latency) |
1394f032 BW |
883 | |
884 | config SYSCALL_TAB_L1 | |
885 | bool "Locate Syscall Table L1 Data Memory" | |
886 | default n | |
820b127d | 887 | depends on !SMP && !BF531 |
1394f032 | 888 | help |
01dd2fbf ML |
889 | If enabled, the Syscall LUT is linked |
890 | into L1 data memory. (less latency) | |
1394f032 BW |
891 | |
892 | config CPLB_SWITCH_TAB_L1 | |
893 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
894 | default n | |
820b127d | 895 | depends on !SMP && !BF531 |
1394f032 | 896 | help |
01dd2fbf ML |
897 | If enabled, the CPLB Switch Tables are linked |
898 | into L1 data memory. (less latency) | |
1394f032 | 899 | |
820b127d MF |
900 | config ICACHE_FLUSH_L1 |
901 | bool "Locate icache flush funcs in L1 Inst Memory" | |
74181295 MF |
902 | default y |
903 | help | |
820b127d | 904 | If enabled, the Blackfin icache flushing functions are linked |
74181295 MF |
905 | into L1 instruction memory. |
906 | ||
907 | Note that this might be required to address anomalies, but | |
908 | these functions are pretty small, so it shouldn't be too bad. | |
909 | If you are using a processor affected by an anomaly, the build | |
910 | system will double check for you and prevent it. | |
911 | ||
820b127d MF |
912 | config DCACHE_FLUSH_L1 |
913 | bool "Locate dcache flush funcs in L1 Inst Memory" | |
914 | default y | |
915 | depends on !SMP | |
916 | help | |
917 | If enabled, the Blackfin dcache flushing functions are linked | |
918 | into L1 instruction memory. | |
919 | ||
ca87b7ad GY |
920 | config APP_STACK_L1 |
921 | bool "Support locating application stack in L1 Scratch Memory" | |
922 | default y | |
820b127d | 923 | depends on !SMP |
ca87b7ad GY |
924 | help |
925 | If enabled the application stack can be located in L1 | |
926 | scratch memory (less latency). | |
927 | ||
928 | Currently only works with FLAT binaries. | |
929 | ||
6ad2b84c MF |
930 | config EXCEPTION_L1_SCRATCH |
931 | bool "Locate exception stack in L1 Scratch Memory" | |
932 | default n | |
820b127d | 933 | depends on !SMP && !APP_STACK_L1 |
6ad2b84c MF |
934 | help |
935 | Whenever an exception occurs, use the L1 Scratch memory for | |
936 | stack storage. You cannot place the stacks of FLAT binaries | |
937 | in L1 when using this option. | |
938 | ||
939 | If you don't use L1 Scratch, then you should say Y here. | |
940 | ||
251383c7 RG |
941 | comment "Speed Optimizations" |
942 | config BFIN_INS_LOWOVERHEAD | |
943 | bool "ins[bwl] low overhead, higher interrupt latency" | |
944 | default y | |
820b127d | 945 | depends on !SMP |
251383c7 RG |
946 | help |
947 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
948 | they can be interrupted at any time (even after they have been issued | |
949 | on to the external bus), and re-issued after the interrupt occurs. | |
950 | For memory - this is not a big deal, since memory does not change if | |
951 | it sees a read. | |
952 | ||
953 | If a FIFO is sitting on the end of the read, it will see two reads, | |
954 | when the core only sees one since the FIFO receives both the read | |
955 | which is cancelled (and not delivered to the core) and the one which | |
956 | is re-issued (which is delivered to the core). | |
957 | ||
958 | To solve this, interrupts are turned off before reads occur to | |
959 | I/O space. This option controls which the overhead/latency of | |
960 | controlling interrupts during this time | |
961 | "n" turns interrupts off every read | |
962 | (higher overhead, but lower interrupt latency) | |
963 | "y" turns interrupts off every loop | |
964 | (low overhead, but longer interrupt latency) | |
965 | ||
966 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
967 | interrupt latency issues, it is safe and OK to turn this off. | |
968 | ||
1394f032 BW |
969 | endmenu |
970 | ||
1394f032 BW |
971 | choice |
972 | prompt "Kernel executes from" | |
973 | help | |
974 | Choose the memory type that the kernel will be running in. | |
975 | ||
976 | config RAMKERNEL | |
977 | bool "RAM" | |
978 | help | |
979 | The kernel will be resident in RAM when running. | |
980 | ||
981 | config ROMKERNEL | |
982 | bool "ROM" | |
983 | help | |
984 | The kernel will be resident in FLASH/ROM when running. | |
985 | ||
986 | endchoice | |
987 | ||
56b4f07a MF |
988 | # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both |
989 | config XIP_KERNEL | |
990 | bool | |
991 | default y | |
992 | depends on ROMKERNEL | |
993 | ||
1394f032 BW |
994 | source "mm/Kconfig" |
995 | ||
780431e3 MF |
996 | config BFIN_GPTIMERS |
997 | tristate "Enable Blackfin General Purpose Timers API" | |
998 | default n | |
999 | help | |
1000 | Enable support for the General Purpose Timers API. If you | |
1001 | are unsure, say N. | |
1002 | ||
1003 | To compile this driver as a module, choose M here: the module | |
4737f097 | 1004 | will be called gptimers. |
780431e3 | 1005 | |
1394f032 | 1006 | choice |
d292b000 | 1007 | prompt "Uncached DMA region" |
1394f032 | 1008 | default DMA_UNCACHED_1M |
c8d11a06 SJ |
1009 | config DMA_UNCACHED_32M |
1010 | bool "Enable 32M DMA region" | |
1011 | config DMA_UNCACHED_16M | |
1012 | bool "Enable 16M DMA region" | |
1013 | config DMA_UNCACHED_8M | |
1014 | bool "Enable 8M DMA region" | |
86ad7932 CC |
1015 | config DMA_UNCACHED_4M |
1016 | bool "Enable 4M DMA region" | |
1394f032 BW |
1017 | config DMA_UNCACHED_2M |
1018 | bool "Enable 2M DMA region" | |
1019 | config DMA_UNCACHED_1M | |
1020 | bool "Enable 1M DMA region" | |
c45c0659 BS |
1021 | config DMA_UNCACHED_512K |
1022 | bool "Enable 512K DMA region" | |
1023 | config DMA_UNCACHED_256K | |
1024 | bool "Enable 256K DMA region" | |
1025 | config DMA_UNCACHED_128K | |
1026 | bool "Enable 128K DMA region" | |
1394f032 BW |
1027 | config DMA_UNCACHED_NONE |
1028 | bool "Disable DMA region" | |
1029 | endchoice | |
1030 | ||
1031 | ||
1032 | comment "Cache Support" | |
41ba653f | 1033 | |
3bebca2d | 1034 | config BFIN_ICACHE |
1394f032 | 1035 | bool "Enable ICACHE" |
41ba653f | 1036 | default y |
41ba653f JZ |
1037 | config BFIN_EXTMEM_ICACHEABLE |
1038 | bool "Enable ICACHE for external memory" | |
1039 | depends on BFIN_ICACHE | |
1040 | default y | |
1041 | config BFIN_L2_ICACHEABLE | |
1042 | bool "Enable ICACHE for L2 SRAM" | |
1043 | depends on BFIN_ICACHE | |
b0ce61d5 | 1044 | depends on (BF54x || BF561 || BF60x) && !SMP |
41ba653f JZ |
1045 | default n |
1046 | ||
3bebca2d | 1047 | config BFIN_DCACHE |
1394f032 | 1048 | bool "Enable DCACHE" |
41ba653f | 1049 | default y |
3bebca2d | 1050 | config BFIN_DCACHE_BANKA |
1394f032 | 1051 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 1052 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 1053 | default n |
41ba653f JZ |
1054 | config BFIN_EXTMEM_DCACHEABLE |
1055 | bool "Enable DCACHE for external memory" | |
3bebca2d | 1056 | depends on BFIN_DCACHE |
41ba653f JZ |
1057 | default y |
1058 | choice | |
1059 | prompt "External memory DCACHE policy" | |
1060 | depends on BFIN_EXTMEM_DCACHEABLE | |
1061 | default BFIN_EXTMEM_WRITEBACK if !SMP | |
1062 | default BFIN_EXTMEM_WRITETHROUGH if SMP | |
1063 | config BFIN_EXTMEM_WRITEBACK | |
1394f032 | 1064 | bool "Write back" |
46fa5eec | 1065 | depends on !SMP |
1394f032 BW |
1066 | help |
1067 | Write Back Policy: | |
1068 | Cached data will be written back to SDRAM only when needed. | |
1069 | This can give a nice increase in performance, but beware of | |
1070 | broken drivers that do not properly invalidate/flush their | |
1071 | cache. | |
1072 | ||
1073 | Write Through Policy: | |
1074 | Cached data will always be written back to SDRAM when the | |
1075 | cache is updated. This is a completely safe setting, but | |
1076 | performance is worse than Write Back. | |
1077 | ||
1078 | If you are unsure of the options and you want to be safe, | |
1079 | then go with Write Through. | |
1080 | ||
41ba653f | 1081 | config BFIN_EXTMEM_WRITETHROUGH |
1394f032 BW |
1082 | bool "Write through" |
1083 | help | |
1084 | Write Back Policy: | |
1085 | Cached data will be written back to SDRAM only when needed. | |
1086 | This can give a nice increase in performance, but beware of | |
1087 | broken drivers that do not properly invalidate/flush their | |
1088 | cache. | |
1089 | ||
1090 | Write Through Policy: | |
1091 | Cached data will always be written back to SDRAM when the | |
1092 | cache is updated. This is a completely safe setting, but | |
1093 | performance is worse than Write Back. | |
1094 | ||
1095 | If you are unsure of the options and you want to be safe, | |
1096 | then go with Write Through. | |
1097 | ||
1098 | endchoice | |
1099 | ||
41ba653f JZ |
1100 | config BFIN_L2_DCACHEABLE |
1101 | bool "Enable DCACHE for L2 SRAM" | |
1102 | depends on BFIN_DCACHE | |
b5affb01 | 1103 | depends on (BF54x || BF561 || BF60x) && !SMP |
41ba653f | 1104 | default n |
5ba76675 | 1105 | choice |
41ba653f JZ |
1106 | prompt "L2 SRAM DCACHE policy" |
1107 | depends on BFIN_L2_DCACHEABLE | |
1108 | default BFIN_L2_WRITEBACK | |
1109 | config BFIN_L2_WRITEBACK | |
5ba76675 | 1110 | bool "Write back" |
5ba76675 | 1111 | |
41ba653f | 1112 | config BFIN_L2_WRITETHROUGH |
5ba76675 | 1113 | bool "Write through" |
5ba76675 | 1114 | endchoice |
f099f39a | 1115 | |
41ba653f JZ |
1116 | |
1117 | comment "Memory Protection Unit" | |
b97b8a99 BS |
1118 | config MPU |
1119 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
1120 | default n | |
1121 | help | |
1122 | Use the processor's MPU to protect applications from accessing | |
1123 | memory they do not own. This comes at a performance penalty | |
1124 | and is recommended only for debugging. | |
1125 | ||
692105b8 | 1126 | comment "Asynchronous Memory Configuration" |
1394f032 | 1127 | |
ddf416b2 | 1128 | menu "EBIU_AMGCTL Global Control" |
b5affb01 | 1129 | depends on !BF60x |
1394f032 BW |
1130 | config C_AMCKEN |
1131 | bool "Enable CLKOUT" | |
1132 | default y | |
1133 | ||
1134 | config C_CDPRIO | |
1135 | bool "DMA has priority over core for ext. accesses" | |
1136 | default n | |
1137 | ||
1138 | config C_B0PEN | |
1139 | depends on BF561 | |
1140 | bool "Bank 0 16 bit packing enable" | |
1141 | default y | |
1142 | ||
1143 | config C_B1PEN | |
1144 | depends on BF561 | |
1145 | bool "Bank 1 16 bit packing enable" | |
1146 | default y | |
1147 | ||
1148 | config C_B2PEN | |
1149 | depends on BF561 | |
1150 | bool "Bank 2 16 bit packing enable" | |
1151 | default y | |
1152 | ||
1153 | config C_B3PEN | |
1154 | depends on BF561 | |
1155 | bool "Bank 3 16 bit packing enable" | |
1156 | default n | |
1157 | ||
1158 | choice | |
692105b8 | 1159 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1160 | default C_AMBEN_ALL |
1161 | ||
1162 | config C_AMBEN | |
1163 | bool "Disable All Banks" | |
1164 | ||
1165 | config C_AMBEN_B0 | |
1166 | bool "Enable Bank 0" | |
1167 | ||
1168 | config C_AMBEN_B0_B1 | |
1169 | bool "Enable Bank 0 & 1" | |
1170 | ||
1171 | config C_AMBEN_B0_B1_B2 | |
1172 | bool "Enable Bank 0 & 1 & 2" | |
1173 | ||
1174 | config C_AMBEN_ALL | |
1175 | bool "Enable All Banks" | |
1176 | endchoice | |
1177 | endmenu | |
1178 | ||
1179 | menu "EBIU_AMBCTL Control" | |
b5affb01 | 1180 | depends on !BF60x |
1394f032 | 1181 | config BANK_0 |
c8342f87 | 1182 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1183 | default 0x7BB0 |
c8342f87 MF |
1184 | help |
1185 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1186 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1187 | |
1188 | config BANK_1 | |
c8342f87 | 1189 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1190 | default 0x7BB0 |
197fba56 | 1191 | default 0x5558 if BF54x |
c8342f87 MF |
1192 | help |
1193 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1194 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1195 | |
1196 | config BANK_2 | |
c8342f87 | 1197 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1198 | default 0x7BB0 |
c8342f87 MF |
1199 | help |
1200 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1201 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1202 | |
1203 | config BANK_3 | |
c8342f87 | 1204 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1205 | default 0x99B3 |
c8342f87 MF |
1206 | help |
1207 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1208 | used to control the Asynchronous Memory Bank 3 settings. | |
1209 | ||
1394f032 BW |
1210 | endmenu |
1211 | ||
e40540b3 SZ |
1212 | config EBIU_MBSCTLVAL |
1213 | hex "EBIU Bank Select Control Register" | |
1214 | depends on BF54x | |
1215 | default 0 | |
1216 | ||
1217 | config EBIU_MODEVAL | |
1218 | hex "Flash Memory Mode Control Register" | |
1219 | depends on BF54x | |
1220 | default 1 | |
1221 | ||
1222 | config EBIU_FCTLVAL | |
1223 | hex "Flash Memory Bank Control Register" | |
1224 | depends on BF54x | |
1225 | default 6 | |
1394f032 BW |
1226 | endmenu |
1227 | ||
1228 | ############################################################################# | |
1229 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1230 | ||
1231 | config PCI | |
1232 | bool "PCI support" | |
a95ca3b2 | 1233 | depends on BROKEN |
1394f032 BW |
1234 | help |
1235 | Support for PCI bus. | |
1236 | ||
1237 | source "drivers/pci/Kconfig" | |
1238 | ||
1394f032 BW |
1239 | source "drivers/pcmcia/Kconfig" |
1240 | ||
1241 | source "drivers/pci/hotplug/Kconfig" | |
1242 | ||
1243 | endmenu | |
1244 | ||
1245 | menu "Executable file formats" | |
1246 | ||
1247 | source "fs/Kconfig.binfmt" | |
1248 | ||
1249 | endmenu | |
1250 | ||
1251 | menu "Power management options" | |
ad46163a | 1252 | |
1394f032 BW |
1253 | source "kernel/power/Kconfig" |
1254 | ||
f4cb5700 JB |
1255 | config ARCH_SUSPEND_POSSIBLE |
1256 | def_bool y | |
f4cb5700 | 1257 | |
1394f032 | 1258 | choice |
1efc80b5 | 1259 | prompt "Standby Power Saving Mode" |
0fbd88ca | 1260 | depends on PM && !BF60x |
cfefe3c6 MH |
1261 | default PM_BFIN_SLEEP_DEEPER |
1262 | config PM_BFIN_SLEEP_DEEPER | |
1263 | bool "Sleep Deeper" | |
1264 | help | |
1265 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1266 | power dissipation by disabling the clock to the processor core (CCLK). | |
1267 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1268 | to 0.85 V to provide the greatest power savings, while preserving the | |
1269 | processor state. | |
1270 | The PLL and system clock (SCLK) continue to operate at a very low | |
1271 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1272 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1273 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1274 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1275 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1276 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1277 | ||
1efc80b5 MH |
1278 | If unsure, select "Sleep Deeper". |
1279 | ||
cfefe3c6 MH |
1280 | config PM_BFIN_SLEEP |
1281 | bool "Sleep" | |
1282 | help | |
1283 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1284 | dissipation by disabling the clock to the processor core (CCLK). | |
1285 | The PLL and system clock (SCLK), however, continue to operate in | |
1286 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1287 | up the processor. When in the sleep mode, system DMA access to L1 |
1288 | memory is not supported. | |
1289 | ||
1290 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1291 | endchoice |
1394f032 | 1292 | |
1efc80b5 MH |
1293 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1294 | depends on PM | |
1295 | ||
1efc80b5 MH |
1296 | config PM_BFIN_WAKE_PH6 |
1297 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1298 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1299 | default n |
1300 | help | |
1301 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1302 | ||
1efc80b5 MH |
1303 | config PM_BFIN_WAKE_GP |
1304 | bool "Allow Wake-Up from GPIOs" | |
1305 | depends on PM && BF54x | |
1306 | default n | |
1307 | help | |
1308 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1309 | (all processors, except ADSP-BF549). This option sets |
1310 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1311 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
59bf8964 | 1312 | On ADSP-BF549 this option enables the same functionality on the |
19986289 MH |
1313 | /MRXON pin also PH7. |
1314 | ||
0fbd88ca SM |
1315 | config PM_BFIN_WAKE_PA15 |
1316 | bool "Allow Wake-Up from PA15" | |
1317 | depends on PM && BF60x | |
1318 | default n | |
1319 | help | |
1320 | Enable PA15 Wake-Up | |
1321 | ||
1322 | config PM_BFIN_WAKE_PA15_POL | |
1323 | int "Wake-up priority" | |
1324 | depends on PM_BFIN_WAKE_PA15 | |
1325 | default 0 | |
1326 | help | |
1327 | Wake-Up priority 0(low) 1(high) | |
1328 | ||
1329 | config PM_BFIN_WAKE_PB15 | |
1330 | bool "Allow Wake-Up from PB15" | |
1331 | depends on PM && BF60x | |
1332 | default n | |
1333 | help | |
1334 | Enable PB15 Wake-Up | |
1335 | ||
1336 | config PM_BFIN_WAKE_PB15_POL | |
1337 | int "Wake-up priority" | |
1338 | depends on PM_BFIN_WAKE_PB15 | |
1339 | default 0 | |
1340 | help | |
1341 | Wake-Up priority 0(low) 1(high) | |
1342 | ||
1343 | config PM_BFIN_WAKE_PC15 | |
1344 | bool "Allow Wake-Up from PC15" | |
1345 | depends on PM && BF60x | |
1346 | default n | |
1347 | help | |
1348 | Enable PC15 Wake-Up | |
1349 | ||
1350 | config PM_BFIN_WAKE_PC15_POL | |
1351 | int "Wake-up priority" | |
1352 | depends on PM_BFIN_WAKE_PC15 | |
1353 | default 0 | |
1354 | help | |
1355 | Wake-Up priority 0(low) 1(high) | |
1356 | ||
1357 | config PM_BFIN_WAKE_PD06 | |
1358 | bool "Allow Wake-Up from PD06(ETH0_PHYINT)" | |
1359 | depends on PM && BF60x | |
1360 | default n | |
1361 | help | |
1362 | Enable PD06(ETH0_PHYINT) Wake-up | |
1363 | ||
1364 | config PM_BFIN_WAKE_PD06_POL | |
1365 | int "Wake-up priority" | |
1366 | depends on PM_BFIN_WAKE_PD06 | |
1367 | default 0 | |
1368 | help | |
1369 | Wake-Up priority 0(low) 1(high) | |
1370 | ||
1371 | config PM_BFIN_WAKE_PE12 | |
1372 | bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)" | |
1373 | depends on PM && BF60x | |
1374 | default n | |
1375 | help | |
1376 | Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up | |
1377 | ||
1378 | config PM_BFIN_WAKE_PE12_POL | |
1379 | int "Wake-up priority" | |
1380 | depends on PM_BFIN_WAKE_PE12 | |
1381 | default 0 | |
1382 | help | |
1383 | Wake-Up priority 0(low) 1(high) | |
1384 | ||
1385 | config PM_BFIN_WAKE_PG04 | |
1386 | bool "Allow Wake-Up from PG04(CAN0_RX)" | |
1387 | depends on PM && BF60x | |
1388 | default n | |
1389 | help | |
1390 | Enable PG04(CAN0_RX) Wake-up | |
1391 | ||
1392 | config PM_BFIN_WAKE_PG04_POL | |
1393 | int "Wake-up priority" | |
1394 | depends on PM_BFIN_WAKE_PG04 | |
1395 | default 0 | |
1396 | help | |
1397 | Wake-Up priority 0(low) 1(high) | |
1398 | ||
1399 | config PM_BFIN_WAKE_PG13 | |
1400 | bool "Allow Wake-Up from PG13" | |
1401 | depends on PM && BF60x | |
1402 | default n | |
1403 | help | |
1404 | Enable PG13 Wake-Up | |
1405 | ||
1406 | config PM_BFIN_WAKE_PG13_POL | |
1407 | int "Wake-up priority" | |
1408 | depends on PM_BFIN_WAKE_PG13 | |
1409 | default 0 | |
1410 | help | |
1411 | Wake-Up priority 0(low) 1(high) | |
1412 | ||
1413 | config PM_BFIN_WAKE_USB | |
1414 | bool "Allow Wake-Up from (USB)" | |
1415 | depends on PM && BF60x | |
1416 | default n | |
1417 | help | |
1418 | Enable (USB) Wake-up | |
1419 | ||
1420 | config PM_BFIN_WAKE_USB_POL | |
1421 | int "Wake-up priority" | |
1422 | depends on PM_BFIN_WAKE_USB | |
1423 | default 0 | |
1424 | help | |
1425 | Wake-Up priority 0(low) 1(high) | |
1426 | ||
1394f032 BW |
1427 | endmenu |
1428 | ||
1394f032 BW |
1429 | menu "CPU Frequency scaling" |
1430 | ||
1431 | source "drivers/cpufreq/Kconfig" | |
1432 | ||
5ad2ca5f MH |
1433 | config BFIN_CPU_FREQ |
1434 | bool | |
1435 | depends on CPU_FREQ | |
1436 | select CPU_FREQ_TABLE | |
1437 | default y | |
1438 | ||
14b03204 MH |
1439 | config CPU_VOLTAGE |
1440 | bool "CPU Voltage scaling" | |
73feb5c0 | 1441 | depends on EXPERIMENTAL |
14b03204 MH |
1442 | depends on CPU_FREQ |
1443 | default n | |
1444 | help | |
1445 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1446 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1447 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1448 | the PLL may unlock. |
1449 | ||
1394f032 BW |
1450 | endmenu |
1451 | ||
1394f032 BW |
1452 | source "net/Kconfig" |
1453 | ||
1454 | source "drivers/Kconfig" | |
1455 | ||
872d024b MF |
1456 | source "drivers/firmware/Kconfig" |
1457 | ||
1394f032 BW |
1458 | source "fs/Kconfig" |
1459 | ||
74ce8322 | 1460 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1461 | |
1462 | source "security/Kconfig" | |
1463 | ||
1464 | source "crypto/Kconfig" | |
1465 | ||
1466 | source "lib/Kconfig" |