Commit | Line | Data |
---|---|---|
1394f032 | 1 | /* |
dd3dd384 | 2 | * bfin_dma_5xx.c - Blackfin DMA implementation |
1394f032 | 3 | * |
9c417a43 | 4 | * Copyright 2004-2008 Analog Devices Inc. |
96f1050d | 5 | * |
dd3dd384 | 6 | * Licensed under the GPL-2 or later. |
1394f032 BW |
7 | */ |
8 | ||
9 | #include <linux/errno.h> | |
dd3dd384 MF |
10 | #include <linux/interrupt.h> |
11 | #include <linux/kernel.h> | |
1394f032 | 12 | #include <linux/module.h> |
dd3dd384 | 13 | #include <linux/param.h> |
d642a8ad | 14 | #include <linux/proc_fs.h> |
1394f032 | 15 | #include <linux/sched.h> |
d642a8ad | 16 | #include <linux/seq_file.h> |
dd3dd384 | 17 | #include <linux/spinlock.h> |
1394f032 | 18 | |
24a07a12 | 19 | #include <asm/blackfin.h> |
1394f032 | 20 | #include <asm/cacheflush.h> |
dd3dd384 MF |
21 | #include <asm/dma.h> |
22 | #include <asm/uaccess.h> | |
837ec2d5 | 23 | #include <asm/early_printk.h> |
1394f032 | 24 | |
76068c3c RG |
25 | /* |
26 | * To make sure we work around 05000119 - we always check DMA_DONE bit, | |
27 | * never the DMA_RUN bit | |
28 | */ | |
29 | ||
9c417a43 MF |
30 | struct dma_channel dma_ch[MAX_DMA_CHANNELS]; |
31 | EXPORT_SYMBOL(dma_ch); | |
1394f032 | 32 | |
a161bb05 | 33 | static int __init blackfin_dma_init(void) |
1394f032 BW |
34 | { |
35 | int i; | |
36 | ||
37 | printk(KERN_INFO "Blackfin DMA Controller\n"); | |
38 | ||
211daf9d | 39 | for (i = 0; i < MAX_DMA_CHANNELS; i++) { |
1394f032 | 40 | dma_ch[i].chan_status = DMA_CHANNEL_FREE; |
77955664 | 41 | dma_ch[i].regs = dma_io_base_addr[i]; |
1394f032 BW |
42 | mutex_init(&(dma_ch[i].dmalock)); |
43 | } | |
23ee968d | 44 | /* Mark MEMDMA Channel 0 as requested since we're using it internally */ |
d642a8ad GY |
45 | request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy"); |
46 | request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy"); | |
a924db7c MH |
47 | |
48 | #if defined(CONFIG_DEB_DMA_URGENT) | |
49 | bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | |
50 | | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT); | |
51 | #endif | |
d642a8ad | 52 | |
1394f032 BW |
53 | return 0; |
54 | } | |
1394f032 BW |
55 | arch_initcall(blackfin_dma_init); |
56 | ||
d642a8ad | 57 | #ifdef CONFIG_PROC_FS |
d642a8ad GY |
58 | static int proc_dma_show(struct seq_file *m, void *v) |
59 | { | |
60 | int i; | |
61 | ||
dd3dd384 | 62 | for (i = 0; i < MAX_DMA_CHANNELS; ++i) |
d642a8ad GY |
63 | if (dma_ch[i].chan_status != DMA_CHANNEL_FREE) |
64 | seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id); | |
65 | ||
66 | return 0; | |
67 | } | |
68 | ||
69 | static int proc_dma_open(struct inode *inode, struct file *file) | |
70 | { | |
71 | return single_open(file, proc_dma_show, NULL); | |
72 | } | |
73 | ||
74 | static const struct file_operations proc_dma_operations = { | |
75 | .open = proc_dma_open, | |
76 | .read = seq_read, | |
77 | .llseek = seq_lseek, | |
78 | .release = single_release, | |
79 | }; | |
80 | ||
81 | static int __init proc_dma_init(void) | |
82 | { | |
83 | return proc_create("dma", 0, NULL, &proc_dma_operations) != NULL; | |
84 | } | |
85 | late_initcall(proc_dma_init); | |
86 | #endif | |
87 | ||
9c417a43 MF |
88 | /** |
89 | * request_dma - request a DMA channel | |
90 | * | |
91 | * Request the specific DMA channel from the system if it's available. | |
92 | */ | |
99532fd2 | 93 | int request_dma(unsigned int channel, const char *device_id) |
1394f032 | 94 | { |
1394f032 | 95 | pr_debug("request_dma() : BEGIN \n"); |
d642a8ad GY |
96 | |
97 | if (device_id == NULL) | |
98 | printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel); | |
5ce998cf MH |
99 | |
100 | #if defined(CONFIG_BF561) && ANOMALY_05000182 | |
101 | if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) { | |
102 | if (get_cclk() > 500000000) { | |
103 | printk(KERN_WARNING | |
104 | "Request IMDMA failed due to ANOMALY 05000182\n"); | |
105 | return -EFAULT; | |
106 | } | |
107 | } | |
108 | #endif | |
109 | ||
1394f032 BW |
110 | mutex_lock(&(dma_ch[channel].dmalock)); |
111 | ||
112 | if ((dma_ch[channel].chan_status == DMA_CHANNEL_REQUESTED) | |
113 | || (dma_ch[channel].chan_status == DMA_CHANNEL_ENABLED)) { | |
114 | mutex_unlock(&(dma_ch[channel].dmalock)); | |
115 | pr_debug("DMA CHANNEL IN USE \n"); | |
116 | return -EBUSY; | |
117 | } else { | |
118 | dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED; | |
119 | pr_debug("DMA CHANNEL IS ALLOCATED \n"); | |
120 | } | |
121 | ||
122 | mutex_unlock(&(dma_ch[channel].dmalock)); | |
123 | ||
8b01eaff | 124 | #ifdef CONFIG_BF54x |
549aaa84 | 125 | if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) { |
ab2375f2 SZ |
126 | unsigned int per_map; |
127 | per_map = dma_ch[channel].regs->peripheral_map & 0xFFF; | |
128 | if (strncmp(device_id, "BFIN_UART", 9) == 0) | |
129 | dma_ch[channel].regs->peripheral_map = per_map | | |
5be36d22 | 130 | ((channel - CH_UART2_RX + 0xC)<<12); |
ab2375f2 SZ |
131 | else |
132 | dma_ch[channel].regs->peripheral_map = per_map | | |
5be36d22 | 133 | ((channel - CH_UART2_RX + 0x6)<<12); |
549aaa84 | 134 | } |
8b01eaff SZ |
135 | #endif |
136 | ||
1394f032 | 137 | dma_ch[channel].device_id = device_id; |
9b011407 | 138 | dma_ch[channel].irq = 0; |
1394f032 BW |
139 | |
140 | /* This is to be enabled by putting a restriction - | |
141 | * you have to request DMA, before doing any operations on | |
142 | * descriptor/channel | |
143 | */ | |
144 | pr_debug("request_dma() : END \n"); | |
596b565b | 145 | return 0; |
1394f032 BW |
146 | } |
147 | EXPORT_SYMBOL(request_dma); | |
148 | ||
68532bda | 149 | int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data) |
1394f032 | 150 | { |
ac860751 RK |
151 | BUG_ON(channel >= MAX_DMA_CHANNELS || |
152 | dma_ch[channel].chan_status == DMA_CHANNEL_FREE); | |
1394f032 BW |
153 | |
154 | if (callback != NULL) { | |
8f1cc233 MF |
155 | int ret; |
156 | unsigned int irq = channel2irq(channel); | |
1394f032 | 157 | |
8f1cc233 MF |
158 | ret = request_irq(irq, callback, IRQF_DISABLED, |
159 | dma_ch[channel].device_id, data); | |
160 | if (ret) | |
161 | return ret; | |
162 | ||
163 | dma_ch[channel].irq = irq; | |
164 | dma_ch[channel].data = data; | |
1394f032 BW |
165 | } |
166 | return 0; | |
167 | } | |
168 | EXPORT_SYMBOL(set_dma_callback); | |
169 | ||
9c417a43 MF |
170 | /** |
171 | * clear_dma_buffer - clear DMA fifos for specified channel | |
172 | * | |
173 | * Set the Buffer Clear bit in the Configuration register of specific DMA | |
174 | * channel. This will stop the descriptor based DMA operation. | |
175 | */ | |
176 | static void clear_dma_buffer(unsigned int channel) | |
177 | { | |
178 | dma_ch[channel].regs->cfg |= RESTART; | |
179 | SSYNC(); | |
180 | dma_ch[channel].regs->cfg &= ~RESTART; | |
181 | } | |
182 | ||
1394f032 BW |
183 | void free_dma(unsigned int channel) |
184 | { | |
1394f032 | 185 | pr_debug("freedma() : BEGIN \n"); |
ac860751 RK |
186 | BUG_ON(channel >= MAX_DMA_CHANNELS || |
187 | dma_ch[channel].chan_status == DMA_CHANNEL_FREE); | |
1394f032 BW |
188 | |
189 | /* Halt the DMA */ | |
190 | disable_dma(channel); | |
191 | clear_dma_buffer(channel); | |
192 | ||
9b011407 | 193 | if (dma_ch[channel].irq) |
a2ba8b19 | 194 | free_irq(dma_ch[channel].irq, dma_ch[channel].data); |
1394f032 BW |
195 | |
196 | /* Clear the DMA Variable in the Channel */ | |
197 | mutex_lock(&(dma_ch[channel].dmalock)); | |
198 | dma_ch[channel].chan_status = DMA_CHANNEL_FREE; | |
199 | mutex_unlock(&(dma_ch[channel].dmalock)); | |
200 | ||
201 | pr_debug("freedma() : END \n"); | |
202 | } | |
203 | EXPORT_SYMBOL(free_dma); | |
204 | ||
1efc80b5 | 205 | #ifdef CONFIG_PM |
c9e0020d MF |
206 | # ifndef MAX_DMA_SUSPEND_CHANNELS |
207 | # define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS | |
208 | # endif | |
1efc80b5 MH |
209 | int blackfin_dma_suspend(void) |
210 | { | |
211 | int i; | |
212 | ||
c9e0020d | 213 | for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i) { |
1efc80b5 MH |
214 | if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) { |
215 | printk(KERN_ERR "DMA Channel %d failed to suspend\n", i); | |
216 | return -EBUSY; | |
217 | } | |
218 | ||
219 | dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map; | |
220 | } | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | void blackfin_dma_resume(void) | |
226 | { | |
227 | int i; | |
c9e0020d | 228 | for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i) |
1efc80b5 MH |
229 | dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map; |
230 | } | |
231 | #endif | |
232 | ||
dd3dd384 MF |
233 | /** |
234 | * blackfin_dma_early_init - minimal DMA init | |
235 | * | |
236 | * Setup a few DMA registers so we can safely do DMA transfers early on in | |
237 | * the kernel booting process. Really this just means using dma_memcpy(). | |
238 | */ | |
239 | void __init blackfin_dma_early_init(void) | |
1394f032 | 240 | { |
837ec2d5 | 241 | early_shadow_stamp(); |
1394f032 | 242 | bfin_write_MDMA_S0_CONFIG(0); |
fecbd736 RG |
243 | bfin_write_MDMA_S1_CONFIG(0); |
244 | } | |
245 | ||
246 | void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size) | |
247 | { | |
248 | unsigned long dst = (unsigned long)pdst; | |
249 | unsigned long src = (unsigned long)psrc; | |
250 | struct dma_register *dst_ch, *src_ch; | |
251 | ||
837ec2d5 RG |
252 | early_shadow_stamp(); |
253 | ||
fecbd736 RG |
254 | /* We assume that everything is 4 byte aligned, so include |
255 | * a basic sanity check | |
256 | */ | |
257 | BUG_ON(dst % 4); | |
258 | BUG_ON(src % 4); | |
259 | BUG_ON(size % 4); | |
260 | ||
fecbd736 RG |
261 | src_ch = 0; |
262 | /* Find an avalible memDMA channel */ | |
263 | while (1) { | |
532f07ca | 264 | if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) { |
fecbd736 RG |
265 | dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR; |
266 | src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR; | |
532f07ca MF |
267 | } else { |
268 | dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR; | |
269 | src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR; | |
fecbd736 RG |
270 | } |
271 | ||
532f07ca MF |
272 | if (!bfin_read16(&src_ch->cfg)) |
273 | break; | |
274 | else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) { | |
275 | bfin_write16(&src_ch->cfg, 0); | |
fecbd736 | 276 | break; |
fecbd736 | 277 | } |
fecbd736 RG |
278 | } |
279 | ||
532f07ca MF |
280 | /* Force a sync in case a previous config reset on this channel |
281 | * occurred. This is needed so subsequent writes to DMA registers | |
282 | * are not spuriously lost/corrupted. | |
283 | */ | |
284 | __builtin_bfin_ssync(); | |
285 | ||
fecbd736 RG |
286 | /* Destination */ |
287 | bfin_write32(&dst_ch->start_addr, dst); | |
288 | bfin_write16(&dst_ch->x_count, size >> 2); | |
289 | bfin_write16(&dst_ch->x_modify, 1 << 2); | |
290 | bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR); | |
291 | ||
292 | /* Source */ | |
293 | bfin_write32(&src_ch->start_addr, src); | |
294 | bfin_write16(&src_ch->x_count, size >> 2); | |
295 | bfin_write16(&src_ch->x_modify, 1 << 2); | |
296 | bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR); | |
297 | ||
298 | /* Enable */ | |
299 | bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32); | |
300 | bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32); | |
301 | ||
302 | /* Since we are atomic now, don't use the workaround ssync */ | |
303 | __builtin_bfin_ssync(); | |
304 | } | |
305 | ||
306 | void __init early_dma_memcpy_done(void) | |
307 | { | |
837ec2d5 RG |
308 | early_shadow_stamp(); |
309 | ||
fecbd736 RG |
310 | while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) || |
311 | (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE))) | |
312 | continue; | |
313 | ||
314 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | |
315 | bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR); | |
316 | /* | |
317 | * Now that DMA is done, we would normally flush cache, but | |
318 | * i/d cache isn't running this early, so we don't bother, | |
319 | * and just clear out the DMA channel for next time | |
320 | */ | |
321 | bfin_write_MDMA_S0_CONFIG(0); | |
322 | bfin_write_MDMA_S1_CONFIG(0); | |
323 | bfin_write_MDMA_D0_CONFIG(0); | |
324 | bfin_write_MDMA_D1_CONFIG(0); | |
325 | ||
326 | __builtin_bfin_ssync(); | |
1394f032 | 327 | } |
5f9a3e89 | 328 | |
49946e73 | 329 | /** |
dd3dd384 | 330 | * __dma_memcpy - program the MDMA registers |
49946e73 | 331 | * |
dd3dd384 MF |
332 | * Actually program MDMA0 and wait for the transfer to finish. Disable IRQs |
333 | * while programming registers so that everything is fully configured. Wait | |
334 | * for DMA to finish with IRQs enabled. If interrupted, the initial DMA_DONE | |
335 | * check will make sure we don't clobber any existing transfer. | |
49946e73 | 336 | */ |
dd3dd384 | 337 | static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf) |
23ee968d | 338 | { |
dd3dd384 | 339 | static DEFINE_SPINLOCK(mdma_lock); |
23ee968d | 340 | unsigned long flags; |
1f83b8f1 | 341 | |
dd3dd384 MF |
342 | spin_lock_irqsave(&mdma_lock, flags); |
343 | ||
41245ac5 MF |
344 | /* Force a sync in case a previous config reset on this channel |
345 | * occurred. This is needed so subsequent writes to DMA registers | |
346 | * are not spuriously lost/corrupted. Do it under irq lock and | |
347 | * without the anomaly version (because we are atomic already). | |
348 | */ | |
349 | __builtin_bfin_ssync(); | |
350 | ||
dd3dd384 MF |
351 | if (bfin_read_MDMA_S0_CONFIG()) |
352 | while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) | |
353 | continue; | |
354 | ||
355 | if (conf & DMA2D) { | |
356 | /* For larger bit sizes, we've already divided down cnt so it | |
357 | * is no longer a multiple of 64k. So we have to break down | |
358 | * the limit here so it is a multiple of the incoming size. | |
359 | * There is no limitation here in terms of total size other | |
360 | * than the hardware though as the bits lost in the shift are | |
361 | * made up by MODIFY (== we can hit the whole address space). | |
362 | * X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4 | |
363 | */ | |
364 | u32 shift = abs(dmod) >> 1; | |
365 | size_t ycnt = cnt >> (16 - shift); | |
366 | cnt = 1 << (16 - shift); | |
367 | bfin_write_MDMA_D0_Y_COUNT(ycnt); | |
368 | bfin_write_MDMA_S0_Y_COUNT(ycnt); | |
369 | bfin_write_MDMA_D0_Y_MODIFY(dmod); | |
370 | bfin_write_MDMA_S0_Y_MODIFY(smod); | |
371 | } | |
1f83b8f1 | 372 | |
dd3dd384 MF |
373 | bfin_write_MDMA_D0_START_ADDR(daddr); |
374 | bfin_write_MDMA_D0_X_COUNT(cnt); | |
375 | bfin_write_MDMA_D0_X_MODIFY(dmod); | |
23ee968d MH |
376 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); |
377 | ||
dd3dd384 MF |
378 | bfin_write_MDMA_S0_START_ADDR(saddr); |
379 | bfin_write_MDMA_S0_X_COUNT(cnt); | |
380 | bfin_write_MDMA_S0_X_MODIFY(smod); | |
23ee968d MH |
381 | bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR); |
382 | ||
dd3dd384 MF |
383 | bfin_write_MDMA_S0_CONFIG(DMAEN | conf); |
384 | bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf); | |
385 | ||
386 | spin_unlock_irqrestore(&mdma_lock, flags); | |
23ee968d | 387 | |
1a7d91d6 MH |
388 | SSYNC(); |
389 | ||
dd3dd384 MF |
390 | while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) |
391 | if (bfin_read_MDMA_S0_CONFIG()) | |
392 | continue; | |
393 | else | |
394 | return; | |
23ee968d MH |
395 | |
396 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | |
397 | ||
398 | bfin_write_MDMA_S0_CONFIG(0); | |
399 | bfin_write_MDMA_D0_CONFIG(0); | |
23ee968d | 400 | } |
23ee968d | 401 | |
dd3dd384 MF |
402 | /** |
403 | * _dma_memcpy - translate C memcpy settings into MDMA settings | |
404 | * | |
405 | * Handle all the high level steps before we touch the MDMA registers. So | |
7ad883a9 | 406 | * handle direction, tweaking of sizes, and formatting of addresses. |
dd3dd384 MF |
407 | */ |
408 | static void *_dma_memcpy(void *pdst, const void *psrc, size_t size) | |
23ee968d | 409 | { |
dd3dd384 MF |
410 | u32 conf, shift; |
411 | s16 mod; | |
412 | unsigned long dst = (unsigned long)pdst; | |
413 | unsigned long src = (unsigned long)psrc; | |
1f83b8f1 | 414 | |
dd3dd384 MF |
415 | if (size == 0) |
416 | return NULL; | |
1a7d91d6 | 417 | |
dd3dd384 MF |
418 | if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) { |
419 | conf = WDSIZE_32; | |
420 | shift = 2; | |
421 | } else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) { | |
422 | conf = WDSIZE_16; | |
423 | shift = 1; | |
424 | } else { | |
425 | conf = WDSIZE_8; | |
426 | shift = 0; | |
427 | } | |
23ee968d | 428 | |
dd3dd384 MF |
429 | /* If the two memory regions have a chance of overlapping, make |
430 | * sure the memcpy still works as expected. Do this by having the | |
431 | * copy run backwards instead. | |
432 | */ | |
433 | mod = 1 << shift; | |
434 | if (src < dst) { | |
435 | mod *= -1; | |
436 | dst += size + mod; | |
437 | src += size + mod; | |
438 | } | |
439 | size >>= shift; | |
23ee968d | 440 | |
dd3dd384 MF |
441 | if (size > 0x10000) |
442 | conf |= DMA2D; | |
23ee968d | 443 | |
dd3dd384 | 444 | __dma_memcpy(dst, mod, src, mod, size, conf); |
23ee968d | 445 | |
dd3dd384 | 446 | return pdst; |
23ee968d | 447 | } |
23ee968d | 448 | |
dd3dd384 MF |
449 | /** |
450 | * dma_memcpy - DMA memcpy under mutex lock | |
451 | * | |
452 | * Do not check arguments before starting the DMA memcpy. Break the transfer | |
453 | * up into two pieces. The first transfer is in multiples of 64k and the | |
454 | * second transfer is the piece smaller than 64k. | |
455 | */ | |
7ad883a9 | 456 | void *dma_memcpy(void *pdst, const void *psrc, size_t size) |
23ee968d | 457 | { |
7ad883a9 MF |
458 | unsigned long dst = (unsigned long)pdst; |
459 | unsigned long src = (unsigned long)psrc; | |
dd3dd384 | 460 | size_t bulk, rest; |
7ad883a9 | 461 | |
67834fa9 | 462 | if (bfin_addr_dcacheable(src)) |
7ad883a9 MF |
463 | blackfin_dcache_flush_range(src, src + size); |
464 | ||
67834fa9 | 465 | if (bfin_addr_dcacheable(dst)) |
7ad883a9 MF |
466 | blackfin_dcache_invalidate_range(dst, dst + size); |
467 | ||
dd3dd384 MF |
468 | bulk = size & ~0xffff; |
469 | rest = size - bulk; | |
470 | if (bulk) | |
7ad883a9 MF |
471 | _dma_memcpy(pdst, psrc, bulk); |
472 | _dma_memcpy(pdst + bulk, psrc + bulk, rest); | |
473 | return pdst; | |
23ee968d | 474 | } |
dd3dd384 | 475 | EXPORT_SYMBOL(dma_memcpy); |
23ee968d | 476 | |
dd3dd384 MF |
477 | /** |
478 | * safe_dma_memcpy - DMA memcpy w/argument checking | |
479 | * | |
480 | * Verify arguments are safe before heading to dma_memcpy(). | |
481 | */ | |
482 | void *safe_dma_memcpy(void *dst, const void *src, size_t size) | |
23ee968d | 483 | { |
dd3dd384 MF |
484 | if (!access_ok(VERIFY_WRITE, dst, size)) |
485 | return NULL; | |
486 | if (!access_ok(VERIFY_READ, src, size)) | |
487 | return NULL; | |
488 | return dma_memcpy(dst, src, size); | |
23ee968d | 489 | } |
dd3dd384 | 490 | EXPORT_SYMBOL(safe_dma_memcpy); |
23ee968d | 491 | |
dd3dd384 MF |
492 | static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len, |
493 | u16 size, u16 dma_size) | |
23ee968d | 494 | { |
dd3dd384 MF |
495 | blackfin_dcache_flush_range(buf, buf + len * size); |
496 | __dma_memcpy(addr, 0, buf, size, len, dma_size); | |
23ee968d | 497 | } |
23ee968d | 498 | |
dd3dd384 MF |
499 | static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len, |
500 | u16 size, u16 dma_size) | |
23ee968d | 501 | { |
dd3dd384 MF |
502 | blackfin_dcache_invalidate_range(buf, buf + len * size); |
503 | __dma_memcpy(buf, size, addr, 0, len, dma_size); | |
23ee968d | 504 | } |
dd3dd384 MF |
505 | |
506 | #define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \ | |
507 | void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \ | |
508 | { \ | |
509 | _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \ | |
510 | } \ | |
511 | EXPORT_SYMBOL(dma_##io##s##bwl) | |
512 | MAKE_DMA_IO(out, b, 1, 8, const); | |
513 | MAKE_DMA_IO(in, b, 1, 8, ); | |
514 | MAKE_DMA_IO(out, w, 2, 16, const); | |
515 | MAKE_DMA_IO(in, w, 2, 16, ); | |
516 | MAKE_DMA_IO(out, l, 4, 32, const); | |
517 | MAKE_DMA_IO(in, l, 4, 32, ); |