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Blackfin: use common code for cycle->nanosecond conversion
[deliverable/linux.git] / arch / blackfin / kernel / bfin_gpio.c
CommitLineData
1394f032 1/*
96f1050d 2 * GPIO Abstraction Layer
1394f032 3 *
96f1050d 4 * Copyright 2006-2009 Analog Devices Inc.
1394f032 5 *
96f1050d 6 * Licensed under the GPL-2 or later
1394f032
BW		 7 */
8
168f1212 9#include <linux/delay.h>
1394f032
BW		 10#include <linux/module.h>
11#include <linux/err.h>
1545a111 12#include <linux/proc_fs.h>
1394f032
BW		 13#include <asm/blackfin.h>
14#include <asm/gpio.h>
c58c2140 15#include <asm/portmux.h>
1394f032
BW		 16#include <linux/irq.h>
17
2b39331a
MH		 18#if ANOMALY_05000311 || ANOMALY_05000323
19enum {
20 AWA_data = SYSCR,
21 AWA_data_clear = SYSCR,
22 AWA_data_set = SYSCR,
23 AWA_toggle = SYSCR,
6ed83942
GY		 24 AWA_maska = BFIN_UART_SCR,
25 AWA_maska_clear = BFIN_UART_SCR,
26 AWA_maska_set = BFIN_UART_SCR,
27 AWA_maska_toggle = BFIN_UART_SCR,
28 AWA_maskb = BFIN_UART_GCTL,
29 AWA_maskb_clear = BFIN_UART_GCTL,
30 AWA_maskb_set = BFIN_UART_GCTL,
31 AWA_maskb_toggle = BFIN_UART_GCTL,
2b39331a
MH		 32 AWA_dir = SPORT1_STAT,
33 AWA_polar = SPORT1_STAT,
34 AWA_edge = SPORT1_STAT,
35 AWA_both = SPORT1_STAT,
36#if ANOMALY_05000311
37 AWA_inen = TIMER_ENABLE,
38#elif ANOMALY_05000323
39 AWA_inen = DMA1_1_CONFIG,
40#endif
41};
42 /* Anomaly Workaround */
43#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
44#else
45#define AWA_DUMMY_READ(...) do { } while (0)
46#endif
47
f556309e 48static struct gpio_port_t * const gpio_array[] = {
dc26aec2 49#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
1394f032 50 (struct gpio_port_t *) FIO_FLAG_D,
269647dc 51#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
1394f032
BW		 52 (struct gpio_port_t *) PORTFIO,
53 (struct gpio_port_t *) PORTGIO,
54 (struct gpio_port_t *) PORTHIO,
f556309e
MF		 55#elif defined(BF561_FAMILY)
56 (struct gpio_port_t *) FIO0_FLAG_D,
57 (struct gpio_port_t *) FIO1_FLAG_D,
58 (struct gpio_port_t *) FIO2_FLAG_D,
269647dc 59#elif defined(CONFIG_BF54x)
f556309e
MF		 60 (struct gpio_port_t *)PORTA_FER,
61 (struct gpio_port_t *)PORTB_FER,
62 (struct gpio_port_t *)PORTC_FER,
63 (struct gpio_port_t *)PORTD_FER,
64 (struct gpio_port_t *)PORTE_FER,
65 (struct gpio_port_t *)PORTF_FER,
66 (struct gpio_port_t *)PORTG_FER,
67 (struct gpio_port_t *)PORTH_FER,
68 (struct gpio_port_t *)PORTI_FER,
69 (struct gpio_port_t *)PORTJ_FER,
70#else
71# error no gpio arrays defined
72#endif
1394f032
BW		 73};
74
269647dc 75#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
f556309e 76static unsigned short * const port_fer[] = {
1394f032
BW		 77 (unsigned short *) PORTF_FER,
78 (unsigned short *) PORTG_FER,
79 (unsigned short *) PORTH_FER,
80};
1394f032 81
f556309e
MF		 82# if !defined(BF537_FAMILY)
83static unsigned short * const port_mux[] = {
59003145
MH		 84 (unsigned short *) PORTF_MUX,
85 (unsigned short *) PORTG_MUX,
86 (unsigned short *) PORTH_MUX,
87};
88
89static const
0ce5eaf8 90u8 pmux_offset[][16] = {
269647dc 91# if defined(CONFIG_BF52x)
0ce5eaf8
GY		 92 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
93 { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
94 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
269647dc 95# elif defined(CONFIG_BF51x)
0ce5eaf8
GY		 96 { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */
97 { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */
98 { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */
99# endif
100};
f556309e 101# endif
0ce5eaf8 102
d2b11a46
MH		 103#endif
104
397861cd 105static unsigned short reserved_gpio_map[GPIO_BANK_NUM];
fac3cf43 106static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
9570ff4a 107static unsigned short reserved_gpio_irq_map[GPIO_BANK_NUM];
c58c2140 108
8c613623
MH		 109#define RESOURCE_LABEL_SIZE 16
110
fac3cf43 111static struct str_ident {
8c613623 112 char name[RESOURCE_LABEL_SIZE];
fac3cf43 113} str_ident[MAX_RESOURCES];
1394f032 114
1efc80b5 115#if defined(CONFIG_PM)
397861cd 116static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
59003145
MH		 117#endif
118
a2c8cfef 119inline int check_gpio(unsigned gpio)
d2b11a46 120{
269647dc 121#if defined(CONFIG_BF54x)
d2b11a46
MH		 122 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
123 || gpio == GPIO_PH14 || gpio == GPIO_PH15
27228b2e 124 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
d2b11a46 125 return -EINVAL;
27228b2e 126#endif
e7613aab 127 if (gpio >= MAX_BLACKFIN_GPIOS)
1394f032
BW		 128 return -EINVAL;
129 return 0;
130}
131
74c04503 132static void gpio_error(unsigned gpio)
acbcd263
MH		 133{
134 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
135}
136
c58c2140
MH		 137static void set_label(unsigned short ident, const char *label)
138{
e9fae189 139 if (label) {
8c613623 140 strncpy(str_ident[ident].name, label,
c58c2140 141 RESOURCE_LABEL_SIZE);
8c613623 142 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
c58c2140
MH		 143 }
144}
145
146static char *get_label(unsigned short ident)
147{
8c613623 148 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
c58c2140
MH		 149}
150
151static int cmp_label(unsigned short ident, const char *label)
152{
fac3cf43
MH		 153 if (label == NULL) {
154 dump_stack();
155 printk(KERN_ERR "Please provide none-null label\n");
156 }
157
e9fae189 158 if (label)
1f7d373f 159 return strcmp(str_ident[ident].name, label);
c58c2140
MH		 160 else
161 return -EINVAL;
162}
163
a2c8cfef 164static void port_setup(unsigned gpio, unsigned short usage)
1394f032 165{
a2d03a1d
MF		 166 if (check_gpio(gpio))
167 return;
168
269647dc 169#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
a2d03a1d
MF		 170 if (usage == GPIO_USAGE)
171 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
172 else
173 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
174 SSYNC();
269647dc 175#elif defined(CONFIG_BF54x)
d2b11a46
MH		 176 if (usage == GPIO_USAGE)
177 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
178 else
179 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
180 SSYNC();
1394f032 181#endif
a2d03a1d 182}
1394f032 183
c58c2140 184#ifdef BF537_FAMILY
8c613623
MH		 185static struct {
186 unsigned short res;
187 unsigned short offset;
188} port_mux_lut[] = {
189 {.res = P_PPI0_D13, .offset = 11},
190 {.res = P_PPI0_D14, .offset = 11},
191 {.res = P_PPI0_D15, .offset = 11},
192 {.res = P_SPORT1_TFS, .offset = 11},
193 {.res = P_SPORT1_TSCLK, .offset = 11},
194 {.res = P_SPORT1_DTPRI, .offset = 11},
195 {.res = P_PPI0_D10, .offset = 10},
196 {.res = P_PPI0_D11, .offset = 10},
197 {.res = P_PPI0_D12, .offset = 10},
198 {.res = P_SPORT1_RSCLK, .offset = 10},
199 {.res = P_SPORT1_RFS, .offset = 10},
200 {.res = P_SPORT1_DRPRI, .offset = 10},
201 {.res = P_PPI0_D8, .offset = 9},
202 {.res = P_PPI0_D9, .offset = 9},
203 {.res = P_SPORT1_DRSEC, .offset = 9},
204 {.res = P_SPORT1_DTSEC, .offset = 9},
205 {.res = P_TMR2, .offset = 8},
206 {.res = P_PPI0_FS3, .offset = 8},
207 {.res = P_TMR3, .offset = 7},
208 {.res = P_SPI0_SSEL4, .offset = 7},
209 {.res = P_TMR4, .offset = 6},
210 {.res = P_SPI0_SSEL5, .offset = 6},
211 {.res = P_TMR5, .offset = 5},
212 {.res = P_SPI0_SSEL6, .offset = 5},
213 {.res = P_UART1_RX, .offset = 4},
214 {.res = P_UART1_TX, .offset = 4},
215 {.res = P_TMR6, .offset = 4},
216 {.res = P_TMR7, .offset = 4},
217 {.res = P_UART0_RX, .offset = 3},
218 {.res = P_UART0_TX, .offset = 3},
219 {.res = P_DMAR0, .offset = 3},
220 {.res = P_DMAR1, .offset = 3},
221 {.res = P_SPORT0_DTSEC, .offset = 1},
222 {.res = P_SPORT0_DRSEC, .offset = 1},
223 {.res = P_CAN0_RX, .offset = 1},
224 {.res = P_CAN0_TX, .offset = 1},
225 {.res = P_SPI0_SSEL7, .offset = 1},
226 {.res = P_SPORT0_TFS, .offset = 0},
227 {.res = P_SPORT0_DTPRI, .offset = 0},
228 {.res = P_SPI0_SSEL2, .offset = 0},
229 {.res = P_SPI0_SSEL3, .offset = 0},
c58c2140
MH		 230};
231
f556309e 232static void portmux_setup(unsigned short per)
c58c2140 233{
8c613623 234 u16 y, offset, muxreg;
f556309e 235 u16 function = P_FUNCT2MUX(per);
c58c2140 236
8c613623
MH		 237 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
238 if (port_mux_lut[y].res == per) {
c58c2140
MH		 239
240 /* SET PORTMUX REG */
241
8c613623 242 offset = port_mux_lut[y].offset;
c58c2140
MH		 243 muxreg = bfin_read_PORT_MUX();
244
d171c233 245 if (offset != 1)
c58c2140 246 muxreg &= ~(1 << offset);
d171c233 247 else
c58c2140 248 muxreg &= ~(3 << 1);
c58c2140
MH		 249
250 muxreg |= (function << offset);
251 bfin_write_PORT_MUX(muxreg);
252 }
253 }
254}
269647dc 255#elif defined(CONFIG_BF54x)
f556309e 256inline void portmux_setup(unsigned short per)
d2b11a46
MH		 257{
258 u32 pmux;
f556309e
MF		 259 u16 ident = P_IDENT(per);
260 u16 function = P_FUNCT2MUX(per);
d2b11a46 261
f556309e 262 pmux = gpio_array[gpio_bank(ident)]->port_mux;
d2b11a46 263
f556309e
MF		 264 pmux &= ~(0x3 << (2 * gpio_sub_n(ident)));
265 pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
d2b11a46 266
f556309e 267 gpio_array[gpio_bank(ident)]->port_mux = pmux;
d2b11a46
MH		 268}
269
f556309e 270inline u16 get_portmux(unsigned short per)
d2b11a46
MH		 271{
272 u32 pmux;
f556309e 273 u16 ident = P_IDENT(per);
c58c2140 274
f556309e 275 pmux = gpio_array[gpio_bank(ident)]->port_mux;
d2b11a46 276
f556309e 277 return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
d2b11a46 278}
269647dc 279#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e 280inline void portmux_setup(unsigned short per)
59003145 281{
f556309e 282 u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per);
59003145
MH		 283 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
284
285 pmux = *port_mux[gpio_bank(ident)];
286 pmux &= ~(3 << offset);
287 pmux |= (function & 3) << offset;
288 *port_mux[gpio_bank(ident)] = pmux;
289 SSYNC();
290}
c58c2140
MH		 291#else
292# define portmux_setup(...) do { } while (0)
293#endif
1394f032 294
269647dc 295#ifndef CONFIG_BF54x
1394f032
BW		 296/***********************************************************
297*
298* FUNCTIONS: Blackfin General Purpose Ports Access Functions
299*
300* INPUTS/OUTPUTS:
301* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
302*
303*
304* DESCRIPTION: These functions abstract direct register access
305* to Blackfin processor General Purpose
306* Ports Regsiters
307*
308* CAUTION: These functions do not belong to the GPIO Driver API
309*************************************************************
310* MODIFICATION HISTORY :
311**************************************************************/
312
313/* Set a specific bit */
314
315#define SET_GPIO(name) \
a2c8cfef 316void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032
BW		 317{ \
318 unsigned long flags; \
6a01f230 319 local_irq_save_hw(flags); \
1394f032 320 if (arg) \
f556309e 321 gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
1394f032 322 else \
f556309e 323 gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
2b39331a 324 AWA_DUMMY_READ(name); \
6a01f230 325 local_irq_restore_hw(flags); \
1394f032
BW		 326} \
327EXPORT_SYMBOL(set_gpio_ ## name);
328
f556309e
MF		 329SET_GPIO(dir) /* set_gpio_dir() */
330SET_GPIO(inen) /* set_gpio_inen() */
331SET_GPIO(polar) /* set_gpio_polar() */
332SET_GPIO(edge) /* set_gpio_edge() */
333SET_GPIO(both) /* set_gpio_both() */
1394f032
BW		 334
335
2b39331a 336#define SET_GPIO_SC(name) \
a2c8cfef 337void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH		 338{ \
339 unsigned long flags; \
f556309e
MF		 340 if (ANOMALY_05000311 || ANOMALY_05000323) \
341 local_irq_save_hw(flags); \
1394f032 342 if (arg) \
f556309e 343 gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
1394f032 344 else \
f556309e
MF		 345 gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
346 if (ANOMALY_05000311 || ANOMALY_05000323) { \
347 AWA_DUMMY_READ(name); \
348 local_irq_restore_hw(flags); \
349 } \
1394f032
BW		 350} \
351EXPORT_SYMBOL(set_gpio_ ## name);
352
353SET_GPIO_SC(maska)
354SET_GPIO_SC(maskb)
1394f032 355SET_GPIO_SC(data)
1394f032 356
a2c8cfef 357void set_gpio_toggle(unsigned gpio)
1394f032
BW		 358{
359 unsigned long flags;
f556309e
MF		 360 if (ANOMALY_05000311 || ANOMALY_05000323)
361 local_irq_save_hw(flags);
362 gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
363 if (ANOMALY_05000311 || ANOMALY_05000323) {
364 AWA_DUMMY_READ(toggle);
365 local_irq_restore_hw(flags);
366 }
1394f032 367}
1394f032
BW		 368EXPORT_SYMBOL(set_gpio_toggle);
369
370
371/*Set current PORT date (16-bit word)*/
372
373#define SET_GPIO_P(name) \
a2c8cfef 374void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
1394f032 375{ \
2b39331a 376 unsigned long flags; \
f556309e
MF		 377 if (ANOMALY_05000311 || ANOMALY_05000323) \
378 local_irq_save_hw(flags); \
379 gpio_array[gpio_bank(gpio)]->name = arg; \
380 if (ANOMALY_05000311 || ANOMALY_05000323) { \
381 AWA_DUMMY_READ(name); \
382 local_irq_restore_hw(flags); \
383 } \
2b39331a
MH		 384} \
385EXPORT_SYMBOL(set_gpiop_ ## name);
1394f032 386
2b39331a 387SET_GPIO_P(data)
1394f032
BW		 388SET_GPIO_P(dir)
389SET_GPIO_P(inen)
390SET_GPIO_P(polar)
391SET_GPIO_P(edge)
392SET_GPIO_P(both)
393SET_GPIO_P(maska)
394SET_GPIO_P(maskb)
395
1394f032 396/* Get a specific bit */
2b39331a 397#define GET_GPIO(name) \
a2c8cfef 398unsigned short get_gpio_ ## name(unsigned gpio) \
2b39331a
MH		 399{ \
400 unsigned long flags; \
401 unsigned short ret; \
f556309e
MF		 402 if (ANOMALY_05000311 || ANOMALY_05000323) \
403 local_irq_save_hw(flags); \
404 ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
405 if (ANOMALY_05000311 || ANOMALY_05000323) { \
406 AWA_DUMMY_READ(name); \
407 local_irq_restore_hw(flags); \
408 } \
2b39331a
MH		 409 return ret; \
410} \
411EXPORT_SYMBOL(get_gpio_ ## name);
1394f032 412
2b39331a 413GET_GPIO(data)
1394f032
BW		 414GET_GPIO(dir)
415GET_GPIO(inen)
416GET_GPIO(polar)
417GET_GPIO(edge)
418GET_GPIO(both)
419GET_GPIO(maska)
420GET_GPIO(maskb)
421
1394f032
BW		 422/*Get current PORT date (16-bit word)*/
423
2b39331a 424#define GET_GPIO_P(name) \
a2c8cfef 425unsigned short get_gpiop_ ## name(unsigned gpio) \
2b39331a
MH		 426{ \
427 unsigned long flags; \
428 unsigned short ret; \
f556309e
MF		 429 if (ANOMALY_05000311 || ANOMALY_05000323) \
430 local_irq_save_hw(flags); \
431 ret = (gpio_array[gpio_bank(gpio)]->name); \
432 if (ANOMALY_05000311 || ANOMALY_05000323) { \
433 AWA_DUMMY_READ(name); \
434 local_irq_restore_hw(flags); \
435 } \
2b39331a
MH		 436 return ret; \
437} \
438EXPORT_SYMBOL(get_gpiop_ ## name);
1394f032 439
2b39331a 440GET_GPIO_P(data)
1394f032
BW		 441GET_GPIO_P(dir)
442GET_GPIO_P(inen)
443GET_GPIO_P(polar)
444GET_GPIO_P(edge)
445GET_GPIO_P(both)
446GET_GPIO_P(maska)
447GET_GPIO_P(maskb)
448
1394f032
BW		 449
450#ifdef CONFIG_PM
f556309e
MF		 451
452static unsigned short wakeup_map[GPIO_BANK_NUM];
453static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
454
455static const unsigned int sic_iwr_irqs[] = {
456#if defined(BF533_FAMILY)
457 IRQ_PROG_INTB
458#elif defined(BF537_FAMILY)
459 IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX
460#elif defined(BF538_FAMILY)
461 IRQ_PORTF_INTB
269647dc 462#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e
MF		 463 IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB
464#elif defined(BF561_FAMILY)
465 IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB
466#else
467# error no SIC_IWR defined
468#endif
469};
470
1394f032
BW		 471/***********************************************************
472*
473* FUNCTIONS: Blackfin PM Setup API
474*
475* INPUTS/OUTPUTS:
476* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
477* type -
478* PM_WAKE_RISING
479* PM_WAKE_FALLING
480* PM_WAKE_HIGH
481* PM_WAKE_LOW
482* PM_WAKE_BOTH_EDGES
483*
484* DESCRIPTION: Blackfin PM Driver API
485*
486* CAUTION:
487*************************************************************
488* MODIFICATION HISTORY :
489**************************************************************/
a2c8cfef 490int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
1394f032
BW		 491{
492 unsigned long flags;
493
494 if ((check_gpio(gpio) < 0) || !type)
495 return -EINVAL;
496
6a01f230 497 local_irq_save_hw(flags);
1394f032
BW		 498 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
499 wakeup_flags_map[gpio] = type;
6a01f230 500 local_irq_restore_hw(flags);
1394f032
BW		 501
502 return 0;
503}
504EXPORT_SYMBOL(gpio_pm_wakeup_request);
505
a2c8cfef 506void gpio_pm_wakeup_free(unsigned gpio)
1394f032
BW		 507{
508 unsigned long flags;
509
510 if (check_gpio(gpio) < 0)
511 return;
512
6a01f230 513 local_irq_save_hw(flags);
1394f032
BW		 514
515 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
516
6a01f230 517 local_irq_restore_hw(flags);
1394f032
BW		 518}
519EXPORT_SYMBOL(gpio_pm_wakeup_free);
520
a2c8cfef 521static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
1394f032
BW		 522{
523 port_setup(gpio, GPIO_USAGE);
524 set_gpio_dir(gpio, 0);
525 set_gpio_inen(gpio, 1);
526
527 if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
528 set_gpio_edge(gpio, 1);
529 else
530 set_gpio_edge(gpio, 0);
531
532 if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
533 set_gpio_both(gpio, 1);
534 else
535 set_gpio_both(gpio, 0);
536
537 if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
538 set_gpio_polar(gpio, 1);
539 else
540 set_gpio_polar(gpio, 0);
541
542 SSYNC();
543
544 return 0;
545}
546
1efc80b5 547u32 bfin_pm_standby_setup(void)
1394f032 548{
1394f032
BW		 549 u16 bank, mask, i, gpio;
550
1f83b8f1 551 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 552 mask = wakeup_map[gpio_bank(i)];
553 bank = gpio_bank(i);
554
f556309e
MF		 555 gpio_bank_saved[bank].maskb = gpio_array[bank]->maskb;
556 gpio_array[bank]->maskb = 0;
1394f032
BW		 557
558 if (mask) {
269647dc 559#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
1394f032
BW		 560 gpio_bank_saved[bank].fer = *port_fer[bank];
561#endif
f556309e
MF		 562 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
563 gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
564 gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
565 gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
566 gpio_bank_saved[bank].both = gpio_array[bank]->both;
c58c2140
MH		 567 gpio_bank_saved[bank].reserved =
568 reserved_gpio_map[bank];
1394f032
BW		 569
570 gpio = i;
571
572 while (mask) {
cfefe3c6
MH		 573 if ((mask & 1) && (wakeup_flags_map[gpio] !=
574 PM_WAKE_IGNORE)) {
c58c2140 575 reserved_gpio_map[gpio_bank(gpio)] |=
581d62ab
MH		 576 gpio_bit(gpio);
577 bfin_gpio_wakeup_type(gpio,
578 wakeup_flags_map[gpio]);
1394f032
BW		 579 set_gpio_data(gpio, 0); /*Clear*/
580 }
581 gpio++;
582 mask >>= 1;
583 }
584
cfefe3c6 585 bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
f556309e 586 gpio_array[bank]->maskb_set = wakeup_map[gpio_bank(i)];
1394f032
BW		 587 }
588 }
589
2b39331a
MH		 590 AWA_DUMMY_READ(maskb_set);
591
cfefe3c6 592 return 0;
1394f032
BW		 593}
594
1efc80b5 595void bfin_pm_standby_restore(void)
1394f032
BW		 596{
597 u16 bank, mask, i;
598
1f83b8f1 599 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 600 mask = wakeup_map[gpio_bank(i)];
601 bank = gpio_bank(i);
602
603 if (mask) {
269647dc 604#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
1394f032
BW		 605 *port_fer[bank] = gpio_bank_saved[bank].fer;
606#endif
f556309e
MF		 607 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
608 gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
609 gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
610 gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
611 gpio_array[bank]->both = gpio_bank_saved[bank].both;
581d62ab 612
c58c2140
MH		 613 reserved_gpio_map[bank] =
614 gpio_bank_saved[bank].reserved;
cfefe3c6 615 bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
1394f032
BW		 616 }
617
f556309e 618 gpio_array[bank]->maskb = gpio_bank_saved[bank].maskb;
1394f032 619 }
2b39331a 620 AWA_DUMMY_READ(maskb);
1394f032
BW		 621}
622
1efc80b5
MH		 623void bfin_gpio_pm_hibernate_suspend(void)
624{
625 int i, bank;
626
627 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
628 bank = gpio_bank(i);
629
269647dc 630#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
f556309e 631 gpio_bank_saved[bank].fer = *port_fer[bank];
269647dc 632#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e 633 gpio_bank_saved[bank].mux = *port_mux[bank];
1efc80b5 634#else
f556309e
MF		 635 if (bank == 0)
636 gpio_bank_saved[bank].mux = bfin_read_PORT_MUX();
1efc80b5
MH		 637#endif
638#endif
f556309e
MF		 639 gpio_bank_saved[bank].data = gpio_array[bank]->data;
640 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
641 gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
642 gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
643 gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
644 gpio_bank_saved[bank].both = gpio_array[bank]->both;
645 gpio_bank_saved[bank].maska = gpio_array[bank]->maska;
1efc80b5
MH		 646 }
647
648 AWA_DUMMY_READ(maska);
649}
650
651void bfin_gpio_pm_hibernate_restore(void)
652{
653 int i, bank;
654
655 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
f556309e 656 bank = gpio_bank(i);
1efc80b5 657
269647dc
MF		 658#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
659#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e 660 *port_mux[bank] = gpio_bank_saved[bank].mux;
1efc80b5 661#else
f556309e
MF		 662 if (bank == 0)
663 bfin_write_PORT_MUX(gpio_bank_saved[bank].mux);
1efc80b5 664#endif
f556309e 665 *port_fer[bank] = gpio_bank_saved[bank].fer;
1efc80b5 666#endif
f556309e 667 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
c03c2a87
MH		 668 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
669 & gpio_bank_saved[bank].dir;
f556309e
MF		 670 gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
671 gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
672 gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
673 gpio_array[bank]->both = gpio_bank_saved[bank].both;
f556309e 674 gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
1efc80b5
MH		 675 }
676 AWA_DUMMY_READ(maska);
677}
678
679
1394f032 680#endif
269647dc 681#else /* CONFIG_BF54x */
1efc80b5
MH		 682#ifdef CONFIG_PM
683
684u32 bfin_pm_standby_setup(void)
685{
686 return 0;
687}
688
689void bfin_pm_standby_restore(void)
690{
691
692}
693
694void bfin_gpio_pm_hibernate_suspend(void)
695{
696 int i, bank;
697
698 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
699 bank = gpio_bank(i);
700
f556309e
MF		 701 gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer;
702 gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux;
703 gpio_bank_saved[bank].data = gpio_array[bank]->data;
f556309e
MF		 704 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
705 gpio_bank_saved[bank].dir = gpio_array[bank]->dir_set;
1efc80b5
MH		 706 }
707}
708
709void bfin_gpio_pm_hibernate_restore(void)
710{
711 int i, bank;
712
713 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
f556309e
MF		 714 bank = gpio_bank(i);
715
716 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
717 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
718 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
719 gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
720 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
721 | gpio_bank_saved[bank].dir;
1efc80b5
MH		 722 }
723}
724#endif
fac3cf43 725
a2c8cfef 726unsigned short get_gpio_dir(unsigned gpio)
fac3cf43 727{
f556309e 728 return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)));
fac3cf43
MH		 729}
730EXPORT_SYMBOL(get_gpio_dir);
731
269647dc 732#endif /* CONFIG_BF54x */
1394f032 733
d2b11a46
MH		 734/***********************************************************
735*
736* FUNCTIONS: Blackfin Peripheral Resource Allocation
737* and PortMux Setup
738*
739* INPUTS/OUTPUTS:
740* per Peripheral Identifier
741* label String
742*
743* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
744*
745* CAUTION:
746*************************************************************
747* MODIFICATION HISTORY :
748**************************************************************/
749
d2b11a46
MH		 750int peripheral_request(unsigned short per, const char *label)
751{
752 unsigned long flags;
753 unsigned short ident = P_IDENT(per);
754
755 /*
756 * Don't cares are pins with only one dedicated function
757 */
c58c2140 758
d2b11a46
MH		 759 if (per & P_DONTCARE)
760 return 0;
761
762 if (!(per & P_DEFINED))
763 return -ENODEV;
764
6a01f230 765 local_irq_save_hw(flags);
d2b11a46 766
6a87d29b
MF		 767 /* If a pin can be muxed as either GPIO or peripheral, make
768 * sure it is not already a GPIO pin when we request it.
769 */
770 if (unlikely(!check_gpio(ident) &&
771 reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
d6879c58
RG		 772 if (system_state == SYSTEM_BOOTING)
773 dump_stack();
d2b11a46 774 printk(KERN_ERR
6c7ec0ec 775 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
b85d858b 776 __func__, ident, get_label(ident));
6a01f230 777 local_irq_restore_hw(flags);
d2b11a46
MH		 778 return -EBUSY;
779 }
780
781 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
782
d171c233
MF		 783 /*
784 * Pin functions like AMC address strobes my
785 * be requested and used by several drivers
786 */
d2b11a46 787
269647dc 788#ifdef CONFIG_BF54x
f556309e 789 if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
6c7ec0ec
MF		 790#else
791 if (!(per & P_MAYSHARE)) {
792#endif
d171c233
MF		 793 /*
794 * Allow that the identical pin function can
795 * be requested from the same driver twice
796 */
d2b11a46 797
d171c233
MF		 798 if (cmp_label(ident, label) == 0)
799 goto anyway;
d2b11a46 800
d6879c58
RG		 801 if (system_state == SYSTEM_BOOTING)
802 dump_stack();
d2b11a46
MH		 803 printk(KERN_ERR
804 "%s: Peripheral %d function %d is already reserved by %s !\n",
b85d858b 805 __func__, ident, P_FUNCT2MUX(per), get_label(ident));
6a01f230 806 local_irq_restore_hw(flags);
d2b11a46
MH		 807 return -EBUSY;
808 }
809 }
810
d171c233 811 anyway:
d2b11a46
MH		 812 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
813
f556309e 814 portmux_setup(per);
c58c2140
MH		 815 port_setup(ident, PERIPHERAL_USAGE);
816
6a01f230 817 local_irq_restore_hw(flags);
c58c2140
MH		 818 set_label(ident, label);
819
820 return 0;
821}
822EXPORT_SYMBOL(peripheral_request);
823
68179371 824int peripheral_request_list(const unsigned short per[], const char *label)
c58c2140
MH		 825{
826 u16 cnt;
827 int ret;
828
829 for (cnt = 0; per[cnt] != 0; cnt++) {
314c98d5 830
c58c2140 831 ret = peripheral_request(per[cnt], label);
314c98d5
MH		 832
833 if (ret < 0) {
d171c233 834 for ( ; cnt > 0; cnt--)
314c98d5 835 peripheral_free(per[cnt - 1]);
d171c233
MF		 836
837 return ret;
314c98d5 838 }
c58c2140
MH		 839 }
840
841 return 0;
842}
843EXPORT_SYMBOL(peripheral_request_list);
844
845void peripheral_free(unsigned short per)
846{
847 unsigned long flags;
848 unsigned short ident = P_IDENT(per);
849
850 if (per & P_DONTCARE)
851 return;
852
853 if (!(per & P_DEFINED))
854 return;
855
6a01f230 856 local_irq_save_hw(flags);
c58c2140 857
d171c233 858 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
6a01f230 859 local_irq_restore_hw(flags);
c58c2140
MH		 860 return;
861 }
862
d171c233 863 if (!(per & P_MAYSHARE))
c58c2140 864 port_setup(ident, GPIO_USAGE);
c58c2140
MH		 865
866 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
867
2acde902
MH		 868 set_label(ident, "free");
869
6a01f230 870 local_irq_restore_hw(flags);
c58c2140
MH		 871}
872EXPORT_SYMBOL(peripheral_free);
873
68179371 874void peripheral_free_list(const unsigned short per[])
c58c2140
MH		 875{
876 u16 cnt;
d171c233 877 for (cnt = 0; per[cnt] != 0; cnt++)
c58c2140 878 peripheral_free(per[cnt]);
c58c2140
MH		 879}
880EXPORT_SYMBOL(peripheral_free_list);
881
1394f032
BW		 882/***********************************************************
883*
884* FUNCTIONS: Blackfin GPIO Driver
885*
886* INPUTS/OUTPUTS:
d2b11a46
MH		 887* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
888* label String
1394f032
BW		 889*
890* DESCRIPTION: Blackfin GPIO Driver API
891*
892* CAUTION:
893*************************************************************
894* MODIFICATION HISTORY :
895**************************************************************/
896
a4f0b32c 897int bfin_gpio_request(unsigned gpio, const char *label)
1394f032
BW		 898{
899 unsigned long flags;
900
901 if (check_gpio(gpio) < 0)
902 return -EINVAL;
903
6a01f230 904 local_irq_save_hw(flags);
1394f032 905
2acde902
MH		 906 /*
907 * Allow that the identical GPIO can
908 * be requested from the same driver twice
909 * Do nothing and return -
910 */
911
912 if (cmp_label(gpio, label) == 0) {
6a01f230 913 local_irq_restore_hw(flags);
2acde902
MH		 914 return 0;
915 }
916
c58c2140 917 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
d6879c58
RG		 918 if (system_state == SYSTEM_BOOTING)
919 dump_stack();
d2b11a46 920 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
9570ff4a 921 gpio, get_label(gpio));
6a01f230 922 local_irq_restore_hw(flags);
d2b11a46
MH		 923 return -EBUSY;
924 }
925 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
d6879c58
RG		 926 if (system_state == SYSTEM_BOOTING)
927 dump_stack();
d2b11a46
MH		 928 printk(KERN_ERR
929 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
930 gpio, get_label(gpio));
6a01f230 931 local_irq_restore_hw(flags);
1394f032
BW		 932 return -EBUSY;
933 }
a2be3931 934 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
9570ff4a
GY		 935 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
936 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
a2be3931 937 }
269647dc 938#ifndef CONFIG_BF54x
a2be3931
MH		 939 else { /* Reset POLAR setting when acquiring a gpio for the first time */
940 set_gpio_polar(gpio, 0);
941 }
942#endif
d2b11a46 943
c58c2140 944 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
9570ff4a 945 set_label(gpio, label);
1394f032 946
6a01f230 947 local_irq_restore_hw(flags);
1394f032
BW		 948
949 port_setup(gpio, GPIO_USAGE);
950
951 return 0;
952}
a4f0b32c 953EXPORT_SYMBOL(bfin_gpio_request);
1394f032 954
a4f0b32c 955void bfin_gpio_free(unsigned gpio)
1394f032
BW		 956{
957 unsigned long flags;
958
959 if (check_gpio(gpio) < 0)
960 return;
961
45c4f2a0
UKK		 962 might_sleep();
963
6a01f230 964 local_irq_save_hw(flags);
1394f032 965
c58c2140 966 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
d6879c58
RG		 967 if (system_state == SYSTEM_BOOTING)
968 dump_stack();
f85c4abd 969 gpio_error(gpio);
6a01f230 970 local_irq_restore_hw(flags);
1394f032
BW		 971 return;
972 }
973
c58c2140 974 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1394f032 975
2acde902
MH		 976 set_label(gpio, "free");
977
6a01f230 978 local_irq_restore_hw(flags);
1394f032 979}
a4f0b32c 980EXPORT_SYMBOL(bfin_gpio_free);
1394f032 981
9570ff4a
GY		 982int bfin_gpio_irq_request(unsigned gpio, const char *label)
983{
984 unsigned long flags;
985
986 if (check_gpio(gpio) < 0)
987 return -EINVAL;
988
6a01f230 989 local_irq_save_hw(flags);
9570ff4a 990
9570ff4a 991 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
d6879c58
RG		 992 if (system_state == SYSTEM_BOOTING)
993 dump_stack();
9570ff4a
GY		 994 printk(KERN_ERR
995 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
996 gpio, get_label(gpio));
6a01f230 997 local_irq_restore_hw(flags);
9570ff4a
GY		 998 return -EBUSY;
999 }
1000 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))
1001 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
1002 "(Documentation/blackfin/bfin-gpio-notes.txt)\n",
1003 gpio, get_label(gpio));
1004
1005 reserved_gpio_irq_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1006 set_label(gpio, label);
1007
6a01f230 1008 local_irq_restore_hw(flags);
9570ff4a
GY		 1009
1010 port_setup(gpio, GPIO_USAGE);
1011
1012 return 0;
1013}
1014
1015void bfin_gpio_irq_free(unsigned gpio)
1016{
1017 unsigned long flags;
1018
1019 if (check_gpio(gpio) < 0)
1020 return;
1021
6a01f230 1022 local_irq_save_hw(flags);
9570ff4a
GY		 1023
1024 if (unlikely(!(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
d6879c58
RG		 1025 if (system_state == SYSTEM_BOOTING)
1026 dump_stack();
9570ff4a 1027 gpio_error(gpio);
6a01f230 1028 local_irq_restore_hw(flags);
9570ff4a
GY		 1029 return;
1030 }
1031
1032 reserved_gpio_irq_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1033
1034 set_label(gpio, "free");
1035
6a01f230 1036 local_irq_restore_hw(flags);
9570ff4a
GY		 1037}
1038
f556309e
MF		 1039static inline void __bfin_gpio_direction_input(unsigned gpio)
1040{
269647dc 1041#ifdef CONFIG_BF54x
f556309e
MF		 1042 gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
1043#else
1044 gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1045#endif
1046 gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
1047}
1048
a4f0b32c 1049int bfin_gpio_direction_input(unsigned gpio)
d2b11a46
MH		 1050{
1051 unsigned long flags;
1052
acbcd263
MH		 1053 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1054 gpio_error(gpio);
1055 return -EINVAL;
1056 }
1057
6a01f230 1058 local_irq_save_hw(flags);
f556309e
MF		 1059 __bfin_gpio_direction_input(gpio);
1060 AWA_DUMMY_READ(inen);
6a01f230 1061 local_irq_restore_hw(flags);
acbcd263
MH		 1062
1063 return 0;
d2b11a46 1064}
a4f0b32c 1065EXPORT_SYMBOL(bfin_gpio_direction_input);
d2b11a46 1066
f556309e 1067void bfin_gpio_irq_prepare(unsigned gpio)
d2b11a46 1068{
269647dc 1069#ifdef CONFIG_BF54x
d2b11a46 1070 unsigned long flags;
f556309e 1071#endif
d2b11a46 1072
f556309e 1073 port_setup(gpio, GPIO_USAGE);
d2b11a46 1074
269647dc 1075#ifdef CONFIG_BF54x
6a01f230 1076 local_irq_save_hw(flags);
f556309e 1077 __bfin_gpio_direction_input(gpio);
6a01f230 1078 local_irq_restore_hw(flags);
f556309e 1079#endif
d2b11a46 1080}
d2b11a46 1081
a4f0b32c 1082void bfin_gpio_set_value(unsigned gpio, int arg)
d2b11a46
MH		 1083{
1084 if (arg)
f556309e 1085 gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
d2b11a46 1086 else
f556309e 1087 gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
d2b11a46 1088}
a4f0b32c 1089EXPORT_SYMBOL(bfin_gpio_set_value);
d2b11a46 1090
f556309e 1091int bfin_gpio_direction_output(unsigned gpio, int value)
affee2b2
MH		 1092{
1093 unsigned long flags;
1094
f556309e
MF		 1095 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1096 gpio_error(gpio);
1097 return -EINVAL;
1098 }
affee2b2 1099
6a01f230 1100 local_irq_save_hw(flags);
affee2b2 1101
f556309e
MF		 1102 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1103 gpio_set_value(gpio, value);
269647dc 1104#ifdef CONFIG_BF54x
f556309e 1105 gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
d2b11a46 1106#else
f556309e
MF		 1107 gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
1108#endif
1109
1110 AWA_DUMMY_READ(dir);
1111 local_irq_restore_hw(flags);
1112
1113 return 0;
1114}
1115EXPORT_SYMBOL(bfin_gpio_direction_output);
d2b11a46 1116
a4f0b32c 1117int bfin_gpio_get_value(unsigned gpio)
803a8d2a 1118{
269647dc 1119#ifdef CONFIG_BF54x
f556309e
MF		 1120 return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
1121#else
803a8d2a 1122 unsigned long flags;
803a8d2a
MH		 1123
1124 if (unlikely(get_gpio_edge(gpio))) {
f556309e 1125 int ret;
6a01f230 1126 local_irq_save_hw(flags);
803a8d2a
MH		 1127 set_gpio_edge(gpio, 0);
1128 ret = get_gpio_data(gpio);
1129 set_gpio_edge(gpio, 1);
6a01f230 1130 local_irq_restore_hw(flags);
803a8d2a
MH		 1131 return ret;
1132 } else
1133 return get_gpio_data(gpio);
f556309e 1134#endif
803a8d2a 1135}
a4f0b32c 1136EXPORT_SYMBOL(bfin_gpio_get_value);
803a8d2a 1137
168f1212
MF		 1138/* If we are booting from SPI and our board lacks a strong enough pull up,
1139 * the core can reset and execute the bootrom faster than the resistor can
1140 * pull the signal logically high. To work around this (common) error in
1141 * board design, we explicitly set the pin back to GPIO mode, force /CS
1142 * high, and wait for the electrons to do their thing.
1143 *
1144 * This function only makes sense to be called from reset code, but it
1145 * lives here as we need to force all the GPIO states w/out going through
1146 * BUG() checks and such.
1147 */
b52dae31 1148void bfin_reset_boot_spi_cs(unsigned short pin)
168f1212 1149{
b52dae31 1150 unsigned short gpio = P_IDENT(pin);
4d5f4ed3 1151 port_setup(gpio, GPIO_USAGE);
f556309e 1152 gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
a2c8cfef 1153 AWA_DUMMY_READ(data_set);
168f1212
MF		 1154 udelay(1);
1155}
d2b11a46 1156
1545a111
MF		 1157#if defined(CONFIG_PROC_FS)
1158static int gpio_proc_read(char *buf, char **start, off_t offset,
1159 int len, int *unused_i, void *unused_v)
1160{
9570ff4a 1161 int c, irq, gpio, outlen = 0;
1545a111
MF		 1162
1163 for (c = 0; c < MAX_RESOURCES; c++) {
9570ff4a
GY		 1164 irq = reserved_gpio_irq_map[gpio_bank(c)] & gpio_bit(c);
1165 gpio = reserved_gpio_map[gpio_bank(c)] & gpio_bit(c);
1166 if (!check_gpio(c) && (gpio || irq))
1167 len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
1168 get_label(c), (gpio && irq) ? " *" : "",
1169 get_gpio_dir(c) ? "OUTPUT" : "INPUT");
1545a111 1170 else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
8eb3e3bf 1171 len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
1545a111
MF		 1172 else
1173 continue;
1174 buf += len;
1175 outlen += len;
1176 }
1177 return outlen;
1178}
1179
1180static __init int gpio_register_proc(void)
1181{
1182 struct proc_dir_entry *proc_gpio;
1183
1184 proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
1185 if (proc_gpio)
1186 proc_gpio->read_proc = gpio_proc_read;
1187 return proc_gpio != NULL;
1188}
1545a111
MF		 1189__initcall(gpio_register_proc);
1190#endif
a4f0b32c
MH		 1191
1192#ifdef CONFIG_GPIOLIB
1193int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio)
1194{
1195 return bfin_gpio_direction_input(gpio);
1196}
1197
1198int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
1199{
1200 return bfin_gpio_direction_output(gpio, level);
1201}
1202
1203int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio)
1204{
1205 return bfin_gpio_get_value(gpio);
1206}
1207
1208void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1209{
a4f0b32c 1210 return bfin_gpio_set_value(gpio, value);
a4f0b32c
MH		 1211}
1212
1213int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio)
1214{
1215 return bfin_gpio_request(gpio, chip->label);
1216}
1217
1218void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio)
1219{
1220 return bfin_gpio_free(gpio);
1221}
1222
1223static struct gpio_chip bfin_chip = {
1224 .label = "Blackfin-GPIOlib",
1225 .direction_input = bfin_gpiolib_direction_input,
1226 .get = bfin_gpiolib_get_value,
1227 .direction_output = bfin_gpiolib_direction_output,
1228 .set = bfin_gpiolib_set_value,
1229 .request = bfin_gpiolib_gpio_request,
1230 .free = bfin_gpiolib_gpio_free,
1231 .base = 0,
1232 .ngpio = MAX_BLACKFIN_GPIOS,
1233};
1234
1235static int __init bfin_gpiolib_setup(void)
1236{
1237 return gpiochip_add(&bfin_chip);
1238}
1239arch_initcall(bfin_gpiolib_setup);
1240#endif
Linux kernel - Deliverables
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