Blackfin: make sure mmiowb inserts a write barrier with SSYNC
[deliverable/linux.git] / arch / blackfin / kernel / bfin_gpio.c
CommitLineData
1394f032 1/*
96f1050d 2 * GPIO Abstraction Layer
1394f032 3 *
96f1050d 4 * Copyright 2006-2009 Analog Devices Inc.
1394f032 5 *
96f1050d 6 * Licensed under the GPL-2 or later
1394f032
BW
7 */
8
168f1212 9#include <linux/delay.h>
1394f032
BW
10#include <linux/module.h>
11#include <linux/err.h>
1545a111 12#include <linux/proc_fs.h>
1394f032
BW
13#include <asm/blackfin.h>
14#include <asm/gpio.h>
c58c2140 15#include <asm/portmux.h>
1394f032
BW
16#include <linux/irq.h>
17
2b39331a
MH
18#if ANOMALY_05000311 || ANOMALY_05000323
19enum {
20 AWA_data = SYSCR,
21 AWA_data_clear = SYSCR,
22 AWA_data_set = SYSCR,
23 AWA_toggle = SYSCR,
6ed83942
GY
24 AWA_maska = BFIN_UART_SCR,
25 AWA_maska_clear = BFIN_UART_SCR,
26 AWA_maska_set = BFIN_UART_SCR,
27 AWA_maska_toggle = BFIN_UART_SCR,
28 AWA_maskb = BFIN_UART_GCTL,
29 AWA_maskb_clear = BFIN_UART_GCTL,
30 AWA_maskb_set = BFIN_UART_GCTL,
31 AWA_maskb_toggle = BFIN_UART_GCTL,
2b39331a
MH
32 AWA_dir = SPORT1_STAT,
33 AWA_polar = SPORT1_STAT,
34 AWA_edge = SPORT1_STAT,
35 AWA_both = SPORT1_STAT,
36#if ANOMALY_05000311
37 AWA_inen = TIMER_ENABLE,
38#elif ANOMALY_05000323
39 AWA_inen = DMA1_1_CONFIG,
40#endif
41};
42 /* Anomaly Workaround */
43#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
44#else
45#define AWA_DUMMY_READ(...) do { } while (0)
46#endif
47
f556309e 48static struct gpio_port_t * const gpio_array[] = {
dc26aec2 49#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
1394f032 50 (struct gpio_port_t *) FIO_FLAG_D,
269647dc 51#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
1394f032
BW
52 (struct gpio_port_t *) PORTFIO,
53 (struct gpio_port_t *) PORTGIO,
54 (struct gpio_port_t *) PORTHIO,
f556309e
MF
55#elif defined(BF561_FAMILY)
56 (struct gpio_port_t *) FIO0_FLAG_D,
57 (struct gpio_port_t *) FIO1_FLAG_D,
58 (struct gpio_port_t *) FIO2_FLAG_D,
269647dc 59#elif defined(CONFIG_BF54x)
f556309e
MF
60 (struct gpio_port_t *)PORTA_FER,
61 (struct gpio_port_t *)PORTB_FER,
62 (struct gpio_port_t *)PORTC_FER,
63 (struct gpio_port_t *)PORTD_FER,
64 (struct gpio_port_t *)PORTE_FER,
65 (struct gpio_port_t *)PORTF_FER,
66 (struct gpio_port_t *)PORTG_FER,
67 (struct gpio_port_t *)PORTH_FER,
68 (struct gpio_port_t *)PORTI_FER,
69 (struct gpio_port_t *)PORTJ_FER,
70#else
71# error no gpio arrays defined
72#endif
1394f032
BW
73};
74
269647dc 75#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
f556309e 76static unsigned short * const port_fer[] = {
1394f032
BW
77 (unsigned short *) PORTF_FER,
78 (unsigned short *) PORTG_FER,
79 (unsigned short *) PORTH_FER,
80};
1394f032 81
f556309e
MF
82# if !defined(BF537_FAMILY)
83static unsigned short * const port_mux[] = {
59003145
MH
84 (unsigned short *) PORTF_MUX,
85 (unsigned short *) PORTG_MUX,
86 (unsigned short *) PORTH_MUX,
87};
88
89static const
0ce5eaf8 90u8 pmux_offset[][16] = {
269647dc 91# if defined(CONFIG_BF52x)
0ce5eaf8
GY
92 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
93 { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
94 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
269647dc 95# elif defined(CONFIG_BF51x)
0ce5eaf8
GY
96 { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */
97 { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */
98 { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */
99# endif
100};
f556309e 101# endif
0ce5eaf8 102
621dd247
MH
103#elif defined(BF538_FAMILY)
104static unsigned short * const port_fer[] = {
105 (unsigned short *) PORTCIO_FER,
106 (unsigned short *) PORTDIO_FER,
107 (unsigned short *) PORTEIO_FER,
108};
d2b11a46
MH
109#endif
110
8c613623
MH
111#define RESOURCE_LABEL_SIZE 16
112
fac3cf43 113static struct str_ident {
8c613623 114 char name[RESOURCE_LABEL_SIZE];
fac3cf43 115} str_ident[MAX_RESOURCES];
1394f032 116
1efc80b5 117#if defined(CONFIG_PM)
397861cd 118static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
59003145
MH
119#endif
120
74c04503 121static void gpio_error(unsigned gpio)
acbcd263
MH
122{
123 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
124}
125
c58c2140
MH
126static void set_label(unsigned short ident, const char *label)
127{
e9fae189 128 if (label) {
8c613623 129 strncpy(str_ident[ident].name, label,
c58c2140 130 RESOURCE_LABEL_SIZE);
8c613623 131 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
c58c2140
MH
132 }
133}
134
135static char *get_label(unsigned short ident)
136{
8c613623 137 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
c58c2140
MH
138}
139
140static int cmp_label(unsigned short ident, const char *label)
141{
fac3cf43
MH
142 if (label == NULL) {
143 dump_stack();
144 printk(KERN_ERR "Please provide none-null label\n");
145 }
146
e9fae189 147 if (label)
1f7d373f 148 return strcmp(str_ident[ident].name, label);
c58c2140
MH
149 else
150 return -EINVAL;
151}
152
332824b8
MF
153#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)]
154#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
155#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i))
156#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i))
157#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c]
158
159DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
160DECLARE_RESERVED_MAP(peri, gpio_bank(MAX_RESOURCES));
161DECLARE_RESERVED_MAP(gpio_irq, GPIO_BANK_NUM);
162
163inline int check_gpio(unsigned gpio)
164{
165#if defined(CONFIG_BF54x)
166 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
167 || gpio == GPIO_PH14 || gpio == GPIO_PH15
168 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
169 return -EINVAL;
170#endif
171 if (gpio >= MAX_BLACKFIN_GPIOS)
172 return -EINVAL;
173 return 0;
174}
175
a2c8cfef 176static void port_setup(unsigned gpio, unsigned short usage)
1394f032 177{
621dd247
MH
178#if defined(BF538_FAMILY)
179 /*
180 * BF538/9 Port C,D and E are special.
181 * Inverted PORT_FER polarity on CDE and no PORF_FER on F
182 * Regular PORT F GPIOs are handled here, CDE are exclusively
183 * managed by GPIOLIB
184 */
185
186 if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES)
187 return;
188
189 gpio -= MAX_BLACKFIN_GPIOS;
190
191 if (usage == GPIO_USAGE)
192 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
193 else
194 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
195 SSYNC();
196 return;
197#endif
198
a2d03a1d
MF
199 if (check_gpio(gpio))
200 return;
201
269647dc 202#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
a2d03a1d
MF
203 if (usage == GPIO_USAGE)
204 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
205 else
206 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
207 SSYNC();
269647dc 208#elif defined(CONFIG_BF54x)
d2b11a46
MH
209 if (usage == GPIO_USAGE)
210 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
211 else
212 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
213 SSYNC();
1394f032 214#endif
a2d03a1d 215}
1394f032 216
c58c2140 217#ifdef BF537_FAMILY
8c613623
MH
218static struct {
219 unsigned short res;
220 unsigned short offset;
221} port_mux_lut[] = {
222 {.res = P_PPI0_D13, .offset = 11},
223 {.res = P_PPI0_D14, .offset = 11},
224 {.res = P_PPI0_D15, .offset = 11},
225 {.res = P_SPORT1_TFS, .offset = 11},
226 {.res = P_SPORT1_TSCLK, .offset = 11},
227 {.res = P_SPORT1_DTPRI, .offset = 11},
228 {.res = P_PPI0_D10, .offset = 10},
229 {.res = P_PPI0_D11, .offset = 10},
230 {.res = P_PPI0_D12, .offset = 10},
231 {.res = P_SPORT1_RSCLK, .offset = 10},
232 {.res = P_SPORT1_RFS, .offset = 10},
233 {.res = P_SPORT1_DRPRI, .offset = 10},
234 {.res = P_PPI0_D8, .offset = 9},
235 {.res = P_PPI0_D9, .offset = 9},
236 {.res = P_SPORT1_DRSEC, .offset = 9},
237 {.res = P_SPORT1_DTSEC, .offset = 9},
238 {.res = P_TMR2, .offset = 8},
239 {.res = P_PPI0_FS3, .offset = 8},
240 {.res = P_TMR3, .offset = 7},
241 {.res = P_SPI0_SSEL4, .offset = 7},
242 {.res = P_TMR4, .offset = 6},
243 {.res = P_SPI0_SSEL5, .offset = 6},
244 {.res = P_TMR5, .offset = 5},
245 {.res = P_SPI0_SSEL6, .offset = 5},
246 {.res = P_UART1_RX, .offset = 4},
247 {.res = P_UART1_TX, .offset = 4},
248 {.res = P_TMR6, .offset = 4},
249 {.res = P_TMR7, .offset = 4},
250 {.res = P_UART0_RX, .offset = 3},
251 {.res = P_UART0_TX, .offset = 3},
252 {.res = P_DMAR0, .offset = 3},
253 {.res = P_DMAR1, .offset = 3},
254 {.res = P_SPORT0_DTSEC, .offset = 1},
255 {.res = P_SPORT0_DRSEC, .offset = 1},
256 {.res = P_CAN0_RX, .offset = 1},
257 {.res = P_CAN0_TX, .offset = 1},
258 {.res = P_SPI0_SSEL7, .offset = 1},
259 {.res = P_SPORT0_TFS, .offset = 0},
260 {.res = P_SPORT0_DTPRI, .offset = 0},
261 {.res = P_SPI0_SSEL2, .offset = 0},
262 {.res = P_SPI0_SSEL3, .offset = 0},
c58c2140
MH
263};
264
f556309e 265static void portmux_setup(unsigned short per)
c58c2140 266{
8c613623 267 u16 y, offset, muxreg;
f556309e 268 u16 function = P_FUNCT2MUX(per);
c58c2140 269
8c613623
MH
270 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
271 if (port_mux_lut[y].res == per) {
c58c2140
MH
272
273 /* SET PORTMUX REG */
274
8c613623 275 offset = port_mux_lut[y].offset;
c58c2140
MH
276 muxreg = bfin_read_PORT_MUX();
277
d171c233 278 if (offset != 1)
c58c2140 279 muxreg &= ~(1 << offset);
d171c233 280 else
c58c2140 281 muxreg &= ~(3 << 1);
c58c2140
MH
282
283 muxreg |= (function << offset);
284 bfin_write_PORT_MUX(muxreg);
285 }
286 }
287}
269647dc 288#elif defined(CONFIG_BF54x)
f556309e 289inline void portmux_setup(unsigned short per)
d2b11a46
MH
290{
291 u32 pmux;
f556309e
MF
292 u16 ident = P_IDENT(per);
293 u16 function = P_FUNCT2MUX(per);
d2b11a46 294
f556309e 295 pmux = gpio_array[gpio_bank(ident)]->port_mux;
d2b11a46 296
f556309e
MF
297 pmux &= ~(0x3 << (2 * gpio_sub_n(ident)));
298 pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
d2b11a46 299
f556309e 300 gpio_array[gpio_bank(ident)]->port_mux = pmux;
d2b11a46
MH
301}
302
f556309e 303inline u16 get_portmux(unsigned short per)
d2b11a46
MH
304{
305 u32 pmux;
f556309e 306 u16 ident = P_IDENT(per);
c58c2140 307
f556309e 308 pmux = gpio_array[gpio_bank(ident)]->port_mux;
d2b11a46 309
f556309e 310 return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
d2b11a46 311}
269647dc 312#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e 313inline void portmux_setup(unsigned short per)
59003145 314{
f556309e 315 u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per);
59003145
MH
316 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
317
318 pmux = *port_mux[gpio_bank(ident)];
319 pmux &= ~(3 << offset);
320 pmux |= (function & 3) << offset;
321 *port_mux[gpio_bank(ident)] = pmux;
322 SSYNC();
323}
c58c2140
MH
324#else
325# define portmux_setup(...) do { } while (0)
326#endif
1394f032 327
269647dc 328#ifndef CONFIG_BF54x
1394f032
BW
329/***********************************************************
330*
331* FUNCTIONS: Blackfin General Purpose Ports Access Functions
332*
333* INPUTS/OUTPUTS:
334* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
335*
336*
337* DESCRIPTION: These functions abstract direct register access
338* to Blackfin processor General Purpose
339* Ports Regsiters
340*
341* CAUTION: These functions do not belong to the GPIO Driver API
342*************************************************************
343* MODIFICATION HISTORY :
344**************************************************************/
345
346/* Set a specific bit */
347
348#define SET_GPIO(name) \
a2c8cfef 349void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032
BW
350{ \
351 unsigned long flags; \
6a01f230 352 local_irq_save_hw(flags); \
1394f032 353 if (arg) \
f556309e 354 gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
1394f032 355 else \
f556309e 356 gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
2b39331a 357 AWA_DUMMY_READ(name); \
6a01f230 358 local_irq_restore_hw(flags); \
1394f032
BW
359} \
360EXPORT_SYMBOL(set_gpio_ ## name);
361
f556309e
MF
362SET_GPIO(dir) /* set_gpio_dir() */
363SET_GPIO(inen) /* set_gpio_inen() */
364SET_GPIO(polar) /* set_gpio_polar() */
365SET_GPIO(edge) /* set_gpio_edge() */
366SET_GPIO(both) /* set_gpio_both() */
1394f032
BW
367
368
2b39331a 369#define SET_GPIO_SC(name) \
a2c8cfef 370void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH
371{ \
372 unsigned long flags; \
f556309e
MF
373 if (ANOMALY_05000311 || ANOMALY_05000323) \
374 local_irq_save_hw(flags); \
1394f032 375 if (arg) \
f556309e 376 gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
1394f032 377 else \
f556309e
MF
378 gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
379 if (ANOMALY_05000311 || ANOMALY_05000323) { \
380 AWA_DUMMY_READ(name); \
381 local_irq_restore_hw(flags); \
382 } \
1394f032
BW
383} \
384EXPORT_SYMBOL(set_gpio_ ## name);
385
386SET_GPIO_SC(maska)
387SET_GPIO_SC(maskb)
1394f032 388SET_GPIO_SC(data)
1394f032 389
a2c8cfef 390void set_gpio_toggle(unsigned gpio)
1394f032
BW
391{
392 unsigned long flags;
f556309e
MF
393 if (ANOMALY_05000311 || ANOMALY_05000323)
394 local_irq_save_hw(flags);
395 gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
396 if (ANOMALY_05000311 || ANOMALY_05000323) {
397 AWA_DUMMY_READ(toggle);
398 local_irq_restore_hw(flags);
399 }
1394f032 400}
1394f032
BW
401EXPORT_SYMBOL(set_gpio_toggle);
402
403
404/*Set current PORT date (16-bit word)*/
405
406#define SET_GPIO_P(name) \
a2c8cfef 407void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
1394f032 408{ \
2b39331a 409 unsigned long flags; \
f556309e
MF
410 if (ANOMALY_05000311 || ANOMALY_05000323) \
411 local_irq_save_hw(flags); \
412 gpio_array[gpio_bank(gpio)]->name = arg; \
413 if (ANOMALY_05000311 || ANOMALY_05000323) { \
414 AWA_DUMMY_READ(name); \
415 local_irq_restore_hw(flags); \
416 } \
2b39331a
MH
417} \
418EXPORT_SYMBOL(set_gpiop_ ## name);
1394f032 419
2b39331a 420SET_GPIO_P(data)
1394f032
BW
421SET_GPIO_P(dir)
422SET_GPIO_P(inen)
423SET_GPIO_P(polar)
424SET_GPIO_P(edge)
425SET_GPIO_P(both)
426SET_GPIO_P(maska)
427SET_GPIO_P(maskb)
428
1394f032 429/* Get a specific bit */
2b39331a 430#define GET_GPIO(name) \
a2c8cfef 431unsigned short get_gpio_ ## name(unsigned gpio) \
2b39331a
MH
432{ \
433 unsigned long flags; \
434 unsigned short ret; \
f556309e
MF
435 if (ANOMALY_05000311 || ANOMALY_05000323) \
436 local_irq_save_hw(flags); \
437 ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
438 if (ANOMALY_05000311 || ANOMALY_05000323) { \
439 AWA_DUMMY_READ(name); \
440 local_irq_restore_hw(flags); \
441 } \
2b39331a
MH
442 return ret; \
443} \
444EXPORT_SYMBOL(get_gpio_ ## name);
1394f032 445
2b39331a 446GET_GPIO(data)
1394f032
BW
447GET_GPIO(dir)
448GET_GPIO(inen)
449GET_GPIO(polar)
450GET_GPIO(edge)
451GET_GPIO(both)
452GET_GPIO(maska)
453GET_GPIO(maskb)
454
1394f032
BW
455/*Get current PORT date (16-bit word)*/
456
2b39331a 457#define GET_GPIO_P(name) \
a2c8cfef 458unsigned short get_gpiop_ ## name(unsigned gpio) \
2b39331a
MH
459{ \
460 unsigned long flags; \
461 unsigned short ret; \
f556309e
MF
462 if (ANOMALY_05000311 || ANOMALY_05000323) \
463 local_irq_save_hw(flags); \
464 ret = (gpio_array[gpio_bank(gpio)]->name); \
465 if (ANOMALY_05000311 || ANOMALY_05000323) { \
466 AWA_DUMMY_READ(name); \
467 local_irq_restore_hw(flags); \
468 } \
2b39331a
MH
469 return ret; \
470} \
471EXPORT_SYMBOL(get_gpiop_ ## name);
1394f032 472
2b39331a 473GET_GPIO_P(data)
1394f032
BW
474GET_GPIO_P(dir)
475GET_GPIO_P(inen)
476GET_GPIO_P(polar)
477GET_GPIO_P(edge)
478GET_GPIO_P(both)
479GET_GPIO_P(maska)
480GET_GPIO_P(maskb)
481
1394f032
BW
482
483#ifdef CONFIG_PM
332824b8 484DECLARE_RESERVED_MAP(wakeup, GPIO_BANK_NUM);
f556309e
MF
485
486static const unsigned int sic_iwr_irqs[] = {
487#if defined(BF533_FAMILY)
488 IRQ_PROG_INTB
489#elif defined(BF537_FAMILY)
490 IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX
491#elif defined(BF538_FAMILY)
492 IRQ_PORTF_INTB
269647dc 493#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e
MF
494 IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB
495#elif defined(BF561_FAMILY)
496 IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB
497#else
498# error no SIC_IWR defined
499#endif
500};
501
1394f032
BW
502/***********************************************************
503*
504* FUNCTIONS: Blackfin PM Setup API
505*
506* INPUTS/OUTPUTS:
507* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
508* type -
509* PM_WAKE_RISING
510* PM_WAKE_FALLING
511* PM_WAKE_HIGH
512* PM_WAKE_LOW
513* PM_WAKE_BOTH_EDGES
514*
515* DESCRIPTION: Blackfin PM Driver API
516*
517* CAUTION:
518*************************************************************
519* MODIFICATION HISTORY :
520**************************************************************/
bb84dbf6 521int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
1394f032
BW
522{
523 unsigned long flags;
524
525 if (check_gpio(gpio) < 0)
bb84dbf6 526 return -EINVAL;
1394f032 527
6a01f230 528 local_irq_save_hw(flags);
bb84dbf6 529 if (ctrl)
332824b8 530 reserve(wakeup, gpio);
1394f032 531 else
332824b8 532 unreserve(wakeup, gpio);
1394f032 533
bb84dbf6
MH
534 set_gpio_maskb(gpio, ctrl);
535 local_irq_restore_hw(flags);
2b39331a 536
cfefe3c6 537 return 0;
1394f032
BW
538}
539
bb84dbf6 540int bfin_pm_standby_ctrl(unsigned ctrl)
1394f032
BW
541{
542 u16 bank, mask, i;
543
1f83b8f1 544 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
332824b8 545 mask = map_entry(wakeup, i);
1394f032
BW
546 bank = gpio_bank(i);
547
bb84dbf6
MH
548 if (mask)
549 bfin_internal_set_wake(sic_iwr_irqs[bank], ctrl);
1394f032 550 }
bb84dbf6 551 return 0;
1394f032
BW
552}
553
1efc80b5
MH
554void bfin_gpio_pm_hibernate_suspend(void)
555{
556 int i, bank;
557
558 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
559 bank = gpio_bank(i);
560
269647dc 561#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
f556309e 562 gpio_bank_saved[bank].fer = *port_fer[bank];
269647dc 563#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e 564 gpio_bank_saved[bank].mux = *port_mux[bank];
1efc80b5 565#else
f556309e
MF
566 if (bank == 0)
567 gpio_bank_saved[bank].mux = bfin_read_PORT_MUX();
1efc80b5
MH
568#endif
569#endif
f556309e
MF
570 gpio_bank_saved[bank].data = gpio_array[bank]->data;
571 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
572 gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
573 gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
574 gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
575 gpio_bank_saved[bank].both = gpio_array[bank]->both;
576 gpio_bank_saved[bank].maska = gpio_array[bank]->maska;
1efc80b5
MH
577 }
578
579 AWA_DUMMY_READ(maska);
580}
581
582void bfin_gpio_pm_hibernate_restore(void)
583{
584 int i, bank;
585
586 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
f556309e 587 bank = gpio_bank(i);
1efc80b5 588
269647dc
MF
589#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
590#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e 591 *port_mux[bank] = gpio_bank_saved[bank].mux;
1efc80b5 592#else
f556309e
MF
593 if (bank == 0)
594 bfin_write_PORT_MUX(gpio_bank_saved[bank].mux);
1efc80b5 595#endif
f556309e 596 *port_fer[bank] = gpio_bank_saved[bank].fer;
1efc80b5 597#endif
f556309e 598 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
c03c2a87
MH
599 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
600 & gpio_bank_saved[bank].dir;
f556309e
MF
601 gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
602 gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
603 gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
604 gpio_array[bank]->both = gpio_bank_saved[bank].both;
f556309e 605 gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
1efc80b5
MH
606 }
607 AWA_DUMMY_READ(maska);
608}
609
610
1394f032 611#endif
269647dc 612#else /* CONFIG_BF54x */
1efc80b5
MH
613#ifdef CONFIG_PM
614
bb84dbf6 615int bfin_pm_standby_ctrl(unsigned ctrl)
1efc80b5
MH
616{
617 return 0;
618}
619
1efc80b5
MH
620void bfin_gpio_pm_hibernate_suspend(void)
621{
622 int i, bank;
623
624 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
625 bank = gpio_bank(i);
626
f556309e
MF
627 gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer;
628 gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux;
629 gpio_bank_saved[bank].data = gpio_array[bank]->data;
f556309e
MF
630 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
631 gpio_bank_saved[bank].dir = gpio_array[bank]->dir_set;
1efc80b5
MH
632 }
633}
634
635void bfin_gpio_pm_hibernate_restore(void)
636{
637 int i, bank;
638
639 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
f556309e
MF
640 bank = gpio_bank(i);
641
642 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
643 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
644 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
645 gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
646 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
647 | gpio_bank_saved[bank].dir;
1efc80b5
MH
648 }
649}
650#endif
fac3cf43 651
a2c8cfef 652unsigned short get_gpio_dir(unsigned gpio)
fac3cf43 653{
f556309e 654 return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)));
fac3cf43
MH
655}
656EXPORT_SYMBOL(get_gpio_dir);
657
269647dc 658#endif /* CONFIG_BF54x */
1394f032 659
d2b11a46
MH
660/***********************************************************
661*
662* FUNCTIONS: Blackfin Peripheral Resource Allocation
663* and PortMux Setup
664*
665* INPUTS/OUTPUTS:
666* per Peripheral Identifier
667* label String
668*
669* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
670*
671* CAUTION:
672*************************************************************
673* MODIFICATION HISTORY :
674**************************************************************/
675
d2b11a46
MH
676int peripheral_request(unsigned short per, const char *label)
677{
678 unsigned long flags;
679 unsigned short ident = P_IDENT(per);
680
681 /*
682 * Don't cares are pins with only one dedicated function
683 */
c58c2140 684
d2b11a46
MH
685 if (per & P_DONTCARE)
686 return 0;
687
688 if (!(per & P_DEFINED))
689 return -ENODEV;
690
89e84eea
BS
691 BUG_ON(ident >= MAX_RESOURCES);
692
6a01f230 693 local_irq_save_hw(flags);
d2b11a46 694
6a87d29b
MF
695 /* If a pin can be muxed as either GPIO or peripheral, make
696 * sure it is not already a GPIO pin when we request it.
697 */
332824b8 698 if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
d6879c58
RG
699 if (system_state == SYSTEM_BOOTING)
700 dump_stack();
d2b11a46 701 printk(KERN_ERR
6c7ec0ec 702 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
b85d858b 703 __func__, ident, get_label(ident));
6a01f230 704 local_irq_restore_hw(flags);
d2b11a46
MH
705 return -EBUSY;
706 }
707
332824b8 708 if (unlikely(is_reserved(peri, ident, 1))) {
d2b11a46 709
d171c233
MF
710 /*
711 * Pin functions like AMC address strobes my
712 * be requested and used by several drivers
713 */
d2b11a46 714
269647dc 715#ifdef CONFIG_BF54x
f556309e 716 if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
6c7ec0ec
MF
717#else
718 if (!(per & P_MAYSHARE)) {
719#endif
d171c233
MF
720 /*
721 * Allow that the identical pin function can
722 * be requested from the same driver twice
723 */
d2b11a46 724
d171c233
MF
725 if (cmp_label(ident, label) == 0)
726 goto anyway;
d2b11a46 727
d6879c58
RG
728 if (system_state == SYSTEM_BOOTING)
729 dump_stack();
d2b11a46
MH
730 printk(KERN_ERR
731 "%s: Peripheral %d function %d is already reserved by %s !\n",
b85d858b 732 __func__, ident, P_FUNCT2MUX(per), get_label(ident));
6a01f230 733 local_irq_restore_hw(flags);
d2b11a46
MH
734 return -EBUSY;
735 }
736 }
737
d171c233 738 anyway:
332824b8 739 reserve(peri, ident);
d2b11a46 740
f556309e 741 portmux_setup(per);
c58c2140
MH
742 port_setup(ident, PERIPHERAL_USAGE);
743
6a01f230 744 local_irq_restore_hw(flags);
c58c2140
MH
745 set_label(ident, label);
746
747 return 0;
748}
749EXPORT_SYMBOL(peripheral_request);
750
68179371 751int peripheral_request_list(const unsigned short per[], const char *label)
c58c2140
MH
752{
753 u16 cnt;
754 int ret;
755
756 for (cnt = 0; per[cnt] != 0; cnt++) {
314c98d5 757
c58c2140 758 ret = peripheral_request(per[cnt], label);
314c98d5
MH
759
760 if (ret < 0) {
d171c233 761 for ( ; cnt > 0; cnt--)
314c98d5 762 peripheral_free(per[cnt - 1]);
d171c233
MF
763
764 return ret;
314c98d5 765 }
c58c2140
MH
766 }
767
768 return 0;
769}
770EXPORT_SYMBOL(peripheral_request_list);
771
772void peripheral_free(unsigned short per)
773{
774 unsigned long flags;
775 unsigned short ident = P_IDENT(per);
776
777 if (per & P_DONTCARE)
778 return;
779
780 if (!(per & P_DEFINED))
781 return;
782
6a01f230 783 local_irq_save_hw(flags);
c58c2140 784
332824b8 785 if (unlikely(!is_reserved(peri, ident, 0))) {
6a01f230 786 local_irq_restore_hw(flags);
c58c2140
MH
787 return;
788 }
789
d171c233 790 if (!(per & P_MAYSHARE))
c58c2140 791 port_setup(ident, GPIO_USAGE);
c58c2140 792
332824b8 793 unreserve(peri, ident);
c58c2140 794
2acde902
MH
795 set_label(ident, "free");
796
6a01f230 797 local_irq_restore_hw(flags);
c58c2140
MH
798}
799EXPORT_SYMBOL(peripheral_free);
800
68179371 801void peripheral_free_list(const unsigned short per[])
c58c2140
MH
802{
803 u16 cnt;
d171c233 804 for (cnt = 0; per[cnt] != 0; cnt++)
c58c2140 805 peripheral_free(per[cnt]);
c58c2140
MH
806}
807EXPORT_SYMBOL(peripheral_free_list);
808
1394f032
BW
809/***********************************************************
810*
811* FUNCTIONS: Blackfin GPIO Driver
812*
813* INPUTS/OUTPUTS:
d2b11a46
MH
814* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
815* label String
1394f032
BW
816*
817* DESCRIPTION: Blackfin GPIO Driver API
818*
819* CAUTION:
820*************************************************************
821* MODIFICATION HISTORY :
822**************************************************************/
823
a4f0b32c 824int bfin_gpio_request(unsigned gpio, const char *label)
1394f032
BW
825{
826 unsigned long flags;
827
828 if (check_gpio(gpio) < 0)
829 return -EINVAL;
830
6a01f230 831 local_irq_save_hw(flags);
1394f032 832
2acde902
MH
833 /*
834 * Allow that the identical GPIO can
835 * be requested from the same driver twice
836 * Do nothing and return -
837 */
838
839 if (cmp_label(gpio, label) == 0) {
6a01f230 840 local_irq_restore_hw(flags);
2acde902
MH
841 return 0;
842 }
843
332824b8 844 if (unlikely(is_reserved(gpio, gpio, 1))) {
d6879c58
RG
845 if (system_state == SYSTEM_BOOTING)
846 dump_stack();
d2b11a46 847 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
9570ff4a 848 gpio, get_label(gpio));
6a01f230 849 local_irq_restore_hw(flags);
d2b11a46
MH
850 return -EBUSY;
851 }
332824b8 852 if (unlikely(is_reserved(peri, gpio, 1))) {
d6879c58
RG
853 if (system_state == SYSTEM_BOOTING)
854 dump_stack();
d2b11a46
MH
855 printk(KERN_ERR
856 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
857 gpio, get_label(gpio));
6a01f230 858 local_irq_restore_hw(flags);
1394f032
BW
859 return -EBUSY;
860 }
332824b8 861 if (unlikely(is_reserved(gpio_irq, gpio, 1))) {
9570ff4a
GY
862 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
863 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
a2be3931 864 }
269647dc 865#ifndef CONFIG_BF54x
a2be3931
MH
866 else { /* Reset POLAR setting when acquiring a gpio for the first time */
867 set_gpio_polar(gpio, 0);
868 }
869#endif
d2b11a46 870
332824b8 871 reserve(gpio, gpio);
9570ff4a 872 set_label(gpio, label);
1394f032 873
6a01f230 874 local_irq_restore_hw(flags);
1394f032
BW
875
876 port_setup(gpio, GPIO_USAGE);
877
878 return 0;
879}
a4f0b32c 880EXPORT_SYMBOL(bfin_gpio_request);
1394f032 881
a4f0b32c 882void bfin_gpio_free(unsigned gpio)
1394f032
BW
883{
884 unsigned long flags;
885
886 if (check_gpio(gpio) < 0)
887 return;
888
45c4f2a0
UKK
889 might_sleep();
890
6a01f230 891 local_irq_save_hw(flags);
1394f032 892
332824b8 893 if (unlikely(!is_reserved(gpio, gpio, 0))) {
d6879c58
RG
894 if (system_state == SYSTEM_BOOTING)
895 dump_stack();
f85c4abd 896 gpio_error(gpio);
6a01f230 897 local_irq_restore_hw(flags);
1394f032
BW
898 return;
899 }
900
332824b8 901 unreserve(gpio, gpio);
1394f032 902
2acde902
MH
903 set_label(gpio, "free");
904
6a01f230 905 local_irq_restore_hw(flags);
1394f032 906}
a4f0b32c 907EXPORT_SYMBOL(bfin_gpio_free);
1394f032 908
621dd247 909#ifdef BFIN_SPECIAL_GPIO_BANKS
332824b8 910DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
621dd247
MH
911
912int bfin_special_gpio_request(unsigned gpio, const char *label)
913{
914 unsigned long flags;
915
916 local_irq_save_hw(flags);
917
918 /*
919 * Allow that the identical GPIO can
920 * be requested from the same driver twice
921 * Do nothing and return -
922 */
923
924 if (cmp_label(gpio, label) == 0) {
925 local_irq_restore_hw(flags);
926 return 0;
927 }
928
332824b8 929 if (unlikely(is_reserved(special_gpio, gpio, 1))) {
621dd247
MH
930 local_irq_restore_hw(flags);
931 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
932 gpio, get_label(gpio));
933
934 return -EBUSY;
935 }
332824b8 936 if (unlikely(is_reserved(peri, gpio, 1))) {
621dd247
MH
937 local_irq_restore_hw(flags);
938 printk(KERN_ERR
939 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
940 gpio, get_label(gpio));
941
942 return -EBUSY;
943 }
944
332824b8
MF
945 reserve(special_gpio, gpio);
946 reserve(peri, gpio);
621dd247
MH
947
948 set_label(gpio, label);
949 local_irq_restore_hw(flags);
950 port_setup(gpio, GPIO_USAGE);
951
952 return 0;
953}
954EXPORT_SYMBOL(bfin_special_gpio_request);
955
956void bfin_special_gpio_free(unsigned gpio)
957{
958 unsigned long flags;
959
960 might_sleep();
961
962 local_irq_save_hw(flags);
963
332824b8 964 if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
621dd247
MH
965 gpio_error(gpio);
966 local_irq_restore_hw(flags);
967 return;
968 }
969
332824b8
MF
970 unreserve(special_gpio, gpio);
971 unreserve(peri, gpio);
621dd247
MH
972 set_label(gpio, "free");
973 local_irq_restore_hw(flags);
974}
975EXPORT_SYMBOL(bfin_special_gpio_free);
976#endif
977
978
9570ff4a
GY
979int bfin_gpio_irq_request(unsigned gpio, const char *label)
980{
981 unsigned long flags;
982
983 if (check_gpio(gpio) < 0)
984 return -EINVAL;
985
6a01f230 986 local_irq_save_hw(flags);
9570ff4a 987
332824b8 988 if (unlikely(is_reserved(peri, gpio, 1))) {
d6879c58
RG
989 if (system_state == SYSTEM_BOOTING)
990 dump_stack();
9570ff4a
GY
991 printk(KERN_ERR
992 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
993 gpio, get_label(gpio));
6a01f230 994 local_irq_restore_hw(flags);
9570ff4a
GY
995 return -EBUSY;
996 }
332824b8 997 if (unlikely(is_reserved(gpio, gpio, 1)))
9570ff4a
GY
998 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
999 "(Documentation/blackfin/bfin-gpio-notes.txt)\n",
1000 gpio, get_label(gpio));
1001
332824b8 1002 reserve(gpio_irq, gpio);
9570ff4a
GY
1003 set_label(gpio, label);
1004
6a01f230 1005 local_irq_restore_hw(flags);
9570ff4a
GY
1006
1007 port_setup(gpio, GPIO_USAGE);
1008
1009 return 0;
1010}
1011
1012void bfin_gpio_irq_free(unsigned gpio)
1013{
1014 unsigned long flags;
1015
1016 if (check_gpio(gpio) < 0)
1017 return;
1018
6a01f230 1019 local_irq_save_hw(flags);
9570ff4a 1020
332824b8 1021 if (unlikely(!is_reserved(gpio_irq, gpio, 0))) {
d6879c58
RG
1022 if (system_state == SYSTEM_BOOTING)
1023 dump_stack();
9570ff4a 1024 gpio_error(gpio);
6a01f230 1025 local_irq_restore_hw(flags);
9570ff4a
GY
1026 return;
1027 }
1028
332824b8 1029 unreserve(gpio_irq, gpio);
9570ff4a
GY
1030
1031 set_label(gpio, "free");
1032
6a01f230 1033 local_irq_restore_hw(flags);
9570ff4a
GY
1034}
1035
f556309e
MF
1036static inline void __bfin_gpio_direction_input(unsigned gpio)
1037{
269647dc 1038#ifdef CONFIG_BF54x
f556309e
MF
1039 gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
1040#else
1041 gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1042#endif
1043 gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
1044}
1045
a4f0b32c 1046int bfin_gpio_direction_input(unsigned gpio)
d2b11a46
MH
1047{
1048 unsigned long flags;
1049
332824b8 1050 if (unlikely(!is_reserved(gpio, gpio, 0))) {
acbcd263
MH
1051 gpio_error(gpio);
1052 return -EINVAL;
1053 }
1054
6a01f230 1055 local_irq_save_hw(flags);
f556309e
MF
1056 __bfin_gpio_direction_input(gpio);
1057 AWA_DUMMY_READ(inen);
6a01f230 1058 local_irq_restore_hw(flags);
acbcd263
MH
1059
1060 return 0;
d2b11a46 1061}
a4f0b32c 1062EXPORT_SYMBOL(bfin_gpio_direction_input);
d2b11a46 1063
f556309e 1064void bfin_gpio_irq_prepare(unsigned gpio)
d2b11a46 1065{
269647dc 1066#ifdef CONFIG_BF54x
d2b11a46 1067 unsigned long flags;
f556309e 1068#endif
d2b11a46 1069
f556309e 1070 port_setup(gpio, GPIO_USAGE);
d2b11a46 1071
269647dc 1072#ifdef CONFIG_BF54x
6a01f230 1073 local_irq_save_hw(flags);
f556309e 1074 __bfin_gpio_direction_input(gpio);
6a01f230 1075 local_irq_restore_hw(flags);
f556309e 1076#endif
d2b11a46 1077}
d2b11a46 1078
a4f0b32c 1079void bfin_gpio_set_value(unsigned gpio, int arg)
d2b11a46
MH
1080{
1081 if (arg)
f556309e 1082 gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
d2b11a46 1083 else
f556309e 1084 gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
d2b11a46 1085}
a4f0b32c 1086EXPORT_SYMBOL(bfin_gpio_set_value);
d2b11a46 1087
f556309e 1088int bfin_gpio_direction_output(unsigned gpio, int value)
affee2b2
MH
1089{
1090 unsigned long flags;
1091
332824b8 1092 if (unlikely(!is_reserved(gpio, gpio, 0))) {
f556309e
MF
1093 gpio_error(gpio);
1094 return -EINVAL;
1095 }
affee2b2 1096
6a01f230 1097 local_irq_save_hw(flags);
affee2b2 1098
f556309e
MF
1099 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1100 gpio_set_value(gpio, value);
269647dc 1101#ifdef CONFIG_BF54x
f556309e 1102 gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
d2b11a46 1103#else
f556309e
MF
1104 gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
1105#endif
1106
1107 AWA_DUMMY_READ(dir);
1108 local_irq_restore_hw(flags);
1109
1110 return 0;
1111}
1112EXPORT_SYMBOL(bfin_gpio_direction_output);
d2b11a46 1113
a4f0b32c 1114int bfin_gpio_get_value(unsigned gpio)
803a8d2a 1115{
269647dc 1116#ifdef CONFIG_BF54x
f556309e
MF
1117 return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
1118#else
803a8d2a 1119 unsigned long flags;
803a8d2a
MH
1120
1121 if (unlikely(get_gpio_edge(gpio))) {
f556309e 1122 int ret;
6a01f230 1123 local_irq_save_hw(flags);
803a8d2a
MH
1124 set_gpio_edge(gpio, 0);
1125 ret = get_gpio_data(gpio);
1126 set_gpio_edge(gpio, 1);
6a01f230 1127 local_irq_restore_hw(flags);
803a8d2a
MH
1128 return ret;
1129 } else
1130 return get_gpio_data(gpio);
f556309e 1131#endif
803a8d2a 1132}
a4f0b32c 1133EXPORT_SYMBOL(bfin_gpio_get_value);
803a8d2a 1134
168f1212
MF
1135/* If we are booting from SPI and our board lacks a strong enough pull up,
1136 * the core can reset and execute the bootrom faster than the resistor can
1137 * pull the signal logically high. To work around this (common) error in
1138 * board design, we explicitly set the pin back to GPIO mode, force /CS
1139 * high, and wait for the electrons to do their thing.
1140 *
1141 * This function only makes sense to be called from reset code, but it
1142 * lives here as we need to force all the GPIO states w/out going through
1143 * BUG() checks and such.
1144 */
b52dae31 1145void bfin_reset_boot_spi_cs(unsigned short pin)
168f1212 1146{
b52dae31 1147 unsigned short gpio = P_IDENT(pin);
4d5f4ed3 1148 port_setup(gpio, GPIO_USAGE);
f556309e 1149 gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
a2c8cfef 1150 AWA_DUMMY_READ(data_set);
168f1212
MF
1151 udelay(1);
1152}
d2b11a46 1153
1545a111
MF
1154#if defined(CONFIG_PROC_FS)
1155static int gpio_proc_read(char *buf, char **start, off_t offset,
1156 int len, int *unused_i, void *unused_v)
1157{
9570ff4a 1158 int c, irq, gpio, outlen = 0;
1545a111
MF
1159
1160 for (c = 0; c < MAX_RESOURCES; c++) {
332824b8
MF
1161 irq = is_reserved(gpio_irq, c, 1);
1162 gpio = is_reserved(gpio, c, 1);
9570ff4a
GY
1163 if (!check_gpio(c) && (gpio || irq))
1164 len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
1165 get_label(c), (gpio && irq) ? " *" : "",
1166 get_gpio_dir(c) ? "OUTPUT" : "INPUT");
332824b8 1167 else if (is_reserved(peri, c, 1))
8eb3e3bf 1168 len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
1545a111
MF
1169 else
1170 continue;
1171 buf += len;
1172 outlen += len;
1173 }
1174 return outlen;
1175}
1176
1177static __init int gpio_register_proc(void)
1178{
1179 struct proc_dir_entry *proc_gpio;
1180
1181 proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
1182 if (proc_gpio)
1183 proc_gpio->read_proc = gpio_proc_read;
1184 return proc_gpio != NULL;
1185}
1545a111
MF
1186__initcall(gpio_register_proc);
1187#endif
a4f0b32c
MH
1188
1189#ifdef CONFIG_GPIOLIB
f9c29e87 1190static int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio)
a4f0b32c
MH
1191{
1192 return bfin_gpio_direction_input(gpio);
1193}
1194
f9c29e87 1195static int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
a4f0b32c
MH
1196{
1197 return bfin_gpio_direction_output(gpio, level);
1198}
1199
f9c29e87 1200static int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio)
a4f0b32c
MH
1201{
1202 return bfin_gpio_get_value(gpio);
1203}
1204
f9c29e87 1205static void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value)
a4f0b32c 1206{
a4f0b32c 1207 return bfin_gpio_set_value(gpio, value);
a4f0b32c
MH
1208}
1209
f9c29e87 1210static int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio)
a4f0b32c
MH
1211{
1212 return bfin_gpio_request(gpio, chip->label);
1213}
1214
f9c29e87 1215static void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio)
a4f0b32c
MH
1216{
1217 return bfin_gpio_free(gpio);
1218}
1219
f9c29e87 1220static int bfin_gpiolib_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
7f4f69f9
JE
1221{
1222 return gpio + GPIO_IRQ_BASE;
1223}
1224
a4f0b32c 1225static struct gpio_chip bfin_chip = {
edd07992 1226 .label = "BFIN-GPIO",
a4f0b32c
MH
1227 .direction_input = bfin_gpiolib_direction_input,
1228 .get = bfin_gpiolib_get_value,
1229 .direction_output = bfin_gpiolib_direction_output,
1230 .set = bfin_gpiolib_set_value,
1231 .request = bfin_gpiolib_gpio_request,
1232 .free = bfin_gpiolib_gpio_free,
7f4f69f9 1233 .to_irq = bfin_gpiolib_gpio_to_irq,
a4f0b32c
MH
1234 .base = 0,
1235 .ngpio = MAX_BLACKFIN_GPIOS,
1236};
1237
1238static int __init bfin_gpiolib_setup(void)
1239{
1240 return gpiochip_add(&bfin_chip);
1241}
1242arch_initcall(bfin_gpiolib_setup);
1243#endif
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