Commit | Line | Data |
---|---|---|
1394f032 | 1 | /* |
96f1050d | 2 | * GPIO Abstraction Layer |
1394f032 | 3 | * |
96f1050d | 4 | * Copyright 2006-2009 Analog Devices Inc. |
1394f032 | 5 | * |
96f1050d | 6 | * Licensed under the GPL-2 or later |
1394f032 BW |
7 | */ |
8 | ||
168f1212 | 9 | #include <linux/delay.h> |
1394f032 BW |
10 | #include <linux/module.h> |
11 | #include <linux/err.h> | |
1545a111 | 12 | #include <linux/proc_fs.h> |
1394f032 BW |
13 | #include <asm/blackfin.h> |
14 | #include <asm/gpio.h> | |
c58c2140 | 15 | #include <asm/portmux.h> |
1394f032 BW |
16 | #include <linux/irq.h> |
17 | ||
2b39331a MH |
18 | #if ANOMALY_05000311 || ANOMALY_05000323 |
19 | enum { | |
20 | AWA_data = SYSCR, | |
21 | AWA_data_clear = SYSCR, | |
22 | AWA_data_set = SYSCR, | |
23 | AWA_toggle = SYSCR, | |
6ed83942 GY |
24 | AWA_maska = BFIN_UART_SCR, |
25 | AWA_maska_clear = BFIN_UART_SCR, | |
26 | AWA_maska_set = BFIN_UART_SCR, | |
27 | AWA_maska_toggle = BFIN_UART_SCR, | |
28 | AWA_maskb = BFIN_UART_GCTL, | |
29 | AWA_maskb_clear = BFIN_UART_GCTL, | |
30 | AWA_maskb_set = BFIN_UART_GCTL, | |
31 | AWA_maskb_toggle = BFIN_UART_GCTL, | |
2b39331a MH |
32 | AWA_dir = SPORT1_STAT, |
33 | AWA_polar = SPORT1_STAT, | |
34 | AWA_edge = SPORT1_STAT, | |
35 | AWA_both = SPORT1_STAT, | |
36 | #if ANOMALY_05000311 | |
37 | AWA_inen = TIMER_ENABLE, | |
38 | #elif ANOMALY_05000323 | |
39 | AWA_inen = DMA1_1_CONFIG, | |
40 | #endif | |
41 | }; | |
42 | /* Anomaly Workaround */ | |
43 | #define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name) | |
44 | #else | |
45 | #define AWA_DUMMY_READ(...) do { } while (0) | |
46 | #endif | |
47 | ||
f556309e | 48 | static struct gpio_port_t * const gpio_array[] = { |
dc26aec2 | 49 | #if defined(BF533_FAMILY) || defined(BF538_FAMILY) |
1394f032 | 50 | (struct gpio_port_t *) FIO_FLAG_D, |
269647dc | 51 | #elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) |
1394f032 BW |
52 | (struct gpio_port_t *) PORTFIO, |
53 | (struct gpio_port_t *) PORTGIO, | |
54 | (struct gpio_port_t *) PORTHIO, | |
f556309e MF |
55 | #elif defined(BF561_FAMILY) |
56 | (struct gpio_port_t *) FIO0_FLAG_D, | |
57 | (struct gpio_port_t *) FIO1_FLAG_D, | |
58 | (struct gpio_port_t *) FIO2_FLAG_D, | |
269647dc | 59 | #elif defined(CONFIG_BF54x) |
f556309e MF |
60 | (struct gpio_port_t *)PORTA_FER, |
61 | (struct gpio_port_t *)PORTB_FER, | |
62 | (struct gpio_port_t *)PORTC_FER, | |
63 | (struct gpio_port_t *)PORTD_FER, | |
64 | (struct gpio_port_t *)PORTE_FER, | |
65 | (struct gpio_port_t *)PORTF_FER, | |
66 | (struct gpio_port_t *)PORTG_FER, | |
67 | (struct gpio_port_t *)PORTH_FER, | |
68 | (struct gpio_port_t *)PORTI_FER, | |
69 | (struct gpio_port_t *)PORTJ_FER, | |
70 | #else | |
71 | # error no gpio arrays defined | |
72 | #endif | |
1394f032 BW |
73 | }; |
74 | ||
269647dc | 75 | #if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) |
f556309e | 76 | static unsigned short * const port_fer[] = { |
1394f032 BW |
77 | (unsigned short *) PORTF_FER, |
78 | (unsigned short *) PORTG_FER, | |
79 | (unsigned short *) PORTH_FER, | |
80 | }; | |
1394f032 | 81 | |
f556309e MF |
82 | # if !defined(BF537_FAMILY) |
83 | static unsigned short * const port_mux[] = { | |
59003145 MH |
84 | (unsigned short *) PORTF_MUX, |
85 | (unsigned short *) PORTG_MUX, | |
86 | (unsigned short *) PORTH_MUX, | |
87 | }; | |
88 | ||
89 | static const | |
0ce5eaf8 | 90 | u8 pmux_offset[][16] = { |
269647dc | 91 | # if defined(CONFIG_BF52x) |
0ce5eaf8 GY |
92 | { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */ |
93 | { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */ | |
94 | { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */ | |
269647dc | 95 | # elif defined(CONFIG_BF51x) |
0ce5eaf8 GY |
96 | { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */ |
97 | { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */ | |
98 | { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */ | |
99 | # endif | |
100 | }; | |
f556309e | 101 | # endif |
0ce5eaf8 | 102 | |
621dd247 MH |
103 | #elif defined(BF538_FAMILY) |
104 | static unsigned short * const port_fer[] = { | |
105 | (unsigned short *) PORTCIO_FER, | |
106 | (unsigned short *) PORTDIO_FER, | |
107 | (unsigned short *) PORTEIO_FER, | |
108 | }; | |
d2b11a46 MH |
109 | #endif |
110 | ||
397861cd | 111 | static unsigned short reserved_gpio_map[GPIO_BANK_NUM]; |
fac3cf43 | 112 | static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)]; |
9570ff4a | 113 | static unsigned short reserved_gpio_irq_map[GPIO_BANK_NUM]; |
c58c2140 | 114 | |
8c613623 MH |
115 | #define RESOURCE_LABEL_SIZE 16 |
116 | ||
fac3cf43 | 117 | static struct str_ident { |
8c613623 | 118 | char name[RESOURCE_LABEL_SIZE]; |
fac3cf43 | 119 | } str_ident[MAX_RESOURCES]; |
1394f032 | 120 | |
1efc80b5 | 121 | #if defined(CONFIG_PM) |
397861cd | 122 | static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM]; |
59003145 MH |
123 | #endif |
124 | ||
a2c8cfef | 125 | inline int check_gpio(unsigned gpio) |
d2b11a46 | 126 | { |
269647dc | 127 | #if defined(CONFIG_BF54x) |
d2b11a46 MH |
128 | if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 |
129 | || gpio == GPIO_PH14 || gpio == GPIO_PH15 | |
27228b2e | 130 | || gpio == GPIO_PJ14 || gpio == GPIO_PJ15) |
d2b11a46 | 131 | return -EINVAL; |
27228b2e | 132 | #endif |
e7613aab | 133 | if (gpio >= MAX_BLACKFIN_GPIOS) |
1394f032 BW |
134 | return -EINVAL; |
135 | return 0; | |
136 | } | |
137 | ||
74c04503 | 138 | static void gpio_error(unsigned gpio) |
acbcd263 MH |
139 | { |
140 | printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio); | |
141 | } | |
142 | ||
c58c2140 MH |
143 | static void set_label(unsigned short ident, const char *label) |
144 | { | |
e9fae189 | 145 | if (label) { |
8c613623 | 146 | strncpy(str_ident[ident].name, label, |
c58c2140 | 147 | RESOURCE_LABEL_SIZE); |
8c613623 | 148 | str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0; |
c58c2140 MH |
149 | } |
150 | } | |
151 | ||
152 | static char *get_label(unsigned short ident) | |
153 | { | |
8c613623 | 154 | return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN"); |
c58c2140 MH |
155 | } |
156 | ||
157 | static int cmp_label(unsigned short ident, const char *label) | |
158 | { | |
fac3cf43 MH |
159 | if (label == NULL) { |
160 | dump_stack(); | |
161 | printk(KERN_ERR "Please provide none-null label\n"); | |
162 | } | |
163 | ||
e9fae189 | 164 | if (label) |
1f7d373f | 165 | return strcmp(str_ident[ident].name, label); |
c58c2140 MH |
166 | else |
167 | return -EINVAL; | |
168 | } | |
169 | ||
a2c8cfef | 170 | static void port_setup(unsigned gpio, unsigned short usage) |
1394f032 | 171 | { |
621dd247 MH |
172 | #if defined(BF538_FAMILY) |
173 | /* | |
174 | * BF538/9 Port C,D and E are special. | |
175 | * Inverted PORT_FER polarity on CDE and no PORF_FER on F | |
176 | * Regular PORT F GPIOs are handled here, CDE are exclusively | |
177 | * managed by GPIOLIB | |
178 | */ | |
179 | ||
180 | if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES) | |
181 | return; | |
182 | ||
183 | gpio -= MAX_BLACKFIN_GPIOS; | |
184 | ||
185 | if (usage == GPIO_USAGE) | |
186 | *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); | |
187 | else | |
188 | *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); | |
189 | SSYNC(); | |
190 | return; | |
191 | #endif | |
192 | ||
a2d03a1d MF |
193 | if (check_gpio(gpio)) |
194 | return; | |
195 | ||
269647dc | 196 | #if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) |
a2d03a1d MF |
197 | if (usage == GPIO_USAGE) |
198 | *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); | |
199 | else | |
200 | *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); | |
201 | SSYNC(); | |
269647dc | 202 | #elif defined(CONFIG_BF54x) |
d2b11a46 MH |
203 | if (usage == GPIO_USAGE) |
204 | gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); | |
205 | else | |
206 | gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio); | |
207 | SSYNC(); | |
1394f032 | 208 | #endif |
a2d03a1d | 209 | } |
1394f032 | 210 | |
c58c2140 | 211 | #ifdef BF537_FAMILY |
8c613623 MH |
212 | static struct { |
213 | unsigned short res; | |
214 | unsigned short offset; | |
215 | } port_mux_lut[] = { | |
216 | {.res = P_PPI0_D13, .offset = 11}, | |
217 | {.res = P_PPI0_D14, .offset = 11}, | |
218 | {.res = P_PPI0_D15, .offset = 11}, | |
219 | {.res = P_SPORT1_TFS, .offset = 11}, | |
220 | {.res = P_SPORT1_TSCLK, .offset = 11}, | |
221 | {.res = P_SPORT1_DTPRI, .offset = 11}, | |
222 | {.res = P_PPI0_D10, .offset = 10}, | |
223 | {.res = P_PPI0_D11, .offset = 10}, | |
224 | {.res = P_PPI0_D12, .offset = 10}, | |
225 | {.res = P_SPORT1_RSCLK, .offset = 10}, | |
226 | {.res = P_SPORT1_RFS, .offset = 10}, | |
227 | {.res = P_SPORT1_DRPRI, .offset = 10}, | |
228 | {.res = P_PPI0_D8, .offset = 9}, | |
229 | {.res = P_PPI0_D9, .offset = 9}, | |
230 | {.res = P_SPORT1_DRSEC, .offset = 9}, | |
231 | {.res = P_SPORT1_DTSEC, .offset = 9}, | |
232 | {.res = P_TMR2, .offset = 8}, | |
233 | {.res = P_PPI0_FS3, .offset = 8}, | |
234 | {.res = P_TMR3, .offset = 7}, | |
235 | {.res = P_SPI0_SSEL4, .offset = 7}, | |
236 | {.res = P_TMR4, .offset = 6}, | |
237 | {.res = P_SPI0_SSEL5, .offset = 6}, | |
238 | {.res = P_TMR5, .offset = 5}, | |
239 | {.res = P_SPI0_SSEL6, .offset = 5}, | |
240 | {.res = P_UART1_RX, .offset = 4}, | |
241 | {.res = P_UART1_TX, .offset = 4}, | |
242 | {.res = P_TMR6, .offset = 4}, | |
243 | {.res = P_TMR7, .offset = 4}, | |
244 | {.res = P_UART0_RX, .offset = 3}, | |
245 | {.res = P_UART0_TX, .offset = 3}, | |
246 | {.res = P_DMAR0, .offset = 3}, | |
247 | {.res = P_DMAR1, .offset = 3}, | |
248 | {.res = P_SPORT0_DTSEC, .offset = 1}, | |
249 | {.res = P_SPORT0_DRSEC, .offset = 1}, | |
250 | {.res = P_CAN0_RX, .offset = 1}, | |
251 | {.res = P_CAN0_TX, .offset = 1}, | |
252 | {.res = P_SPI0_SSEL7, .offset = 1}, | |
253 | {.res = P_SPORT0_TFS, .offset = 0}, | |
254 | {.res = P_SPORT0_DTPRI, .offset = 0}, | |
255 | {.res = P_SPI0_SSEL2, .offset = 0}, | |
256 | {.res = P_SPI0_SSEL3, .offset = 0}, | |
c58c2140 MH |
257 | }; |
258 | ||
f556309e | 259 | static void portmux_setup(unsigned short per) |
c58c2140 | 260 | { |
8c613623 | 261 | u16 y, offset, muxreg; |
f556309e | 262 | u16 function = P_FUNCT2MUX(per); |
c58c2140 | 263 | |
8c613623 MH |
264 | for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) { |
265 | if (port_mux_lut[y].res == per) { | |
c58c2140 MH |
266 | |
267 | /* SET PORTMUX REG */ | |
268 | ||
8c613623 | 269 | offset = port_mux_lut[y].offset; |
c58c2140 MH |
270 | muxreg = bfin_read_PORT_MUX(); |
271 | ||
d171c233 | 272 | if (offset != 1) |
c58c2140 | 273 | muxreg &= ~(1 << offset); |
d171c233 | 274 | else |
c58c2140 | 275 | muxreg &= ~(3 << 1); |
c58c2140 MH |
276 | |
277 | muxreg |= (function << offset); | |
278 | bfin_write_PORT_MUX(muxreg); | |
279 | } | |
280 | } | |
281 | } | |
269647dc | 282 | #elif defined(CONFIG_BF54x) |
f556309e | 283 | inline void portmux_setup(unsigned short per) |
d2b11a46 MH |
284 | { |
285 | u32 pmux; | |
f556309e MF |
286 | u16 ident = P_IDENT(per); |
287 | u16 function = P_FUNCT2MUX(per); | |
d2b11a46 | 288 | |
f556309e | 289 | pmux = gpio_array[gpio_bank(ident)]->port_mux; |
d2b11a46 | 290 | |
f556309e MF |
291 | pmux &= ~(0x3 << (2 * gpio_sub_n(ident))); |
292 | pmux |= (function & 0x3) << (2 * gpio_sub_n(ident)); | |
d2b11a46 | 293 | |
f556309e | 294 | gpio_array[gpio_bank(ident)]->port_mux = pmux; |
d2b11a46 MH |
295 | } |
296 | ||
f556309e | 297 | inline u16 get_portmux(unsigned short per) |
d2b11a46 MH |
298 | { |
299 | u32 pmux; | |
f556309e | 300 | u16 ident = P_IDENT(per); |
c58c2140 | 301 | |
f556309e | 302 | pmux = gpio_array[gpio_bank(ident)]->port_mux; |
d2b11a46 | 303 | |
f556309e | 304 | return (pmux >> (2 * gpio_sub_n(ident)) & 0x3); |
d2b11a46 | 305 | } |
269647dc | 306 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
f556309e | 307 | inline void portmux_setup(unsigned short per) |
59003145 | 308 | { |
f556309e | 309 | u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per); |
59003145 MH |
310 | u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)]; |
311 | ||
312 | pmux = *port_mux[gpio_bank(ident)]; | |
313 | pmux &= ~(3 << offset); | |
314 | pmux |= (function & 3) << offset; | |
315 | *port_mux[gpio_bank(ident)] = pmux; | |
316 | SSYNC(); | |
317 | } | |
c58c2140 MH |
318 | #else |
319 | # define portmux_setup(...) do { } while (0) | |
320 | #endif | |
1394f032 | 321 | |
269647dc | 322 | #ifndef CONFIG_BF54x |
1394f032 BW |
323 | /*********************************************************** |
324 | * | |
325 | * FUNCTIONS: Blackfin General Purpose Ports Access Functions | |
326 | * | |
327 | * INPUTS/OUTPUTS: | |
328 | * gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS | |
329 | * | |
330 | * | |
331 | * DESCRIPTION: These functions abstract direct register access | |
332 | * to Blackfin processor General Purpose | |
333 | * Ports Regsiters | |
334 | * | |
335 | * CAUTION: These functions do not belong to the GPIO Driver API | |
336 | ************************************************************* | |
337 | * MODIFICATION HISTORY : | |
338 | **************************************************************/ | |
339 | ||
340 | /* Set a specific bit */ | |
341 | ||
342 | #define SET_GPIO(name) \ | |
a2c8cfef | 343 | void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ |
1394f032 BW |
344 | { \ |
345 | unsigned long flags; \ | |
6a01f230 | 346 | local_irq_save_hw(flags); \ |
1394f032 | 347 | if (arg) \ |
f556309e | 348 | gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \ |
1394f032 | 349 | else \ |
f556309e | 350 | gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \ |
2b39331a | 351 | AWA_DUMMY_READ(name); \ |
6a01f230 | 352 | local_irq_restore_hw(flags); \ |
1394f032 BW |
353 | } \ |
354 | EXPORT_SYMBOL(set_gpio_ ## name); | |
355 | ||
f556309e MF |
356 | SET_GPIO(dir) /* set_gpio_dir() */ |
357 | SET_GPIO(inen) /* set_gpio_inen() */ | |
358 | SET_GPIO(polar) /* set_gpio_polar() */ | |
359 | SET_GPIO(edge) /* set_gpio_edge() */ | |
360 | SET_GPIO(both) /* set_gpio_both() */ | |
1394f032 BW |
361 | |
362 | ||
2b39331a | 363 | #define SET_GPIO_SC(name) \ |
a2c8cfef | 364 | void set_gpio_ ## name(unsigned gpio, unsigned short arg) \ |
2b39331a MH |
365 | { \ |
366 | unsigned long flags; \ | |
f556309e MF |
367 | if (ANOMALY_05000311 || ANOMALY_05000323) \ |
368 | local_irq_save_hw(flags); \ | |
1394f032 | 369 | if (arg) \ |
f556309e | 370 | gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \ |
1394f032 | 371 | else \ |
f556309e MF |
372 | gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \ |
373 | if (ANOMALY_05000311 || ANOMALY_05000323) { \ | |
374 | AWA_DUMMY_READ(name); \ | |
375 | local_irq_restore_hw(flags); \ | |
376 | } \ | |
1394f032 BW |
377 | } \ |
378 | EXPORT_SYMBOL(set_gpio_ ## name); | |
379 | ||
380 | SET_GPIO_SC(maska) | |
381 | SET_GPIO_SC(maskb) | |
1394f032 | 382 | SET_GPIO_SC(data) |
1394f032 | 383 | |
a2c8cfef | 384 | void set_gpio_toggle(unsigned gpio) |
1394f032 BW |
385 | { |
386 | unsigned long flags; | |
f556309e MF |
387 | if (ANOMALY_05000311 || ANOMALY_05000323) |
388 | local_irq_save_hw(flags); | |
389 | gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio); | |
390 | if (ANOMALY_05000311 || ANOMALY_05000323) { | |
391 | AWA_DUMMY_READ(toggle); | |
392 | local_irq_restore_hw(flags); | |
393 | } | |
1394f032 | 394 | } |
1394f032 BW |
395 | EXPORT_SYMBOL(set_gpio_toggle); |
396 | ||
397 | ||
398 | /*Set current PORT date (16-bit word)*/ | |
399 | ||
400 | #define SET_GPIO_P(name) \ | |
a2c8cfef | 401 | void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \ |
1394f032 | 402 | { \ |
2b39331a | 403 | unsigned long flags; \ |
f556309e MF |
404 | if (ANOMALY_05000311 || ANOMALY_05000323) \ |
405 | local_irq_save_hw(flags); \ | |
406 | gpio_array[gpio_bank(gpio)]->name = arg; \ | |
407 | if (ANOMALY_05000311 || ANOMALY_05000323) { \ | |
408 | AWA_DUMMY_READ(name); \ | |
409 | local_irq_restore_hw(flags); \ | |
410 | } \ | |
2b39331a MH |
411 | } \ |
412 | EXPORT_SYMBOL(set_gpiop_ ## name); | |
1394f032 | 413 | |
2b39331a | 414 | SET_GPIO_P(data) |
1394f032 BW |
415 | SET_GPIO_P(dir) |
416 | SET_GPIO_P(inen) | |
417 | SET_GPIO_P(polar) | |
418 | SET_GPIO_P(edge) | |
419 | SET_GPIO_P(both) | |
420 | SET_GPIO_P(maska) | |
421 | SET_GPIO_P(maskb) | |
422 | ||
1394f032 | 423 | /* Get a specific bit */ |
2b39331a | 424 | #define GET_GPIO(name) \ |
a2c8cfef | 425 | unsigned short get_gpio_ ## name(unsigned gpio) \ |
2b39331a MH |
426 | { \ |
427 | unsigned long flags; \ | |
428 | unsigned short ret; \ | |
f556309e MF |
429 | if (ANOMALY_05000311 || ANOMALY_05000323) \ |
430 | local_irq_save_hw(flags); \ | |
431 | ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \ | |
432 | if (ANOMALY_05000311 || ANOMALY_05000323) { \ | |
433 | AWA_DUMMY_READ(name); \ | |
434 | local_irq_restore_hw(flags); \ | |
435 | } \ | |
2b39331a MH |
436 | return ret; \ |
437 | } \ | |
438 | EXPORT_SYMBOL(get_gpio_ ## name); | |
1394f032 | 439 | |
2b39331a | 440 | GET_GPIO(data) |
1394f032 BW |
441 | GET_GPIO(dir) |
442 | GET_GPIO(inen) | |
443 | GET_GPIO(polar) | |
444 | GET_GPIO(edge) | |
445 | GET_GPIO(both) | |
446 | GET_GPIO(maska) | |
447 | GET_GPIO(maskb) | |
448 | ||
1394f032 BW |
449 | /*Get current PORT date (16-bit word)*/ |
450 | ||
2b39331a | 451 | #define GET_GPIO_P(name) \ |
a2c8cfef | 452 | unsigned short get_gpiop_ ## name(unsigned gpio) \ |
2b39331a MH |
453 | { \ |
454 | unsigned long flags; \ | |
455 | unsigned short ret; \ | |
f556309e MF |
456 | if (ANOMALY_05000311 || ANOMALY_05000323) \ |
457 | local_irq_save_hw(flags); \ | |
458 | ret = (gpio_array[gpio_bank(gpio)]->name); \ | |
459 | if (ANOMALY_05000311 || ANOMALY_05000323) { \ | |
460 | AWA_DUMMY_READ(name); \ | |
461 | local_irq_restore_hw(flags); \ | |
462 | } \ | |
2b39331a MH |
463 | return ret; \ |
464 | } \ | |
465 | EXPORT_SYMBOL(get_gpiop_ ## name); | |
1394f032 | 466 | |
2b39331a | 467 | GET_GPIO_P(data) |
1394f032 BW |
468 | GET_GPIO_P(dir) |
469 | GET_GPIO_P(inen) | |
470 | GET_GPIO_P(polar) | |
471 | GET_GPIO_P(edge) | |
472 | GET_GPIO_P(both) | |
473 | GET_GPIO_P(maska) | |
474 | GET_GPIO_P(maskb) | |
475 | ||
1394f032 BW |
476 | |
477 | #ifdef CONFIG_PM | |
f556309e MF |
478 | |
479 | static unsigned short wakeup_map[GPIO_BANK_NUM]; | |
480 | static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS]; | |
481 | ||
482 | static const unsigned int sic_iwr_irqs[] = { | |
483 | #if defined(BF533_FAMILY) | |
484 | IRQ_PROG_INTB | |
485 | #elif defined(BF537_FAMILY) | |
486 | IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX | |
487 | #elif defined(BF538_FAMILY) | |
488 | IRQ_PORTF_INTB | |
269647dc | 489 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
f556309e MF |
490 | IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB |
491 | #elif defined(BF561_FAMILY) | |
492 | IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB | |
493 | #else | |
494 | # error no SIC_IWR defined | |
495 | #endif | |
496 | }; | |
497 | ||
1394f032 BW |
498 | /*********************************************************** |
499 | * | |
500 | * FUNCTIONS: Blackfin PM Setup API | |
501 | * | |
502 | * INPUTS/OUTPUTS: | |
503 | * gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS | |
504 | * type - | |
505 | * PM_WAKE_RISING | |
506 | * PM_WAKE_FALLING | |
507 | * PM_WAKE_HIGH | |
508 | * PM_WAKE_LOW | |
509 | * PM_WAKE_BOTH_EDGES | |
510 | * | |
511 | * DESCRIPTION: Blackfin PM Driver API | |
512 | * | |
513 | * CAUTION: | |
514 | ************************************************************* | |
515 | * MODIFICATION HISTORY : | |
516 | **************************************************************/ | |
a2c8cfef | 517 | int gpio_pm_wakeup_request(unsigned gpio, unsigned char type) |
1394f032 BW |
518 | { |
519 | unsigned long flags; | |
520 | ||
521 | if ((check_gpio(gpio) < 0) || !type) | |
522 | return -EINVAL; | |
523 | ||
6a01f230 | 524 | local_irq_save_hw(flags); |
1394f032 BW |
525 | wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio); |
526 | wakeup_flags_map[gpio] = type; | |
6a01f230 | 527 | local_irq_restore_hw(flags); |
1394f032 BW |
528 | |
529 | return 0; | |
530 | } | |
531 | EXPORT_SYMBOL(gpio_pm_wakeup_request); | |
532 | ||
a2c8cfef | 533 | void gpio_pm_wakeup_free(unsigned gpio) |
1394f032 BW |
534 | { |
535 | unsigned long flags; | |
536 | ||
537 | if (check_gpio(gpio) < 0) | |
538 | return; | |
539 | ||
6a01f230 | 540 | local_irq_save_hw(flags); |
1394f032 BW |
541 | |
542 | wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); | |
543 | ||
6a01f230 | 544 | local_irq_restore_hw(flags); |
1394f032 BW |
545 | } |
546 | EXPORT_SYMBOL(gpio_pm_wakeup_free); | |
547 | ||
a2c8cfef | 548 | static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type) |
1394f032 BW |
549 | { |
550 | port_setup(gpio, GPIO_USAGE); | |
551 | set_gpio_dir(gpio, 0); | |
552 | set_gpio_inen(gpio, 1); | |
553 | ||
554 | if (type & (PM_WAKE_RISING | PM_WAKE_FALLING)) | |
555 | set_gpio_edge(gpio, 1); | |
556 | else | |
557 | set_gpio_edge(gpio, 0); | |
558 | ||
559 | if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES)) | |
560 | set_gpio_both(gpio, 1); | |
561 | else | |
562 | set_gpio_both(gpio, 0); | |
563 | ||
564 | if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW))) | |
565 | set_gpio_polar(gpio, 1); | |
566 | else | |
567 | set_gpio_polar(gpio, 0); | |
568 | ||
569 | SSYNC(); | |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
1efc80b5 | 574 | u32 bfin_pm_standby_setup(void) |
1394f032 | 575 | { |
1394f032 BW |
576 | u16 bank, mask, i, gpio; |
577 | ||
1f83b8f1 | 578 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { |
1394f032 BW |
579 | mask = wakeup_map[gpio_bank(i)]; |
580 | bank = gpio_bank(i); | |
581 | ||
f556309e MF |
582 | gpio_bank_saved[bank].maskb = gpio_array[bank]->maskb; |
583 | gpio_array[bank]->maskb = 0; | |
1394f032 BW |
584 | |
585 | if (mask) { | |
269647dc | 586 | #if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) |
1394f032 BW |
587 | gpio_bank_saved[bank].fer = *port_fer[bank]; |
588 | #endif | |
f556309e MF |
589 | gpio_bank_saved[bank].inen = gpio_array[bank]->inen; |
590 | gpio_bank_saved[bank].polar = gpio_array[bank]->polar; | |
591 | gpio_bank_saved[bank].dir = gpio_array[bank]->dir; | |
592 | gpio_bank_saved[bank].edge = gpio_array[bank]->edge; | |
593 | gpio_bank_saved[bank].both = gpio_array[bank]->both; | |
c58c2140 MH |
594 | gpio_bank_saved[bank].reserved = |
595 | reserved_gpio_map[bank]; | |
1394f032 BW |
596 | |
597 | gpio = i; | |
598 | ||
599 | while (mask) { | |
cfefe3c6 MH |
600 | if ((mask & 1) && (wakeup_flags_map[gpio] != |
601 | PM_WAKE_IGNORE)) { | |
c58c2140 | 602 | reserved_gpio_map[gpio_bank(gpio)] |= |
581d62ab MH |
603 | gpio_bit(gpio); |
604 | bfin_gpio_wakeup_type(gpio, | |
605 | wakeup_flags_map[gpio]); | |
1394f032 BW |
606 | set_gpio_data(gpio, 0); /*Clear*/ |
607 | } | |
608 | gpio++; | |
609 | mask >>= 1; | |
610 | } | |
611 | ||
cfefe3c6 | 612 | bfin_internal_set_wake(sic_iwr_irqs[bank], 1); |
f556309e | 613 | gpio_array[bank]->maskb_set = wakeup_map[gpio_bank(i)]; |
1394f032 BW |
614 | } |
615 | } | |
616 | ||
2b39331a MH |
617 | AWA_DUMMY_READ(maskb_set); |
618 | ||
cfefe3c6 | 619 | return 0; |
1394f032 BW |
620 | } |
621 | ||
1efc80b5 | 622 | void bfin_pm_standby_restore(void) |
1394f032 BW |
623 | { |
624 | u16 bank, mask, i; | |
625 | ||
1f83b8f1 | 626 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { |
1394f032 BW |
627 | mask = wakeup_map[gpio_bank(i)]; |
628 | bank = gpio_bank(i); | |
629 | ||
630 | if (mask) { | |
269647dc | 631 | #if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) |
1394f032 BW |
632 | *port_fer[bank] = gpio_bank_saved[bank].fer; |
633 | #endif | |
f556309e MF |
634 | gpio_array[bank]->inen = gpio_bank_saved[bank].inen; |
635 | gpio_array[bank]->dir = gpio_bank_saved[bank].dir; | |
636 | gpio_array[bank]->polar = gpio_bank_saved[bank].polar; | |
637 | gpio_array[bank]->edge = gpio_bank_saved[bank].edge; | |
638 | gpio_array[bank]->both = gpio_bank_saved[bank].both; | |
581d62ab | 639 | |
c58c2140 MH |
640 | reserved_gpio_map[bank] = |
641 | gpio_bank_saved[bank].reserved; | |
cfefe3c6 | 642 | bfin_internal_set_wake(sic_iwr_irqs[bank], 0); |
1394f032 BW |
643 | } |
644 | ||
f556309e | 645 | gpio_array[bank]->maskb = gpio_bank_saved[bank].maskb; |
1394f032 | 646 | } |
2b39331a | 647 | AWA_DUMMY_READ(maskb); |
1394f032 BW |
648 | } |
649 | ||
1efc80b5 MH |
650 | void bfin_gpio_pm_hibernate_suspend(void) |
651 | { | |
652 | int i, bank; | |
653 | ||
654 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { | |
655 | bank = gpio_bank(i); | |
656 | ||
269647dc | 657 | #if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) |
f556309e | 658 | gpio_bank_saved[bank].fer = *port_fer[bank]; |
269647dc | 659 | #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
f556309e | 660 | gpio_bank_saved[bank].mux = *port_mux[bank]; |
1efc80b5 | 661 | #else |
f556309e MF |
662 | if (bank == 0) |
663 | gpio_bank_saved[bank].mux = bfin_read_PORT_MUX(); | |
1efc80b5 MH |
664 | #endif |
665 | #endif | |
f556309e MF |
666 | gpio_bank_saved[bank].data = gpio_array[bank]->data; |
667 | gpio_bank_saved[bank].inen = gpio_array[bank]->inen; | |
668 | gpio_bank_saved[bank].polar = gpio_array[bank]->polar; | |
669 | gpio_bank_saved[bank].dir = gpio_array[bank]->dir; | |
670 | gpio_bank_saved[bank].edge = gpio_array[bank]->edge; | |
671 | gpio_bank_saved[bank].both = gpio_array[bank]->both; | |
672 | gpio_bank_saved[bank].maska = gpio_array[bank]->maska; | |
1efc80b5 MH |
673 | } |
674 | ||
675 | AWA_DUMMY_READ(maska); | |
676 | } | |
677 | ||
678 | void bfin_gpio_pm_hibernate_restore(void) | |
679 | { | |
680 | int i, bank; | |
681 | ||
682 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { | |
f556309e | 683 | bank = gpio_bank(i); |
1efc80b5 | 684 | |
269647dc MF |
685 | #if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) |
686 | #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x) | |
f556309e | 687 | *port_mux[bank] = gpio_bank_saved[bank].mux; |
1efc80b5 | 688 | #else |
f556309e MF |
689 | if (bank == 0) |
690 | bfin_write_PORT_MUX(gpio_bank_saved[bank].mux); | |
1efc80b5 | 691 | #endif |
f556309e | 692 | *port_fer[bank] = gpio_bank_saved[bank].fer; |
1efc80b5 | 693 | #endif |
f556309e | 694 | gpio_array[bank]->inen = gpio_bank_saved[bank].inen; |
c03c2a87 MH |
695 | gpio_array[bank]->data_set = gpio_bank_saved[bank].data |
696 | & gpio_bank_saved[bank].dir; | |
f556309e MF |
697 | gpio_array[bank]->dir = gpio_bank_saved[bank].dir; |
698 | gpio_array[bank]->polar = gpio_bank_saved[bank].polar; | |
699 | gpio_array[bank]->edge = gpio_bank_saved[bank].edge; | |
700 | gpio_array[bank]->both = gpio_bank_saved[bank].both; | |
f556309e | 701 | gpio_array[bank]->maska = gpio_bank_saved[bank].maska; |
1efc80b5 MH |
702 | } |
703 | AWA_DUMMY_READ(maska); | |
704 | } | |
705 | ||
706 | ||
1394f032 | 707 | #endif |
269647dc | 708 | #else /* CONFIG_BF54x */ |
1efc80b5 MH |
709 | #ifdef CONFIG_PM |
710 | ||
711 | u32 bfin_pm_standby_setup(void) | |
712 | { | |
713 | return 0; | |
714 | } | |
715 | ||
716 | void bfin_pm_standby_restore(void) | |
717 | { | |
718 | ||
719 | } | |
720 | ||
721 | void bfin_gpio_pm_hibernate_suspend(void) | |
722 | { | |
723 | int i, bank; | |
724 | ||
725 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { | |
726 | bank = gpio_bank(i); | |
727 | ||
f556309e MF |
728 | gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer; |
729 | gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux; | |
730 | gpio_bank_saved[bank].data = gpio_array[bank]->data; | |
f556309e MF |
731 | gpio_bank_saved[bank].inen = gpio_array[bank]->inen; |
732 | gpio_bank_saved[bank].dir = gpio_array[bank]->dir_set; | |
1efc80b5 MH |
733 | } |
734 | } | |
735 | ||
736 | void bfin_gpio_pm_hibernate_restore(void) | |
737 | { | |
738 | int i, bank; | |
739 | ||
740 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { | |
f556309e MF |
741 | bank = gpio_bank(i); |
742 | ||
743 | gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux; | |
744 | gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer; | |
745 | gpio_array[bank]->inen = gpio_bank_saved[bank].inen; | |
746 | gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir; | |
747 | gpio_array[bank]->data_set = gpio_bank_saved[bank].data | |
748 | | gpio_bank_saved[bank].dir; | |
1efc80b5 MH |
749 | } |
750 | } | |
751 | #endif | |
fac3cf43 | 752 | |
a2c8cfef | 753 | unsigned short get_gpio_dir(unsigned gpio) |
fac3cf43 | 754 | { |
f556309e | 755 | return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio))); |
fac3cf43 MH |
756 | } |
757 | EXPORT_SYMBOL(get_gpio_dir); | |
758 | ||
269647dc | 759 | #endif /* CONFIG_BF54x */ |
1394f032 | 760 | |
d2b11a46 MH |
761 | /*********************************************************** |
762 | * | |
763 | * FUNCTIONS: Blackfin Peripheral Resource Allocation | |
764 | * and PortMux Setup | |
765 | * | |
766 | * INPUTS/OUTPUTS: | |
767 | * per Peripheral Identifier | |
768 | * label String | |
769 | * | |
770 | * DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API | |
771 | * | |
772 | * CAUTION: | |
773 | ************************************************************* | |
774 | * MODIFICATION HISTORY : | |
775 | **************************************************************/ | |
776 | ||
d2b11a46 MH |
777 | int peripheral_request(unsigned short per, const char *label) |
778 | { | |
779 | unsigned long flags; | |
780 | unsigned short ident = P_IDENT(per); | |
781 | ||
782 | /* | |
783 | * Don't cares are pins with only one dedicated function | |
784 | */ | |
c58c2140 | 785 | |
d2b11a46 MH |
786 | if (per & P_DONTCARE) |
787 | return 0; | |
788 | ||
789 | if (!(per & P_DEFINED)) | |
790 | return -ENODEV; | |
791 | ||
89e84eea BS |
792 | BUG_ON(ident >= MAX_RESOURCES); |
793 | ||
6a01f230 | 794 | local_irq_save_hw(flags); |
d2b11a46 | 795 | |
6a87d29b MF |
796 | /* If a pin can be muxed as either GPIO or peripheral, make |
797 | * sure it is not already a GPIO pin when we request it. | |
798 | */ | |
799 | if (unlikely(!check_gpio(ident) && | |
800 | reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) { | |
d6879c58 RG |
801 | if (system_state == SYSTEM_BOOTING) |
802 | dump_stack(); | |
d2b11a46 | 803 | printk(KERN_ERR |
6c7ec0ec | 804 | "%s: Peripheral %d is already reserved as GPIO by %s !\n", |
b85d858b | 805 | __func__, ident, get_label(ident)); |
6a01f230 | 806 | local_irq_restore_hw(flags); |
d2b11a46 MH |
807 | return -EBUSY; |
808 | } | |
809 | ||
810 | if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) { | |
811 | ||
d171c233 MF |
812 | /* |
813 | * Pin functions like AMC address strobes my | |
814 | * be requested and used by several drivers | |
815 | */ | |
d2b11a46 | 816 | |
269647dc | 817 | #ifdef CONFIG_BF54x |
f556309e | 818 | if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) { |
6c7ec0ec MF |
819 | #else |
820 | if (!(per & P_MAYSHARE)) { | |
821 | #endif | |
d171c233 MF |
822 | /* |
823 | * Allow that the identical pin function can | |
824 | * be requested from the same driver twice | |
825 | */ | |
d2b11a46 | 826 | |
d171c233 MF |
827 | if (cmp_label(ident, label) == 0) |
828 | goto anyway; | |
d2b11a46 | 829 | |
d6879c58 RG |
830 | if (system_state == SYSTEM_BOOTING) |
831 | dump_stack(); | |
d2b11a46 MH |
832 | printk(KERN_ERR |
833 | "%s: Peripheral %d function %d is already reserved by %s !\n", | |
b85d858b | 834 | __func__, ident, P_FUNCT2MUX(per), get_label(ident)); |
6a01f230 | 835 | local_irq_restore_hw(flags); |
d2b11a46 MH |
836 | return -EBUSY; |
837 | } | |
838 | } | |
839 | ||
d171c233 | 840 | anyway: |
d2b11a46 MH |
841 | reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident); |
842 | ||
f556309e | 843 | portmux_setup(per); |
c58c2140 MH |
844 | port_setup(ident, PERIPHERAL_USAGE); |
845 | ||
6a01f230 | 846 | local_irq_restore_hw(flags); |
c58c2140 MH |
847 | set_label(ident, label); |
848 | ||
849 | return 0; | |
850 | } | |
851 | EXPORT_SYMBOL(peripheral_request); | |
852 | ||
68179371 | 853 | int peripheral_request_list(const unsigned short per[], const char *label) |
c58c2140 MH |
854 | { |
855 | u16 cnt; | |
856 | int ret; | |
857 | ||
858 | for (cnt = 0; per[cnt] != 0; cnt++) { | |
314c98d5 | 859 | |
c58c2140 | 860 | ret = peripheral_request(per[cnt], label); |
314c98d5 MH |
861 | |
862 | if (ret < 0) { | |
d171c233 | 863 | for ( ; cnt > 0; cnt--) |
314c98d5 | 864 | peripheral_free(per[cnt - 1]); |
d171c233 MF |
865 | |
866 | return ret; | |
314c98d5 | 867 | } |
c58c2140 MH |
868 | } |
869 | ||
870 | return 0; | |
871 | } | |
872 | EXPORT_SYMBOL(peripheral_request_list); | |
873 | ||
874 | void peripheral_free(unsigned short per) | |
875 | { | |
876 | unsigned long flags; | |
877 | unsigned short ident = P_IDENT(per); | |
878 | ||
879 | if (per & P_DONTCARE) | |
880 | return; | |
881 | ||
882 | if (!(per & P_DEFINED)) | |
883 | return; | |
884 | ||
6a01f230 | 885 | local_irq_save_hw(flags); |
c58c2140 | 886 | |
d171c233 | 887 | if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) { |
6a01f230 | 888 | local_irq_restore_hw(flags); |
c58c2140 MH |
889 | return; |
890 | } | |
891 | ||
d171c233 | 892 | if (!(per & P_MAYSHARE)) |
c58c2140 | 893 | port_setup(ident, GPIO_USAGE); |
c58c2140 MH |
894 | |
895 | reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident); | |
896 | ||
2acde902 MH |
897 | set_label(ident, "free"); |
898 | ||
6a01f230 | 899 | local_irq_restore_hw(flags); |
c58c2140 MH |
900 | } |
901 | EXPORT_SYMBOL(peripheral_free); | |
902 | ||
68179371 | 903 | void peripheral_free_list(const unsigned short per[]) |
c58c2140 MH |
904 | { |
905 | u16 cnt; | |
d171c233 | 906 | for (cnt = 0; per[cnt] != 0; cnt++) |
c58c2140 | 907 | peripheral_free(per[cnt]); |
c58c2140 MH |
908 | } |
909 | EXPORT_SYMBOL(peripheral_free_list); | |
910 | ||
1394f032 BW |
911 | /*********************************************************** |
912 | * | |
913 | * FUNCTIONS: Blackfin GPIO Driver | |
914 | * | |
915 | * INPUTS/OUTPUTS: | |
d2b11a46 MH |
916 | * gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS |
917 | * label String | |
1394f032 BW |
918 | * |
919 | * DESCRIPTION: Blackfin GPIO Driver API | |
920 | * | |
921 | * CAUTION: | |
922 | ************************************************************* | |
923 | * MODIFICATION HISTORY : | |
924 | **************************************************************/ | |
925 | ||
a4f0b32c | 926 | int bfin_gpio_request(unsigned gpio, const char *label) |
1394f032 BW |
927 | { |
928 | unsigned long flags; | |
929 | ||
930 | if (check_gpio(gpio) < 0) | |
931 | return -EINVAL; | |
932 | ||
6a01f230 | 933 | local_irq_save_hw(flags); |
1394f032 | 934 | |
2acde902 MH |
935 | /* |
936 | * Allow that the identical GPIO can | |
937 | * be requested from the same driver twice | |
938 | * Do nothing and return - | |
939 | */ | |
940 | ||
941 | if (cmp_label(gpio, label) == 0) { | |
6a01f230 | 942 | local_irq_restore_hw(flags); |
2acde902 MH |
943 | return 0; |
944 | } | |
945 | ||
c58c2140 | 946 | if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { |
d6879c58 RG |
947 | if (system_state == SYSTEM_BOOTING) |
948 | dump_stack(); | |
d2b11a46 | 949 | printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", |
9570ff4a | 950 | gpio, get_label(gpio)); |
6a01f230 | 951 | local_irq_restore_hw(flags); |
d2b11a46 MH |
952 | return -EBUSY; |
953 | } | |
954 | if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { | |
d6879c58 RG |
955 | if (system_state == SYSTEM_BOOTING) |
956 | dump_stack(); | |
d2b11a46 MH |
957 | printk(KERN_ERR |
958 | "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", | |
959 | gpio, get_label(gpio)); | |
6a01f230 | 960 | local_irq_restore_hw(flags); |
1394f032 BW |
961 | return -EBUSY; |
962 | } | |
a2be3931 | 963 | if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) { |
9570ff4a GY |
964 | printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!" |
965 | " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio); | |
a2be3931 | 966 | } |
269647dc | 967 | #ifndef CONFIG_BF54x |
a2be3931 MH |
968 | else { /* Reset POLAR setting when acquiring a gpio for the first time */ |
969 | set_gpio_polar(gpio, 0); | |
970 | } | |
971 | #endif | |
d2b11a46 | 972 | |
c58c2140 | 973 | reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio); |
9570ff4a | 974 | set_label(gpio, label); |
1394f032 | 975 | |
6a01f230 | 976 | local_irq_restore_hw(flags); |
1394f032 BW |
977 | |
978 | port_setup(gpio, GPIO_USAGE); | |
979 | ||
980 | return 0; | |
981 | } | |
a4f0b32c | 982 | EXPORT_SYMBOL(bfin_gpio_request); |
1394f032 | 983 | |
a4f0b32c | 984 | void bfin_gpio_free(unsigned gpio) |
1394f032 BW |
985 | { |
986 | unsigned long flags; | |
987 | ||
988 | if (check_gpio(gpio) < 0) | |
989 | return; | |
990 | ||
45c4f2a0 UKK |
991 | might_sleep(); |
992 | ||
6a01f230 | 993 | local_irq_save_hw(flags); |
1394f032 | 994 | |
c58c2140 | 995 | if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { |
d6879c58 RG |
996 | if (system_state == SYSTEM_BOOTING) |
997 | dump_stack(); | |
f85c4abd | 998 | gpio_error(gpio); |
6a01f230 | 999 | local_irq_restore_hw(flags); |
1394f032 BW |
1000 | return; |
1001 | } | |
1002 | ||
c58c2140 | 1003 | reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); |
1394f032 | 1004 | |
2acde902 MH |
1005 | set_label(gpio, "free"); |
1006 | ||
6a01f230 | 1007 | local_irq_restore_hw(flags); |
1394f032 | 1008 | } |
a4f0b32c | 1009 | EXPORT_SYMBOL(bfin_gpio_free); |
1394f032 | 1010 | |
621dd247 MH |
1011 | #ifdef BFIN_SPECIAL_GPIO_BANKS |
1012 | static unsigned short reserved_special_gpio_map[gpio_bank(MAX_RESOURCES)]; | |
1013 | ||
1014 | int bfin_special_gpio_request(unsigned gpio, const char *label) | |
1015 | { | |
1016 | unsigned long flags; | |
1017 | ||
1018 | local_irq_save_hw(flags); | |
1019 | ||
1020 | /* | |
1021 | * Allow that the identical GPIO can | |
1022 | * be requested from the same driver twice | |
1023 | * Do nothing and return - | |
1024 | */ | |
1025 | ||
1026 | if (cmp_label(gpio, label) == 0) { | |
1027 | local_irq_restore_hw(flags); | |
1028 | return 0; | |
1029 | } | |
1030 | ||
1031 | if (unlikely(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { | |
1032 | local_irq_restore_hw(flags); | |
1033 | printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", | |
1034 | gpio, get_label(gpio)); | |
1035 | ||
1036 | return -EBUSY; | |
1037 | } | |
1038 | if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { | |
1039 | local_irq_restore_hw(flags); | |
1040 | printk(KERN_ERR | |
1041 | "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", | |
1042 | gpio, get_label(gpio)); | |
1043 | ||
1044 | return -EBUSY; | |
1045 | } | |
1046 | ||
1047 | reserved_special_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio); | |
1048 | reserved_peri_map[gpio_bank(gpio)] |= gpio_bit(gpio); | |
1049 | ||
1050 | set_label(gpio, label); | |
1051 | local_irq_restore_hw(flags); | |
1052 | port_setup(gpio, GPIO_USAGE); | |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | EXPORT_SYMBOL(bfin_special_gpio_request); | |
1057 | ||
1058 | void bfin_special_gpio_free(unsigned gpio) | |
1059 | { | |
1060 | unsigned long flags; | |
1061 | ||
1062 | might_sleep(); | |
1063 | ||
1064 | local_irq_save_hw(flags); | |
1065 | ||
1066 | if (unlikely(!(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { | |
1067 | gpio_error(gpio); | |
1068 | local_irq_restore_hw(flags); | |
1069 | return; | |
1070 | } | |
1071 | ||
1072 | reserved_special_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); | |
1073 | reserved_peri_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); | |
1074 | set_label(gpio, "free"); | |
1075 | local_irq_restore_hw(flags); | |
1076 | } | |
1077 | EXPORT_SYMBOL(bfin_special_gpio_free); | |
1078 | #endif | |
1079 | ||
1080 | ||
9570ff4a GY |
1081 | int bfin_gpio_irq_request(unsigned gpio, const char *label) |
1082 | { | |
1083 | unsigned long flags; | |
1084 | ||
1085 | if (check_gpio(gpio) < 0) | |
1086 | return -EINVAL; | |
1087 | ||
6a01f230 | 1088 | local_irq_save_hw(flags); |
9570ff4a | 1089 | |
9570ff4a | 1090 | if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { |
d6879c58 RG |
1091 | if (system_state == SYSTEM_BOOTING) |
1092 | dump_stack(); | |
9570ff4a GY |
1093 | printk(KERN_ERR |
1094 | "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", | |
1095 | gpio, get_label(gpio)); | |
6a01f230 | 1096 | local_irq_restore_hw(flags); |
9570ff4a GY |
1097 | return -EBUSY; |
1098 | } | |
1099 | if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) | |
1100 | printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! " | |
1101 | "(Documentation/blackfin/bfin-gpio-notes.txt)\n", | |
1102 | gpio, get_label(gpio)); | |
1103 | ||
1104 | reserved_gpio_irq_map[gpio_bank(gpio)] |= gpio_bit(gpio); | |
1105 | set_label(gpio, label); | |
1106 | ||
6a01f230 | 1107 | local_irq_restore_hw(flags); |
9570ff4a GY |
1108 | |
1109 | port_setup(gpio, GPIO_USAGE); | |
1110 | ||
1111 | return 0; | |
1112 | } | |
1113 | ||
1114 | void bfin_gpio_irq_free(unsigned gpio) | |
1115 | { | |
1116 | unsigned long flags; | |
1117 | ||
1118 | if (check_gpio(gpio) < 0) | |
1119 | return; | |
1120 | ||
6a01f230 | 1121 | local_irq_save_hw(flags); |
9570ff4a GY |
1122 | |
1123 | if (unlikely(!(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { | |
d6879c58 RG |
1124 | if (system_state == SYSTEM_BOOTING) |
1125 | dump_stack(); | |
9570ff4a | 1126 | gpio_error(gpio); |
6a01f230 | 1127 | local_irq_restore_hw(flags); |
9570ff4a GY |
1128 | return; |
1129 | } | |
1130 | ||
1131 | reserved_gpio_irq_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); | |
1132 | ||
1133 | set_label(gpio, "free"); | |
1134 | ||
6a01f230 | 1135 | local_irq_restore_hw(flags); |
9570ff4a GY |
1136 | } |
1137 | ||
f556309e MF |
1138 | static inline void __bfin_gpio_direction_input(unsigned gpio) |
1139 | { | |
269647dc | 1140 | #ifdef CONFIG_BF54x |
f556309e MF |
1141 | gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio); |
1142 | #else | |
1143 | gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); | |
1144 | #endif | |
1145 | gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio); | |
1146 | } | |
1147 | ||
a4f0b32c | 1148 | int bfin_gpio_direction_input(unsigned gpio) |
d2b11a46 MH |
1149 | { |
1150 | unsigned long flags; | |
1151 | ||
acbcd263 MH |
1152 | if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { |
1153 | gpio_error(gpio); | |
1154 | return -EINVAL; | |
1155 | } | |
1156 | ||
6a01f230 | 1157 | local_irq_save_hw(flags); |
f556309e MF |
1158 | __bfin_gpio_direction_input(gpio); |
1159 | AWA_DUMMY_READ(inen); | |
6a01f230 | 1160 | local_irq_restore_hw(flags); |
acbcd263 MH |
1161 | |
1162 | return 0; | |
d2b11a46 | 1163 | } |
a4f0b32c | 1164 | EXPORT_SYMBOL(bfin_gpio_direction_input); |
d2b11a46 | 1165 | |
f556309e | 1166 | void bfin_gpio_irq_prepare(unsigned gpio) |
d2b11a46 | 1167 | { |
269647dc | 1168 | #ifdef CONFIG_BF54x |
d2b11a46 | 1169 | unsigned long flags; |
f556309e | 1170 | #endif |
d2b11a46 | 1171 | |
f556309e | 1172 | port_setup(gpio, GPIO_USAGE); |
d2b11a46 | 1173 | |
269647dc | 1174 | #ifdef CONFIG_BF54x |
6a01f230 | 1175 | local_irq_save_hw(flags); |
f556309e | 1176 | __bfin_gpio_direction_input(gpio); |
6a01f230 | 1177 | local_irq_restore_hw(flags); |
f556309e | 1178 | #endif |
d2b11a46 | 1179 | } |
d2b11a46 | 1180 | |
a4f0b32c | 1181 | void bfin_gpio_set_value(unsigned gpio, int arg) |
d2b11a46 MH |
1182 | { |
1183 | if (arg) | |
f556309e | 1184 | gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio); |
d2b11a46 | 1185 | else |
f556309e | 1186 | gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio); |
d2b11a46 | 1187 | } |
a4f0b32c | 1188 | EXPORT_SYMBOL(bfin_gpio_set_value); |
d2b11a46 | 1189 | |
f556309e | 1190 | int bfin_gpio_direction_output(unsigned gpio, int value) |
affee2b2 MH |
1191 | { |
1192 | unsigned long flags; | |
1193 | ||
f556309e MF |
1194 | if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { |
1195 | gpio_error(gpio); | |
1196 | return -EINVAL; | |
1197 | } | |
affee2b2 | 1198 | |
6a01f230 | 1199 | local_irq_save_hw(flags); |
affee2b2 | 1200 | |
f556309e MF |
1201 | gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); |
1202 | gpio_set_value(gpio, value); | |
269647dc | 1203 | #ifdef CONFIG_BF54x |
f556309e | 1204 | gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio); |
d2b11a46 | 1205 | #else |
f556309e MF |
1206 | gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio); |
1207 | #endif | |
1208 | ||
1209 | AWA_DUMMY_READ(dir); | |
1210 | local_irq_restore_hw(flags); | |
1211 | ||
1212 | return 0; | |
1213 | } | |
1214 | EXPORT_SYMBOL(bfin_gpio_direction_output); | |
d2b11a46 | 1215 | |
a4f0b32c | 1216 | int bfin_gpio_get_value(unsigned gpio) |
803a8d2a | 1217 | { |
269647dc | 1218 | #ifdef CONFIG_BF54x |
f556309e MF |
1219 | return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio))); |
1220 | #else | |
803a8d2a | 1221 | unsigned long flags; |
803a8d2a MH |
1222 | |
1223 | if (unlikely(get_gpio_edge(gpio))) { | |
f556309e | 1224 | int ret; |
6a01f230 | 1225 | local_irq_save_hw(flags); |
803a8d2a MH |
1226 | set_gpio_edge(gpio, 0); |
1227 | ret = get_gpio_data(gpio); | |
1228 | set_gpio_edge(gpio, 1); | |
6a01f230 | 1229 | local_irq_restore_hw(flags); |
803a8d2a MH |
1230 | return ret; |
1231 | } else | |
1232 | return get_gpio_data(gpio); | |
f556309e | 1233 | #endif |
803a8d2a | 1234 | } |
a4f0b32c | 1235 | EXPORT_SYMBOL(bfin_gpio_get_value); |
803a8d2a | 1236 | |
168f1212 MF |
1237 | /* If we are booting from SPI and our board lacks a strong enough pull up, |
1238 | * the core can reset and execute the bootrom faster than the resistor can | |
1239 | * pull the signal logically high. To work around this (common) error in | |
1240 | * board design, we explicitly set the pin back to GPIO mode, force /CS | |
1241 | * high, and wait for the electrons to do their thing. | |
1242 | * | |
1243 | * This function only makes sense to be called from reset code, but it | |
1244 | * lives here as we need to force all the GPIO states w/out going through | |
1245 | * BUG() checks and such. | |
1246 | */ | |
b52dae31 | 1247 | void bfin_reset_boot_spi_cs(unsigned short pin) |
168f1212 | 1248 | { |
b52dae31 | 1249 | unsigned short gpio = P_IDENT(pin); |
4d5f4ed3 | 1250 | port_setup(gpio, GPIO_USAGE); |
f556309e | 1251 | gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio); |
a2c8cfef | 1252 | AWA_DUMMY_READ(data_set); |
168f1212 MF |
1253 | udelay(1); |
1254 | } | |
d2b11a46 | 1255 | |
1545a111 MF |
1256 | #if defined(CONFIG_PROC_FS) |
1257 | static int gpio_proc_read(char *buf, char **start, off_t offset, | |
1258 | int len, int *unused_i, void *unused_v) | |
1259 | { | |
9570ff4a | 1260 | int c, irq, gpio, outlen = 0; |
1545a111 MF |
1261 | |
1262 | for (c = 0; c < MAX_RESOURCES; c++) { | |
9570ff4a GY |
1263 | irq = reserved_gpio_irq_map[gpio_bank(c)] & gpio_bit(c); |
1264 | gpio = reserved_gpio_map[gpio_bank(c)] & gpio_bit(c); | |
1265 | if (!check_gpio(c) && (gpio || irq)) | |
1266 | len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c, | |
1267 | get_label(c), (gpio && irq) ? " *" : "", | |
1268 | get_gpio_dir(c) ? "OUTPUT" : "INPUT"); | |
1545a111 | 1269 | else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c)) |
8eb3e3bf | 1270 | len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c)); |
1545a111 MF |
1271 | else |
1272 | continue; | |
1273 | buf += len; | |
1274 | outlen += len; | |
1275 | } | |
1276 | return outlen; | |
1277 | } | |
1278 | ||
1279 | static __init int gpio_register_proc(void) | |
1280 | { | |
1281 | struct proc_dir_entry *proc_gpio; | |
1282 | ||
1283 | proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL); | |
1284 | if (proc_gpio) | |
1285 | proc_gpio->read_proc = gpio_proc_read; | |
1286 | return proc_gpio != NULL; | |
1287 | } | |
1545a111 MF |
1288 | __initcall(gpio_register_proc); |
1289 | #endif | |
a4f0b32c MH |
1290 | |
1291 | #ifdef CONFIG_GPIOLIB | |
1292 | int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio) | |
1293 | { | |
1294 | return bfin_gpio_direction_input(gpio); | |
1295 | } | |
1296 | ||
1297 | int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level) | |
1298 | { | |
1299 | return bfin_gpio_direction_output(gpio, level); | |
1300 | } | |
1301 | ||
1302 | int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio) | |
1303 | { | |
1304 | return bfin_gpio_get_value(gpio); | |
1305 | } | |
1306 | ||
1307 | void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value) | |
1308 | { | |
a4f0b32c | 1309 | return bfin_gpio_set_value(gpio, value); |
a4f0b32c MH |
1310 | } |
1311 | ||
1312 | int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio) | |
1313 | { | |
1314 | return bfin_gpio_request(gpio, chip->label); | |
1315 | } | |
1316 | ||
1317 | void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio) | |
1318 | { | |
1319 | return bfin_gpio_free(gpio); | |
1320 | } | |
1321 | ||
1322 | static struct gpio_chip bfin_chip = { | |
edd07992 | 1323 | .label = "BFIN-GPIO", |
a4f0b32c MH |
1324 | .direction_input = bfin_gpiolib_direction_input, |
1325 | .get = bfin_gpiolib_get_value, | |
1326 | .direction_output = bfin_gpiolib_direction_output, | |
1327 | .set = bfin_gpiolib_set_value, | |
1328 | .request = bfin_gpiolib_gpio_request, | |
1329 | .free = bfin_gpiolib_gpio_free, | |
1330 | .base = 0, | |
1331 | .ngpio = MAX_BLACKFIN_GPIOS, | |
1332 | }; | |
1333 | ||
1334 | static int __init bfin_gpiolib_setup(void) | |
1335 | { | |
1336 | return gpiochip_add(&bfin_chip); | |
1337 | } | |
1338 | arch_initcall(bfin_gpiolib_setup); | |
1339 | #endif |