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29440a2b BS |
1 | /* |
2 | * Blackfin CPLB initialization | |
3 | * | |
4 | * Copyright 2004-2007 Analog Devices Inc. | |
5 | * | |
6 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, see the file COPYING, or write | |
20 | * to the Free Software Foundation, Inc., | |
21 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | */ | |
23 | #include <linux/module.h> | |
24 | ||
25 | #include <asm/blackfin.h> | |
3bebca2d | 26 | #include <asm/cplb.h> |
29440a2b BS |
27 | #include <asm/cplbinit.h> |
28 | ||
99d95bbd | 29 | #define CPLB_MEM CONFIG_MAX_MEM_SIZE |
a086ee22 | 30 | |
0e184c6b MF |
31 | /* |
32 | * Number of required data CPLB switchtable entries | |
33 | * MEMSIZE / 4 (we mostly install 4M page size CPLBs | |
34 | * approx 16 for smaller 1MB page size CPLBs for allignment purposes | |
35 | * 1 for L1 Data Memory | |
36 | * possibly 1 for L2 Data Memory | |
37 | * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO | |
38 | * 1 for ASYNC Memory | |
39 | */ | |
a086ee22 | 40 | #define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \ |
0e184c6b MF |
41 | + ASYNC_MEMORY_CPLB_COVERAGE) * 2) |
42 | ||
43 | /* | |
44 | * Number of required instruction CPLB switchtable entries | |
45 | * MEMSIZE / 4 (we mostly install 4M page size CPLBs | |
46 | * approx 12 for smaller 1MB page size CPLBs for allignment purposes | |
47 | * 1 for L1 Instruction Memory | |
48 | * possibly 1 for L2 Instruction Memory | |
49 | * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO | |
50 | */ | |
a086ee22 | 51 | #define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2) |
0e184c6b MF |
52 | |
53 | ||
81a487a5 MF |
54 | u_long icplb_table[MAX_CPLBS + 1]; |
55 | u_long dcplb_table[MAX_CPLBS + 1]; | |
29440a2b BS |
56 | |
57 | #ifdef CONFIG_CPLB_SWITCH_TAB_L1 | |
81a487a5 | 58 | # define PDT_ATTR __attribute__((l1_data)) |
29440a2b | 59 | #else |
81a487a5 MF |
60 | # define PDT_ATTR |
61 | #endif | |
29440a2b | 62 | |
81a487a5 MF |
63 | u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR; |
64 | u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR; | |
29440a2b BS |
65 | |
66 | #ifdef CONFIG_CPLB_INFO | |
81a487a5 MF |
67 | u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR; |
68 | u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR; | |
69 | #endif | |
29440a2b BS |
70 | |
71 | struct s_cplb { | |
72 | struct cplb_tab init_i; | |
73 | struct cplb_tab init_d; | |
74 | struct cplb_tab switch_i; | |
75 | struct cplb_tab switch_d; | |
76 | }; | |
77 | ||
3bebca2d | 78 | #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) |
29440a2b BS |
79 | static struct cplb_desc cplb_data[] = { |
80 | { | |
81 | .start = 0, | |
82 | .end = SIZE_1K, | |
83 | .psize = SIZE_1K, | |
84 | .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, | |
85 | .i_conf = SDRAM_OOPS, | |
86 | .d_conf = SDRAM_OOPS, | |
87 | #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO) | |
88 | .valid = 1, | |
89 | #else | |
90 | .valid = 0, | |
91 | #endif | |
c3a9f435 | 92 | .name = "Zero Pointer Guard Page", |
29440a2b BS |
93 | }, |
94 | { | |
95 | .start = L1_CODE_START, | |
96 | .end = L1_CODE_START + L1_CODE_LENGTH, | |
97 | .psize = SIZE_4M, | |
98 | .attr = INITIAL_T | SWITCH_T | I_CPLB, | |
99 | .i_conf = L1_IMEMORY, | |
100 | .d_conf = 0, | |
101 | .valid = 1, | |
102 | .name = "L1 I-Memory", | |
103 | }, | |
104 | { | |
105 | .start = L1_DATA_A_START, | |
106 | .end = L1_DATA_B_START + L1_DATA_B_LENGTH, | |
107 | .psize = SIZE_4M, | |
108 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | |
109 | .i_conf = 0, | |
110 | .d_conf = L1_DMEMORY, | |
111 | #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0)) | |
112 | .valid = 1, | |
113 | #else | |
114 | .valid = 0, | |
115 | #endif | |
116 | .name = "L1 D-Memory", | |
117 | }, | |
118 | { | |
119 | .start = 0, | |
120 | .end = 0, /* dynamic */ | |
121 | .psize = 0, | |
122 | .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, | |
c3a9f435 MF |
123 | .i_conf = SDRAM_IGENERIC, |
124 | .d_conf = SDRAM_DGENERIC, | |
29440a2b | 125 | .valid = 1, |
c3a9f435 | 126 | .name = "Kernel Memory", |
29440a2b BS |
127 | }, |
128 | { | |
129 | .start = 0, /* dynamic */ | |
130 | .end = 0, /* dynamic */ | |
131 | .psize = 0, | |
132 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | |
c3a9f435 MF |
133 | .i_conf = SDRAM_IGENERIC, |
134 | .d_conf = SDRAM_DNON_CHBL, | |
29440a2b | 135 | .valid = 1, |
c3a9f435 | 136 | .name = "uClinux MTD Memory", |
29440a2b BS |
137 | }, |
138 | { | |
139 | .start = 0, /* dynamic */ | |
140 | .end = 0, /* dynamic */ | |
141 | .psize = SIZE_1M, | |
142 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | |
143 | .d_conf = SDRAM_DNON_CHBL, | |
144 | .valid = 1, | |
c3a9f435 | 145 | .name = "Uncached DMA Zone", |
29440a2b BS |
146 | }, |
147 | { | |
148 | .start = 0, /* dynamic */ | |
149 | .end = 0, /* dynamic */ | |
150 | .psize = 0, | |
151 | .attr = SWITCH_T | D_CPLB, | |
152 | .i_conf = 0, /* dynamic */ | |
153 | .d_conf = 0, /* dynamic */ | |
154 | .valid = 1, | |
c3a9f435 | 155 | .name = "Reserved Memory", |
29440a2b BS |
156 | }, |
157 | { | |
158 | .start = ASYNC_BANK0_BASE, | |
159 | .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE, | |
160 | .psize = 0, | |
161 | .attr = SWITCH_T | D_CPLB, | |
162 | .d_conf = SDRAM_EBIU, | |
163 | .valid = 1, | |
c3a9f435 | 164 | .name = "Asynchronous Memory Banks", |
29440a2b BS |
165 | }, |
166 | { | |
c3a9f435 MF |
167 | .start = L2_START, |
168 | .end = L2_START + L2_LENGTH, | |
29440a2b | 169 | .psize = SIZE_1M, |
c3a9f435 | 170 | .attr = SWITCH_T | I_CPLB | D_CPLB, |
29440a2b BS |
171 | .i_conf = L2_MEMORY, |
172 | .d_conf = L2_MEMORY, | |
07aa7be5 | 173 | .valid = (L2_LENGTH > 0), |
29440a2b | 174 | .name = "L2 Memory", |
c3a9f435 MF |
175 | }, |
176 | { | |
177 | .start = BOOT_ROM_START, | |
178 | .end = BOOT_ROM_START + BOOT_ROM_LENGTH, | |
179 | .psize = SIZE_1M, | |
180 | .attr = SWITCH_T | I_CPLB | D_CPLB, | |
181 | .i_conf = SDRAM_IGENERIC, | |
182 | .d_conf = SDRAM_DGENERIC, | |
183 | .valid = 1, | |
184 | .name = "On-Chip BootROM", | |
185 | }, | |
29440a2b BS |
186 | }; |
187 | ||
188 | static u16 __init lock_kernel_check(u32 start, u32 end) | |
189 | { | |
6a3f0b46 RG |
190 | if ((end <= (u32) _end && end >= (u32)_stext) || |
191 | (start <= (u32) _end && start >= (u32)_stext)) | |
29440a2b BS |
192 | return IN_KERNEL; |
193 | return 0; | |
194 | } | |
195 | ||
196 | static unsigned short __init | |
197 | fill_cplbtab(struct cplb_tab *table, | |
198 | unsigned long start, unsigned long end, | |
199 | unsigned long block_size, unsigned long cplb_data) | |
200 | { | |
201 | int i; | |
202 | ||
203 | switch (block_size) { | |
204 | case SIZE_4M: | |
205 | i = 3; | |
206 | break; | |
207 | case SIZE_1M: | |
208 | i = 2; | |
209 | break; | |
210 | case SIZE_4K: | |
211 | i = 1; | |
212 | break; | |
213 | case SIZE_1K: | |
214 | default: | |
215 | i = 0; | |
216 | break; | |
217 | } | |
218 | ||
219 | cplb_data = (cplb_data & ~(3 << 16)) | (i << 16); | |
220 | ||
221 | while ((start < end) && (table->pos < table->size)) { | |
222 | ||
223 | table->tab[table->pos++] = start; | |
224 | ||
225 | if (lock_kernel_check(start, start + block_size) == IN_KERNEL) | |
226 | table->tab[table->pos++] = | |
227 | cplb_data | CPLB_LOCK | CPLB_DIRTY; | |
228 | else | |
229 | table->tab[table->pos++] = cplb_data; | |
230 | ||
231 | start += block_size; | |
232 | } | |
233 | return 0; | |
234 | } | |
235 | ||
236 | static unsigned short __init | |
237 | close_cplbtab(struct cplb_tab *table) | |
238 | { | |
239 | ||
240 | while (table->pos < table->size) { | |
241 | ||
242 | table->tab[table->pos++] = 0; | |
243 | table->tab[table->pos++] = 0; /* !CPLB_VALID */ | |
244 | } | |
245 | return 0; | |
246 | } | |
247 | ||
248 | /* helper function */ | |
8d0a6003 BW |
249 | static void __init |
250 | __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end) | |
29440a2b BS |
251 | { |
252 | if (cplb_data[i].psize) { | |
253 | fill_cplbtab(t, | |
254 | cplb_data[i].start, | |
255 | cplb_data[i].end, | |
256 | cplb_data[i].psize, | |
257 | cplb_data[i].i_conf); | |
258 | } else { | |
3bebca2d | 259 | #if defined(CONFIG_BFIN_ICACHE) |
1aafd909 | 260 | if (ANOMALY_05000263 && i == SDRAM_KERN) { |
29440a2b BS |
261 | fill_cplbtab(t, |
262 | cplb_data[i].start, | |
263 | cplb_data[i].end, | |
264 | SIZE_4M, | |
265 | cplb_data[i].i_conf); | |
266 | } else | |
267 | #endif | |
268 | { | |
269 | fill_cplbtab(t, | |
270 | cplb_data[i].start, | |
271 | a_start, | |
272 | SIZE_1M, | |
273 | cplb_data[i].i_conf); | |
274 | fill_cplbtab(t, | |
275 | a_start, | |
276 | a_end, | |
277 | SIZE_4M, | |
278 | cplb_data[i].i_conf); | |
279 | fill_cplbtab(t, a_end, | |
280 | cplb_data[i].end, | |
281 | SIZE_1M, | |
282 | cplb_data[i].i_conf); | |
283 | } | |
284 | } | |
285 | } | |
286 | ||
8d0a6003 BW |
287 | static void __init |
288 | __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end) | |
29440a2b BS |
289 | { |
290 | if (cplb_data[i].psize) { | |
291 | fill_cplbtab(t, | |
292 | cplb_data[i].start, | |
293 | cplb_data[i].end, | |
294 | cplb_data[i].psize, | |
295 | cplb_data[i].d_conf); | |
296 | } else { | |
297 | fill_cplbtab(t, | |
298 | cplb_data[i].start, | |
299 | a_start, SIZE_1M, | |
300 | cplb_data[i].d_conf); | |
301 | fill_cplbtab(t, a_start, | |
302 | a_end, SIZE_4M, | |
303 | cplb_data[i].d_conf); | |
304 | fill_cplbtab(t, a_end, | |
305 | cplb_data[i].end, | |
306 | SIZE_1M, | |
307 | cplb_data[i].d_conf); | |
308 | } | |
309 | } | |
310 | ||
5b04f271 | 311 | void __init generate_cplb_tables(void) |
29440a2b BS |
312 | { |
313 | ||
314 | u16 i, j, process; | |
315 | u32 a_start, a_end, as, ae, as_1m; | |
316 | ||
317 | struct cplb_tab *t_i = NULL; | |
318 | struct cplb_tab *t_d = NULL; | |
319 | struct s_cplb cplb; | |
320 | ||
8cab0288 MF |
321 | printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n"); |
322 | ||
29440a2b BS |
323 | cplb.init_i.size = MAX_CPLBS; |
324 | cplb.init_d.size = MAX_CPLBS; | |
325 | cplb.switch_i.size = MAX_SWITCH_I_CPLBS; | |
326 | cplb.switch_d.size = MAX_SWITCH_D_CPLBS; | |
327 | ||
328 | cplb.init_i.pos = 0; | |
329 | cplb.init_d.pos = 0; | |
330 | cplb.switch_i.pos = 0; | |
331 | cplb.switch_d.pos = 0; | |
332 | ||
333 | cplb.init_i.tab = icplb_table; | |
334 | cplb.init_d.tab = dcplb_table; | |
335 | cplb.switch_i.tab = ipdt_table; | |
336 | cplb.switch_d.tab = dpdt_table; | |
337 | ||
338 | cplb_data[SDRAM_KERN].end = memory_end; | |
339 | ||
340 | #ifdef CONFIG_MTD_UCLINUX | |
341 | cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start; | |
342 | cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size; | |
343 | cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0; | |
344 | # if defined(CONFIG_ROMFS_FS) | |
345 | cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB; | |
346 | ||
347 | /* | |
348 | * The ROMFS_FS size is often not multiple of 1MB. | |
349 | * This can cause multiple CPLB sets covering the same memory area. | |
350 | * This will then cause multiple CPLB hit exceptions. | |
351 | * Workaround: We ensure a contiguous memory area by extending the kernel | |
352 | * memory section over the mtd section. | |
353 | * For ROMFS_FS memory must be covered with ICPLBs anyways. | |
354 | * So there is no difference between kernel and mtd memory setup. | |
355 | */ | |
356 | ||
357 | cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;; | |
358 | cplb_data[SDRAM_RAM_MTD].valid = 0; | |
359 | ||
360 | # endif | |
361 | #else | |
362 | cplb_data[SDRAM_RAM_MTD].valid = 0; | |
363 | #endif | |
364 | ||
365 | cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION; | |
366 | cplb_data[SDRAM_DMAZ].end = _ramend; | |
367 | ||
368 | cplb_data[RES_MEM].start = _ramend; | |
369 | cplb_data[RES_MEM].end = physical_mem_end; | |
370 | ||
371 | if (reserved_mem_dcache_on) | |
372 | cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC; | |
373 | else | |
374 | cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL; | |
375 | ||
376 | if (reserved_mem_icache_on) | |
377 | cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC; | |
378 | else | |
379 | cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL; | |
380 | ||
c3a9f435 | 381 | for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) { |
29440a2b BS |
382 | if (!cplb_data[i].valid) |
383 | continue; | |
384 | ||
385 | as_1m = cplb_data[i].start % SIZE_1M; | |
386 | ||
387 | /* We need to make sure all sections are properly 1M aligned | |
388 | * However between Kernel Memory and the Kernel mtd section, depending on the | |
389 | * rootfs size, there can be overlapping memory areas. | |
390 | */ | |
391 | ||
392 | if (as_1m && i != L1I_MEM && i != L1D_MEM) { | |
393 | #ifdef CONFIG_MTD_UCLINUX | |
394 | if (i == SDRAM_RAM_MTD) { | |
395 | if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start) | |
396 | cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M; | |
397 | else | |
398 | cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)); | |
399 | } else | |
400 | #endif | |
401 | printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n", | |
402 | cplb_data[i].name, cplb_data[i].start); | |
403 | } | |
404 | ||
405 | as = cplb_data[i].start % SIZE_4M; | |
406 | ae = cplb_data[i].end % SIZE_4M; | |
407 | ||
408 | if (as) | |
409 | a_start = cplb_data[i].start + (SIZE_4M - (as)); | |
410 | else | |
411 | a_start = cplb_data[i].start; | |
412 | ||
413 | a_end = cplb_data[i].end - ae; | |
414 | ||
415 | for (j = INITIAL_T; j <= SWITCH_T; j++) { | |
416 | ||
417 | switch (j) { | |
418 | case INITIAL_T: | |
419 | if (cplb_data[i].attr & INITIAL_T) { | |
420 | t_i = &cplb.init_i; | |
421 | t_d = &cplb.init_d; | |
422 | process = 1; | |
423 | } else | |
424 | process = 0; | |
425 | break; | |
426 | case SWITCH_T: | |
427 | if (cplb_data[i].attr & SWITCH_T) { | |
428 | t_i = &cplb.switch_i; | |
429 | t_d = &cplb.switch_d; | |
430 | process = 1; | |
431 | } else | |
432 | process = 0; | |
433 | break; | |
434 | default: | |
435 | process = 0; | |
436 | break; | |
437 | } | |
438 | ||
439 | if (!process) | |
440 | continue; | |
441 | if (cplb_data[i].attr & I_CPLB) | |
442 | __fill_code_cplbtab(t_i, i, a_start, a_end); | |
443 | ||
444 | if (cplb_data[i].attr & D_CPLB) | |
445 | __fill_data_cplbtab(t_d, i, a_start, a_end); | |
446 | } | |
447 | } | |
448 | ||
449 | /* close tables */ | |
450 | ||
451 | close_cplbtab(&cplb.init_i); | |
452 | close_cplbtab(&cplb.init_d); | |
453 | ||
454 | cplb.init_i.tab[cplb.init_i.pos] = -1; | |
455 | cplb.init_d.tab[cplb.init_d.pos] = -1; | |
456 | cplb.switch_i.tab[cplb.switch_i.pos] = -1; | |
457 | cplb.switch_d.tab[cplb.switch_d.pos] = -1; | |
458 | ||
459 | } | |
460 | ||
461 | #endif | |
462 |