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Blackfin arch: unify differences between our diff head.S files -- no functional changes
[deliverable/linux.git] / arch / blackfin / kernel / setup.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/kernel/setup.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/delay.h>
31#include <linux/console.h>
32#include <linux/bootmem.h>
33#include <linux/seq_file.h>
34#include <linux/cpu.h>
35#include <linux/module.h>
1394f032
BW		 36#include <linux/tty.h>
37
38#include <linux/ext2_fs.h>
39#include <linux/cramfs_fs.h>
40#include <linux/romfs_fs.h>
41
42#include <asm/cacheflush.h>
43#include <asm/blackfin.h>
44#include <asm/cplbinit.h>
45
a9c59c27
MF		 46u16 _bfin_swrst;
47
1394f032
BW		 48unsigned long memory_start, memory_end, physical_mem_end;
49unsigned long reserved_mem_dcache_on;
50unsigned long reserved_mem_icache_on;
51EXPORT_SYMBOL(memory_start);
52EXPORT_SYMBOL(memory_end);
53EXPORT_SYMBOL(physical_mem_end);
54EXPORT_SYMBOL(_ramend);
55
56#ifdef CONFIG_MTD_UCLINUX
57unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
58unsigned long _ebss;
59EXPORT_SYMBOL(memory_mtd_end);
60EXPORT_SYMBOL(memory_mtd_start);
61EXPORT_SYMBOL(mtd_size);
62#endif
63
64char command_line[COMMAND_LINE_SIZE];
65
66#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
67static void generate_cpl_tables(void);
68#endif
69
70void __init bf53x_cache_init(void)
71{
72#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
73 generate_cpl_tables();
74#endif
75
76#ifdef CONFIG_BLKFIN_CACHE
77 bfin_icache_init();
78 printk(KERN_INFO "Instruction Cache Enabled\n");
79#endif
80
81#ifdef CONFIG_BLKFIN_DCACHE
82 bfin_dcache_init();
83 printk(KERN_INFO "Data Cache Enabled"
84# if defined CONFIG_BLKFIN_WB
85 " (write-back)"
86# elif defined CONFIG_BLKFIN_WT
87 " (write-through)"
88# endif
89 "\n");
90#endif
91}
92
93void bf53x_relocate_l1_mem(void)
94{
95 unsigned long l1_code_length;
96 unsigned long l1_data_a_length;
97 unsigned long l1_data_b_length;
98
99 l1_code_length = _etext_l1 - _stext_l1;
100 if (l1_code_length > L1_CODE_LENGTH)
101 l1_code_length = L1_CODE_LENGTH;
102 /* cannot complain as printk is not available as yet.
103 * But we can continue booting and complain later!
104 */
105
106 /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
107 dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
108
109 l1_data_a_length = _ebss_l1 - _sdata_l1;
110 if (l1_data_a_length > L1_DATA_A_LENGTH)
111 l1_data_a_length = L1_DATA_A_LENGTH;
112
113 /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */
114 dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
115
116 l1_data_b_length = _ebss_b_l1 - _sdata_b_l1;
117 if (l1_data_b_length > L1_DATA_B_LENGTH)
118 l1_data_b_length = L1_DATA_B_LENGTH;
119
120 /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */
121 dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
122 l1_data_a_length, l1_data_b_length);
123
124}
125
126/*
127 * Initial parsing of the command line. Currently, we support:
128 * - Controlling the linux memory size: mem=xxx[KMG]
129 * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
130 * $ -> reserved memory is dcacheable
131 * # -> reserved memory is icacheable
132 */
133static __init void parse_cmdline_early(char *cmdline_p)
134{
135 char c = ' ', *to = cmdline_p;
136 unsigned int memsize;
137 for (;;) {
138 if (c == ' ') {
139
140 if (!memcmp(to, "mem=", 4)) {
141 to += 4;
142 memsize = memparse(to, &to);
143 if (memsize)
144 _ramend = memsize;
145
146 } else if (!memcmp(to, "max_mem=", 8)) {
147 to += 8;
148 memsize = memparse(to, &to);
149 if (memsize) {
150 physical_mem_end = memsize;
151 if (*to != ' ') {
152 if (*to == '$'
153 || *(to + 1) == '$')
154 reserved_mem_dcache_on =
155 1;
156 if (*to == '#'
157 || *(to + 1) == '#')
158 reserved_mem_icache_on =
159 1;
160 }
161 }
162 }
163
164 }
165 c = *(to++);
166 if (!c)
167 break;
168 }
169}
170
171void __init setup_arch(char **cmdline_p)
172{
173 int bootmap_size;
174 unsigned long l1_length, sclk, cclk;
175#ifdef CONFIG_MTD_UCLINUX
176 unsigned long mtd_phys = 0;
177#endif
178
6e537e93
MH		 179#ifdef CONFIG_DUMMY_CONSOLE
180 conswitchp = &dummy_con;
181#endif
1394f032
BW		 182 cclk = get_cclk();
183 sclk = get_sclk();
184
185#if !defined(CONFIG_BFIN_KERNEL_CLOCK) && defined(ANOMALY_05000273)
186 if (cclk == sclk)
187 panic("ANOMALY 05000273, SCLK can not be same as CCLK");
188#endif
189
190#if defined(ANOMALY_05000266)
191 bfin_read_IMDMA_D0_IRQ_STATUS();
192 bfin_read_IMDMA_D1_IRQ_STATUS();
193#endif
194
195#ifdef DEBUG_SERIAL_EARLY_INIT
196 bfin_console_init(); /* early console registration */
197 /* this give a chance to get printk() working before crash. */
198#endif
199
200#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
201 /* we need to initialize the Flashrom device here since we might
202 * do things with flash early on in the boot
203 */
204 flash_probe();
205#endif
206
207#if defined(CONFIG_CMDLINE_BOOL)
208 memset(command_line, 0, sizeof(command_line));
209 strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
210 command_line[sizeof(command_line) - 1] = 0;
211#endif
212
213 /* Keep a copy of command line */
214 *cmdline_p = &command_line[0];
215 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
216 boot_command_line[COMMAND_LINE_SIZE - 1] = 0;
217
218 /* setup memory defaults from the user config */
219 physical_mem_end = 0;
220 _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
221
222 parse_cmdline_early(&command_line[0]);
223
224 if (physical_mem_end == 0)
225 physical_mem_end = _ramend;
226
227 /* by now the stack is part of the init task */
228 memory_end = _ramend - DMA_UNCACHED_REGION;
229
230 _ramstart = (unsigned long)__bss_stop;
231 memory_start = PAGE_ALIGN(_ramstart);
232
233#if defined(CONFIG_MTD_UCLINUX)
234 /* generic memory mapped MTD driver */
235 memory_mtd_end = memory_end;
236
237 mtd_phys = _ramstart;
238 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
239
240# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
241 if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
242 mtd_size =
243 PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
244# endif
245
246# if defined(CONFIG_CRAMFS)
247 if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
248 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
249# endif
250
251# if defined(CONFIG_ROMFS_FS)
252 if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
253 && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
254 mtd_size =
255 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
256# if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
257 /* Due to a Hardware Anomaly we need to limit the size of usable
258 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
259 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
260 */
261# if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
262 if (memory_end >= 56 * 1024 * 1024)
263 memory_end = 56 * 1024 * 1024;
264# else
265 if (memory_end >= 60 * 1024 * 1024)
266 memory_end = 60 * 1024 * 1024;
267# endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
268# endif /* ANOMALY_05000263 */
269# endif /* CONFIG_ROMFS_FS */
270
271 memory_end -= mtd_size;
272
273 if (mtd_size == 0) {
274 console_init();
275 panic("Don't boot kernel without rootfs attached.\n");
276 }
277
278 /* Relocate MTD image to the top of memory after the uncached memory area */
279 dma_memcpy((char *)memory_end, __bss_stop, mtd_size);
280
281 memory_mtd_start = memory_end;
282 _ebss = memory_mtd_start; /* define _ebss for compatible */
283#endif /* CONFIG_MTD_UCLINUX */
284
285#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
286 /* Due to a Hardware Anomaly we need to limit the size of usable
287 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
288 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
289 */
290#if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
291 if (memory_end >= 56 * 1024 * 1024)
292 memory_end = 56 * 1024 * 1024;
293#else
294 if (memory_end >= 60 * 1024 * 1024)
295 memory_end = 60 * 1024 * 1024;
296#endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
297 printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
298#endif /* ANOMALY_05000263 */
299
300#if !defined(CONFIG_MTD_UCLINUX)
301 memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
302#endif
303 init_mm.start_code = (unsigned long)_stext;
304 init_mm.end_code = (unsigned long)_etext;
305 init_mm.end_data = (unsigned long)_edata;
306 init_mm.brk = (unsigned long)0;
307
308 init_leds();
309
310 printk(KERN_INFO "Blackfin support (C) 2004-2007 Analog Devices, Inc.\n");
311 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
312 if (bfin_revid() != bfin_compiled_revid())
313 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
314 bfin_compiled_revid(), bfin_revid());
315 if (bfin_revid() < SUPPORTED_REVID)
316 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
317 CPU, bfin_revid());
318 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
319
320 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n",
321 cclk / 1000000, sclk / 1000000);
322
323#if defined(ANOMALY_05000273)
324 if ((cclk >> 1) <= sclk)
325 printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
326#endif
327
328 printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
329 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
330
331 printk(KERN_INFO "Memory map:\n"
332 KERN_INFO " text = 0x%p-0x%p\n"
333 KERN_INFO " init = 0x%p-0x%p\n"
334 KERN_INFO " data = 0x%p-0x%p\n"
335 KERN_INFO " stack = 0x%p-0x%p\n"
336 KERN_INFO " bss = 0x%p-0x%p\n"
337 KERN_INFO " available = 0x%p-0x%p\n"
338#ifdef CONFIG_MTD_UCLINUX
339 KERN_INFO " rootfs = 0x%p-0x%p\n"
340#endif
341#if DMA_UNCACHED_REGION > 0
342 KERN_INFO " DMA Zone = 0x%p-0x%p\n"
343#endif
344 , _stext, _etext,
345 __init_begin, __init_end,
346 _sdata, _edata,
347 (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000),
348 __bss_start, __bss_stop,
349 (void*)_ramstart, (void*)memory_end
350#ifdef CONFIG_MTD_UCLINUX
351 , (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size)
352#endif
353#if DMA_UNCACHED_REGION > 0
354 , (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend)
355#endif
356 );
357
358 /*
359 * give all the memory to the bootmap allocator, tell it to put the
360 * boot mem_map at the start of memory
361 */
362 bootmap_size = init_bootmem_node(NODE_DATA(0), memory_start >> PAGE_SHIFT, /* map goes here */
363 PAGE_OFFSET >> PAGE_SHIFT,
364 memory_end >> PAGE_SHIFT);
365 /*
366 * free the usable memory, we have to make sure we do not free
367 * the bootmem bitmap so we then reserve it after freeing it :-)
368 */
369 free_bootmem(memory_start, memory_end - memory_start);
370
371 reserve_bootmem(memory_start, bootmap_size);
372 /*
373 * get kmalloc into gear
374 */
375 paging_init();
376
377 /* check the size of the l1 area */
378 l1_length = _etext_l1 - _stext_l1;
379 if (l1_length > L1_CODE_LENGTH)
380 panic("L1 memory overflow\n");
381
382 l1_length = _ebss_l1 - _sdata_l1;
383 if (l1_length > L1_DATA_A_LENGTH)
384 panic("L1 memory overflow\n");
385
a9c59c27
MF		 386#ifdef BF561_FAMILY
387 _bfin_swrst = bfin_read_SICA_SWRST();
388#else
389 _bfin_swrst = bfin_read_SWRST();
390#endif
391
1394f032
BW		 392 bf53x_cache_init();
393
1394f032
BW		 394 printk(KERN_INFO "Hardware Trace Enabled\n");
395 bfin_write_TBUFCTL(0x03);
396}
397
1394f032
BW		 398static int __init topology_init(void)
399{
400#if defined (CONFIG_BF561)
c0fc525d 401 static struct cpu cpu[2];
1394f032
BW		 402 register_cpu(&cpu[0], 0);
403 register_cpu(&cpu[1], 1);
404 return 0;
405#else
c0fc525d 406 static struct cpu cpu[1];
1394f032
BW		 407 return register_cpu(cpu, 0);
408#endif
409}
410
411subsys_initcall(topology_init);
412
413#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
414u16 lock_kernel_check(u32 start, u32 end)
415{
416 if ((start <= (u32) _stext && end >= (u32) _end)
417 || (start >= (u32) _stext && end <= (u32) _end))
418 return IN_KERNEL;
419 return 0;
420}
421
422static unsigned short __init
423fill_cplbtab(struct cplb_tab *table,
424 unsigned long start, unsigned long end,
425 unsigned long block_size, unsigned long cplb_data)
426{
427 int i;
428
429 switch (block_size) {
430 case SIZE_4M:
431 i = 3;
432 break;
433 case SIZE_1M:
434 i = 2;
435 break;
436 case SIZE_4K:
437 i = 1;
438 break;
439 case SIZE_1K:
440 default:
441 i = 0;
442 break;
443 }
444
445 cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
446
447 while ((start < end) && (table->pos < table->size)) {
448
449 table->tab[table->pos++] = start;
450
451 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
452 table->tab[table->pos++] =
453 cplb_data | CPLB_LOCK | CPLB_DIRTY;
454 else
455 table->tab[table->pos++] = cplb_data;
456
457 start += block_size;
458 }
459 return 0;
460}
461
462static unsigned short __init
463close_cplbtab(struct cplb_tab *table)
464{
465
466 while (table->pos < table->size) {
467
468 table->tab[table->pos++] = 0;
469 table->tab[table->pos++] = 0; /* !CPLB_VALID */
470 }
471 return 0;
472}
473
474static void __init generate_cpl_tables(void)
475{
476
477 u16 i, j, process;
478 u32 a_start, a_end, as, ae, as_1m;
479
480 struct cplb_tab *t_i = NULL;
481 struct cplb_tab *t_d = NULL;
482 struct s_cplb cplb;
483
484 cplb.init_i.size = MAX_CPLBS;
485 cplb.init_d.size = MAX_CPLBS;
486 cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
487 cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
488
489 cplb.init_i.pos = 0;
490 cplb.init_d.pos = 0;
491 cplb.switch_i.pos = 0;
492 cplb.switch_d.pos = 0;
493
494 cplb.init_i.tab = icplb_table;
495 cplb.init_d.tab = dcplb_table;
496 cplb.switch_i.tab = ipdt_table;
497 cplb.switch_d.tab = dpdt_table;
498
499 cplb_data[SDRAM_KERN].end = memory_end;
500
501#ifdef CONFIG_MTD_UCLINUX
502 cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
503 cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
504 cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
505# if defined(CONFIG_ROMFS_FS)
506 cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
507
508 /*
509 * The ROMFS_FS size is often not multiple of 1MB.
510 * This can cause multiple CPLB sets covering the same memory area.
511 * This will then cause multiple CPLB hit exceptions.
512 * Workaround: We ensure a contiguous memory area by extending the kernel
513 * memory section over the mtd section.
514 * For ROMFS_FS memory must be covered with ICPLBs anyways.
515 * So there is no difference between kernel and mtd memory setup.
516 */
517
518 cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
519 cplb_data[SDRAM_RAM_MTD].valid = 0;
520
521# endif
522#else
523 cplb_data[SDRAM_RAM_MTD].valid = 0;
524#endif
525
526 cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
527 cplb_data[SDRAM_DMAZ].end = _ramend;
528
529 cplb_data[RES_MEM].start = _ramend;
530 cplb_data[RES_MEM].end = physical_mem_end;
531
532 if (reserved_mem_dcache_on)
533 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
534 else
535 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
536
537 if (reserved_mem_icache_on)
538 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
539 else
540 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
541
542 for (i = ZERO_P; i <= L2_MEM; i++) {
543
544 if (cplb_data[i].valid) {
545
546 as_1m = cplb_data[i].start % SIZE_1M;
547
548 /* We need to make sure all sections are properly 1M aligned
549 * However between Kernel Memory and the Kernel mtd section, depending on the
550 * rootfs size, there can be overlapping memory areas.
551 */
552
553 if (as_1m && i!=L1I_MEM && i!=L1D_MEM) {
554#ifdef CONFIG_MTD_UCLINUX
555 if (i == SDRAM_RAM_MTD) {
556 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
557 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
558 else
559 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
560 } else
561#endif
562 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
563 cplb_data[i].name, cplb_data[i].start);
564 }
565
566 as = cplb_data[i].start % SIZE_4M;
567 ae = cplb_data[i].end % SIZE_4M;
568
569 if (as)
570 a_start = cplb_data[i].start + (SIZE_4M - (as));
571 else
572 a_start = cplb_data[i].start;
573
574 a_end = cplb_data[i].end - ae;
575
576 for (j = INITIAL_T; j <= SWITCH_T; j++) {
577
578 switch (j) {
579 case INITIAL_T:
580 if (cplb_data[i].attr & INITIAL_T) {
581 t_i = &cplb.init_i;
582 t_d = &cplb.init_d;
583 process = 1;
584 } else
585 process = 0;
586 break;
587 case SWITCH_T:
588 if (cplb_data[i].attr & SWITCH_T) {
589 t_i = &cplb.switch_i;
590 t_d = &cplb.switch_d;
591 process = 1;
592 } else
593 process = 0;
594 break;
595 default:
596 process = 0;
597 break;
598 }
599
600 if (process) {
601 if (cplb_data[i].attr & I_CPLB) {
602
603 if (cplb_data[i].psize) {
604 fill_cplbtab(t_i,
605 cplb_data[i].start,
606 cplb_data[i].end,
607 cplb_data[i].psize,
608 cplb_data[i].i_conf);
609 } else {
610 /*icplb_table */
611#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
612 if (i == SDRAM_KERN) {
613 fill_cplbtab(t_i,
614 cplb_data[i].start,
615 cplb_data[i].end,
616 SIZE_4M,
617 cplb_data[i].i_conf);
618 } else
619#endif
620 {
621 fill_cplbtab(t_i,
622 cplb_data[i].start,
623 a_start,
624 SIZE_1M,
625 cplb_data[i].i_conf);
626 fill_cplbtab(t_i,
627 a_start,
628 a_end,
629 SIZE_4M,
630 cplb_data[i].i_conf);
631 fill_cplbtab(t_i, a_end,
632 cplb_data[i].end,
633 SIZE_1M,
634 cplb_data[i].i_conf);
635 }
636 }
637
638 }
639 if (cplb_data[i].attr & D_CPLB) {
640
641 if (cplb_data[i].psize) {
642 fill_cplbtab(t_d,
643 cplb_data[i].start,
644 cplb_data[i].end,
645 cplb_data[i].psize,
646 cplb_data[i].d_conf);
647 } else {
648/*dcplb_table*/
649 fill_cplbtab(t_d,
650 cplb_data[i].start,
651 a_start, SIZE_1M,
652 cplb_data[i].d_conf);
653 fill_cplbtab(t_d, a_start,
654 a_end, SIZE_4M,
655 cplb_data[i].d_conf);
656 fill_cplbtab(t_d, a_end,
657 cplb_data[i].end,
658 SIZE_1M,
659 cplb_data[i].d_conf);
660
661 }
662
663 }
664 }
665 }
666
667 }
668 }
669
670/* close tables */
671
672 close_cplbtab(&cplb.init_i);
673 close_cplbtab(&cplb.init_d);
674
675 cplb.init_i.tab[cplb.init_i.pos] = -1;
676 cplb.init_d.tab[cplb.init_d.pos] = -1;
677 cplb.switch_i.tab[cplb.switch_i.pos] = -1;
678 cplb.switch_d.tab[cplb.switch_d.pos] = -1;
679
680}
681
682#endif
683
684static inline u_long get_vco(void)
685{
686 u_long msel;
687 u_long vco;
688
689 msel = (bfin_read_PLL_CTL() >> 9) & 0x3F;
690 if (0 == msel)
691 msel = 64;
692
693 vco = CONFIG_CLKIN_HZ;
694 vco >>= (1 & bfin_read_PLL_CTL()); /* DF bit */
695 vco = msel * vco;
696 return vco;
697}
698
699/*Get the Core clock*/
700u_long get_cclk(void)
701{
702 u_long csel, ssel;
703 if (bfin_read_PLL_STAT() & 0x1)
704 return CONFIG_CLKIN_HZ;
705
706 ssel = bfin_read_PLL_DIV();
707 csel = ((ssel >> 4) & 0x03);
708 ssel &= 0xf;
709 if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
710 return get_vco() / ssel;
711 return get_vco() >> csel;
712}
713
714EXPORT_SYMBOL(get_cclk);
715
716/* Get the System clock */
717u_long get_sclk(void)
718{
719 u_long ssel;
720
721 if (bfin_read_PLL_STAT() & 0x1)
722 return CONFIG_CLKIN_HZ;
723
724 ssel = (bfin_read_PLL_DIV() & 0xf);
725 if (0 == ssel) {
726 printk(KERN_WARNING "Invalid System Clock\n");
727 ssel = 1;
728 }
729
730 return get_vco() / ssel;
731}
732
733EXPORT_SYMBOL(get_sclk);
734
735/*
736 * Get CPU information for use by the procfs.
737 */
738static int show_cpuinfo(struct seq_file *m, void *v)
739{
740 char *cpu, *mmu, *fpu, *name;
741 uint32_t revid;
742
743 u_long cclk = 0, sclk = 0;
744 u_int dcache_size = 0, dsup_banks = 0;
745
746 cpu = CPU;
747 mmu = "none";
748 fpu = "none";
749 revid = bfin_revid();
750 name = bfin_board_name;
751
752 cclk = get_cclk();
753 sclk = get_sclk();
754
755 seq_printf(m, "CPU:\t\tADSP-%s Rev. 0.%d\n"
756 "MMU:\t\t%s\n"
757 "FPU:\t\t%s\n"
758 "Core Clock:\t%9lu Hz\n"
759 "System Clock:\t%9lu Hz\n"
760 "BogoMips:\t%lu.%02lu\n"
761 "Calibration:\t%lu loops\n",
762 cpu, revid, mmu, fpu,
763 cclk,
764 sclk,
765 (loops_per_jiffy * HZ) / 500000,
766 ((loops_per_jiffy * HZ) / 5000) % 100,
767 (loops_per_jiffy * HZ));
768 seq_printf(m, "Board Name:\t%s\n", name);
769 seq_printf(m, "Board Memory:\t%ld MB\n", physical_mem_end >> 20);
770 seq_printf(m, "Kernel Memory:\t%ld MB\n", (unsigned long)_ramend >> 20);
771 if (bfin_read_IMEM_CONTROL() & (ENICPLB | IMC))
772 seq_printf(m, "I-CACHE:\tON\n");
773 else
774 seq_printf(m, "I-CACHE:\tOFF\n");
775 if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
776 seq_printf(m, "D-CACHE:\tON"
777#if defined CONFIG_BLKFIN_WB
778 " (write-back)"
779#elif defined CONFIG_BLKFIN_WT
780 " (write-through)"
781#endif
782 "\n");
783 else
784 seq_printf(m, "D-CACHE:\tOFF\n");
785
786
787 switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
788 case ACACHE_BSRAM:
789 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
790 dcache_size = 16;
791 dsup_banks = 1;
792 break;
793 case ACACHE_BCACHE:
794 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
795 dcache_size = 32;
796 dsup_banks = 2;
797 break;
798 case ASRAM_BSRAM:
799 seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
800 dcache_size = 0;
801 dsup_banks = 0;
802 break;
803 default:
804 break;
805 }
806
807
808 seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024);
809 seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size);
810 seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n",
811 BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES);
812 seq_printf(m,
813 "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
814 dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS,
815 BLKFIN_DLINES);
816#ifdef CONFIG_BLKFIN_CACHE_LOCK
817 switch (read_iloc()) {
818 case WAY0_L:
819 seq_printf(m, "Way0 Locked-Down\n");
820 break;
821 case WAY1_L:
822 seq_printf(m, "Way1 Locked-Down\n");
823 break;
824 case WAY01_L:
825 seq_printf(m, "Way0,Way1 Locked-Down\n");
826 break;
827 case WAY2_L:
828 seq_printf(m, "Way2 Locked-Down\n");
829 break;
830 case WAY02_L:
831 seq_printf(m, "Way0,Way2 Locked-Down\n");
832 break;
833 case WAY12_L:
834 seq_printf(m, "Way1,Way2 Locked-Down\n");
835 break;
836 case WAY012_L:
837 seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
838 break;
839 case WAY3_L:
840 seq_printf(m, "Way3 Locked-Down\n");
841 break;
842 case WAY03_L:
843 seq_printf(m, "Way0,Way3 Locked-Down\n");
844 break;
845 case WAY13_L:
846 seq_printf(m, "Way1,Way3 Locked-Down\n");
847 break;
848 case WAY013_L:
849 seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
850 break;
851 case WAY32_L:
852 seq_printf(m, "Way3,Way2 Locked-Down\n");
853 break;
854 case WAY320_L:
855 seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
856 break;
857 case WAY321_L:
858 seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
859 break;
860 case WAYALL_L:
861 seq_printf(m, "All Ways are locked\n");
862 break;
863 default:
864 seq_printf(m, "No Ways are locked\n");
865 }
866#endif
867 return 0;
868}
869
870static void *c_start(struct seq_file *m, loff_t *pos)
871{
872 return *pos < NR_CPUS ? ((void *)0x12345678) : NULL;
873}
874
875static void *c_next(struct seq_file *m, void *v, loff_t *pos)
876{
877 ++*pos;
878 return c_start(m, pos);
879}
880
881static void c_stop(struct seq_file *m, void *v)
882{
883}
884
885struct seq_operations cpuinfo_op = {
886 .start = c_start,
887 .next = c_next,
888 .stop = c_stop,
889 .show = show_cpuinfo,
890};
891
892void cmdline_init(unsigned long r0)
893{
894 if (r0)
895 strncpy(command_line, (char *)r0, COMMAND_LINE_SIZE);
896}
Linux kernel - Deliverables
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