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Blackfin arch: Fix bug - wrong endpoint number and dma channels of USB
[deliverable/linux.git] / arch / blackfin / kernel / setup.c
CommitLineData
1394f032 1/*
550d5538 2 * arch/blackfin/kernel/setup.c
1394f032 3 *
550d5538 4 * Copyright 2004-2006 Analog Devices Inc.
1394f032 5 *
550d5538 6 * Enter bugs at http://blackfin.uclinux.org/
1394f032 7 *
550d5538 8 * Licensed under the GPL-2 or later.
1394f032
BW		 9 */
10
11#include <linux/delay.h>
12#include <linux/console.h>
13#include <linux/bootmem.h>
14#include <linux/seq_file.h>
15#include <linux/cpu.h>
259fea42 16#include <linux/mm.h>
1394f032 17#include <linux/module.h>
1394f032 18#include <linux/tty.h>
856783b3 19#include <linux/pfn.h>
1394f032
BW		 20
21#include <linux/ext2_fs.h>
22#include <linux/cramfs_fs.h>
23#include <linux/romfs_fs.h>
24
3bebca2d 25#include <asm/cplb.h>
1394f032
BW		 26#include <asm/cacheflush.h>
27#include <asm/blackfin.h>
28#include <asm/cplbinit.h>
1754a5d9 29#include <asm/div64.h>
8f65873e 30#include <asm/cpu.h>
7adfb58f 31#include <asm/fixed_code.h>
ce3afa1c 32#include <asm/early_printk.h>
1394f032 33
a9c59c27 34u16 _bfin_swrst;
d45118b1 35EXPORT_SYMBOL(_bfin_swrst);
a9c59c27 36
1394f032 37unsigned long memory_start, memory_end, physical_mem_end;
3132b586 38unsigned long _rambase, _ramstart, _ramend;
1394f032
BW		 39unsigned long reserved_mem_dcache_on;
40unsigned long reserved_mem_icache_on;
41EXPORT_SYMBOL(memory_start);
42EXPORT_SYMBOL(memory_end);
43EXPORT_SYMBOL(physical_mem_end);
44EXPORT_SYMBOL(_ramend);
58c35bd3 45EXPORT_SYMBOL(reserved_mem_dcache_on);
1394f032
BW		 46
47#ifdef CONFIG_MTD_UCLINUX
48unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
49unsigned long _ebss;
50EXPORT_SYMBOL(memory_mtd_end);
51EXPORT_SYMBOL(memory_mtd_start);
52EXPORT_SYMBOL(mtd_size);
53#endif
54
5e10b4a6 55char __initdata command_line[COMMAND_LINE_SIZE];
0c7a6b21
RG		 56void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat,
57 *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr;
1394f032 58
856783b3
YL		 59/* boot memmap, for parsing "memmap=" */
60#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
61#define BFIN_MEMMAP_RAM 1
62#define BFIN_MEMMAP_RESERVED 2
63struct bfin_memmap {
64 int nr_map;
65 struct bfin_memmap_entry {
66 unsigned long long addr; /* start of memory segment */
67 unsigned long long size;
68 unsigned long type;
69 } map[BFIN_MEMMAP_MAX];
70} bfin_memmap __initdata;
71
72/* for memmap sanitization */
73struct change_member {
74 struct bfin_memmap_entry *pentry; /* pointer to original entry */
75 unsigned long long addr; /* address for this change point */
76};
77static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
78static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
79static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
80static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
81
8f65873e
GY		 82DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
83
7f1e2f98
MF		 84static int early_init_clkin_hz(char *buf);
85
3bebca2d 86#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
8f65873e
GY		 87void __init generate_cplb_tables(void)
88{
89 unsigned int cpu;
90
91 /* Generate per-CPU I&D CPLB tables */
92 for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
93 generate_cplb_tables_cpu(cpu);
94}
1394f032
BW		 95#endif
96
8f65873e
GY		 97void __cpuinit bfin_setup_caches(unsigned int cpu)
98{
3bebca2d 99#ifdef CONFIG_BFIN_ICACHE
8f65873e
GY		 100#ifdef CONFIG_MPU
101 bfin_icache_init(icplb_tbl[cpu]);
102#else
103 bfin_icache_init(icplb_tables[cpu]);
104#endif
1394f032
BW		 105#endif
106
3bebca2d 107#ifdef CONFIG_BFIN_DCACHE
8f65873e
GY		 108#ifdef CONFIG_MPU
109 bfin_dcache_init(dcplb_tbl[cpu]);
110#else
111 bfin_dcache_init(dcplb_tables[cpu]);
112#endif
113#endif
114
115 /*
116 * In cache coherence emulation mode, we need to have the
117 * D-cache enabled before running any atomic operation which
118 * might invove cache invalidation (i.e. spinlock, rwlock).
119 * So printk's are deferred until then.
120 */
121#ifdef CONFIG_BFIN_ICACHE
122 printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
123#endif
124#ifdef CONFIG_BFIN_DCACHE
125 printk(KERN_INFO "Data Cache Enabled for CPU%u"
3bebca2d 126# if defined CONFIG_BFIN_WB
1394f032 127 " (write-back)"
3bebca2d 128# elif defined CONFIG_BFIN_WT
1394f032
BW		 129 " (write-through)"
130# endif
8f65873e 131 "\n", cpu);
1394f032
BW		 132#endif
133}
134
8f65873e
GY		 135void __cpuinit bfin_setup_cpudata(unsigned int cpu)
136{
137 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
138
139 cpudata->idle = current;
140 cpudata->loops_per_jiffy = loops_per_jiffy;
8f65873e
GY		 141 cpudata->imemctl = bfin_read_IMEM_CONTROL();
142 cpudata->dmemctl = bfin_read_DMEM_CONTROL();
143}
144
145void __init bfin_cache_init(void)
146{
147#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
148 generate_cplb_tables();
149#endif
150 bfin_setup_caches(0);
151}
152
5b04f271 153void __init bfin_relocate_l1_mem(void)
1394f032
BW		 154{
155 unsigned long l1_code_length;
156 unsigned long l1_data_a_length;
157 unsigned long l1_data_b_length;
262c3825 158 unsigned long l2_length;
1394f032 159
dd3dd384
MF		 160 blackfin_dma_early_init();
161
1394f032
BW		 162 l1_code_length = _etext_l1 - _stext_l1;
163 if (l1_code_length > L1_CODE_LENGTH)
b85b82d9 164 panic("L1 Instruction SRAM Overflow\n");
1394f032
BW		 165 /* cannot complain as printk is not available as yet.
166 * But we can continue booting and complain later!
167 */
168
169 /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
170 dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
171
3b1f26a5 172 l1_data_a_length = _sbss_l1 - _sdata_l1;
1394f032 173 if (l1_data_a_length > L1_DATA_A_LENGTH)
b85b82d9 174 panic("L1 Data SRAM Bank A Overflow\n");
1394f032 175
3b1f26a5 176 /* Copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */
1394f032
BW		 177 dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
178
3b1f26a5 179 l1_data_b_length = _sbss_b_l1 - _sdata_b_l1;
1394f032 180 if (l1_data_b_length > L1_DATA_B_LENGTH)
b85b82d9 181 panic("L1 Data SRAM Bank B Overflow\n");
1394f032 182
3b1f26a5 183 /* Copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */
1394f032
BW		 184 dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
185 l1_data_a_length, l1_data_b_length);
262c3825 186
07aa7be5 187 if (L2_LENGTH != 0) {
3b1f26a5 188 l2_length = _sbss_l2 - _stext_l2;
07aa7be5
MF		 189 if (l2_length > L2_LENGTH)
190 panic("L2 SRAM Overflow\n");
262c3825 191
07aa7be5
MF		 192 /* Copy _stext_l2 to _edata_l2 to L2 SRAM */
193 dma_memcpy(_stext_l2, _l2_lma_start, l2_length);
194 }
1394f032
BW		 195}
196
856783b3
YL		 197/* add_memory_region to memmap */
198static void __init add_memory_region(unsigned long long start,
199 unsigned long long size, int type)
200{
201 int i;
202
203 i = bfin_memmap.nr_map;
204
205 if (i == BFIN_MEMMAP_MAX) {
206 printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
207 return;
208 }
209
210 bfin_memmap.map[i].addr = start;
211 bfin_memmap.map[i].size = size;
212 bfin_memmap.map[i].type = type;
213 bfin_memmap.nr_map++;
214}
215
216/*
217 * Sanitize the boot memmap, removing overlaps.
218 */
219static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
220{
221 struct change_member *change_tmp;
222 unsigned long current_type, last_type;
223 unsigned long long last_addr;
224 int chgidx, still_changing;
225 int overlap_entries;
226 int new_entry;
227 int old_nr, new_nr, chg_nr;
228 int i;
229
230 /*
231 Visually we're performing the following (1,2,3,4 = memory types)
232
233 Sample memory map (w/overlaps):
234 ____22__________________
235 ______________________4_
236 ____1111________________
237 _44_____________________
238 11111111________________
239 ____________________33__
240 ___________44___________
241 __________33333_________
242 ______________22________
243 ___________________2222_
244 _________111111111______
245 _____________________11_
246 _________________4______
247
248 Sanitized equivalent (no overlap):
249 1_______________________
250 _44_____________________
251 ___1____________________
252 ____22__________________
253 ______11________________
254 _________1______________
255 __________3_____________
256 ___________44___________
257 _____________33_________
258 _______________2________
259 ________________1_______
260 _________________4______
261 ___________________2____
262 ____________________33__
263 ______________________4_
264 */
265 /* if there's only one memory region, don't bother */
266 if (*pnr_map < 2)
267 return -1;
268
269 old_nr = *pnr_map;
270
271 /* bail out if we find any unreasonable addresses in memmap */
272 for (i = 0; i < old_nr; i++)
273 if (map[i].addr + map[i].size < map[i].addr)
274 return -1;
275
276 /* create pointers for initial change-point information (for sorting) */
277 for (i = 0; i < 2*old_nr; i++)
278 change_point[i] = &change_point_list[i];
279
280 /* record all known change-points (starting and ending addresses),
281 omitting those that are for empty memory regions */
282 chgidx = 0;
8f65873e 283 for (i = 0; i < old_nr; i++) {
856783b3
YL		 284 if (map[i].size != 0) {
285 change_point[chgidx]->addr = map[i].addr;
286 change_point[chgidx++]->pentry = &map[i];
287 change_point[chgidx]->addr = map[i].addr + map[i].size;
288 change_point[chgidx++]->pentry = &map[i];
289 }
290 }
8f65873e 291 chg_nr = chgidx; /* true number of change-points */
856783b3
YL		 292
293 /* sort change-point list by memory addresses (low -> high) */
294 still_changing = 1;
8f65873e 295 while (still_changing) {
856783b3 296 still_changing = 0;
8f65873e 297 for (i = 1; i < chg_nr; i++) {
856783b3
YL		 298 /* if <current_addr> > <last_addr>, swap */
299 /* or, if current=<start_addr> & last=<end_addr>, swap */
300 if ((change_point[i]->addr < change_point[i-1]->addr) ||
301 ((change_point[i]->addr == change_point[i-1]->addr) &&
302 (change_point[i]->addr == change_point[i]->pentry->addr) &&
303 (change_point[i-1]->addr != change_point[i-1]->pentry->addr))
304 ) {
305 change_tmp = change_point[i];
306 change_point[i] = change_point[i-1];
307 change_point[i-1] = change_tmp;
308 still_changing = 1;
309 }
310 }
311 }
312
313 /* create a new memmap, removing overlaps */
8f65873e
GY		 314 overlap_entries = 0; /* number of entries in the overlap table */
315 new_entry = 0; /* index for creating new memmap entries */
316 last_type = 0; /* start with undefined memory type */
317 last_addr = 0; /* start with 0 as last starting address */
856783b3
YL		 318 /* loop through change-points, determining affect on the new memmap */
319 for (chgidx = 0; chgidx < chg_nr; chgidx++) {
320 /* keep track of all overlapping memmap entries */
321 if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
322 /* add map entry to overlap list (> 1 entry implies an overlap) */
323 overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
324 } else {
325 /* remove entry from list (order independent, so swap with last) */
326 for (i = 0; i < overlap_entries; i++) {
327 if (overlap_list[i] == change_point[chgidx]->pentry)
328 overlap_list[i] = overlap_list[overlap_entries-1];
329 }
330 overlap_entries--;
331 }
332 /* if there are overlapping entries, decide which "type" to use */
333 /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
334 current_type = 0;
335 for (i = 0; i < overlap_entries; i++)
336 if (overlap_list[i]->type > current_type)
337 current_type = overlap_list[i]->type;
338 /* continue building up new memmap based on this information */
8f65873e 339 if (current_type != last_type) {
856783b3
YL		 340 if (last_type != 0) {
341 new_map[new_entry].size =
342 change_point[chgidx]->addr - last_addr;
343 /* move forward only if the new size was non-zero */
344 if (new_map[new_entry].size != 0)
345 if (++new_entry >= BFIN_MEMMAP_MAX)
8f65873e 346 break; /* no more space left for new entries */
856783b3
YL		 347 }
348 if (current_type != 0) {
349 new_map[new_entry].addr = change_point[chgidx]->addr;
350 new_map[new_entry].type = current_type;
351 last_addr = change_point[chgidx]->addr;
352 }
353 last_type = current_type;
354 }
355 }
8f65873e 356 new_nr = new_entry; /* retain count for new entries */
856783b3 357
8f65873e 358 /* copy new mapping into original location */
856783b3
YL		 359 memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
360 *pnr_map = new_nr;
361
362 return 0;
363}
364
365static void __init print_memory_map(char *who)
366{
367 int i;
368
369 for (i = 0; i < bfin_memmap.nr_map; i++) {
370 printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
371 bfin_memmap.map[i].addr,
372 bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
373 switch (bfin_memmap.map[i].type) {
374 case BFIN_MEMMAP_RAM:
375 printk("(usable)\n");
376 break;
377 case BFIN_MEMMAP_RESERVED:
378 printk("(reserved)\n");
379 break;
380 default: printk("type %lu\n", bfin_memmap.map[i].type);
381 break;
382 }
383 }
384}
385
386static __init int parse_memmap(char *arg)
387{
388 unsigned long long start_at, mem_size;
389
390 if (!arg)
391 return -EINVAL;
392
393 mem_size = memparse(arg, &arg);
394 if (*arg == '@') {
395 start_at = memparse(arg+1, &arg);
396 add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
397 } else if (*arg == '$') {
398 start_at = memparse(arg+1, &arg);
399 add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
400 }
401
402 return 0;
403}
404
1394f032
BW		 405/*
406 * Initial parsing of the command line. Currently, we support:
407 * - Controlling the linux memory size: mem=xxx[KMG]
408 * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
409 * $ -> reserved memory is dcacheable
410 * # -> reserved memory is icacheable
856783b3
YL		 411 * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
412 * @ from <start> to <start>+<mem>, type RAM
413 * $ from <start> to <start>+<mem>, type RESERVED
1394f032
BW		 414 */
415static __init void parse_cmdline_early(char *cmdline_p)
416{
417 char c = ' ', *to = cmdline_p;
418 unsigned int memsize;
419 for (;;) {
420 if (c == ' ') {
1394f032
BW		 421 if (!memcmp(to, "mem=", 4)) {
422 to += 4;
423 memsize = memparse(to, &to);
424 if (memsize)
425 _ramend = memsize;
426
427 } else if (!memcmp(to, "max_mem=", 8)) {
428 to += 8;
429 memsize = memparse(to, &to);
430 if (memsize) {
431 physical_mem_end = memsize;
432 if (*to != ' ') {
433 if (*to == '$'
434 || *(to + 1) == '$')
8f65873e 435 reserved_mem_dcache_on = 1;
1394f032
BW		 436 if (*to == '#'
437 || *(to + 1) == '#')
8f65873e 438 reserved_mem_icache_on = 1;
1394f032
BW		 439 }
440 }
7f1e2f98
MF		 441 } else if (!memcmp(to, "clkin_hz=", 9)) {
442 to += 9;
443 early_init_clkin_hz(to);
ce3afa1c
RG		 444 } else if (!memcmp(to, "earlyprintk=", 12)) {
445 to += 12;
446 setup_early_printk(to);
856783b3
YL		 447 } else if (!memcmp(to, "memmap=", 7)) {
448 to += 7;
449 parse_memmap(to);
1394f032 450 }
1394f032
BW		 451 }
452 c = *(to++);
453 if (!c)
454 break;
455 }
456}
457
856783b3
YL		 458/*
459 * Setup memory defaults from user config.
460 * The physical memory layout looks like:
461 *
462 * [_rambase, _ramstart]: kernel image
463 * [memory_start, memory_end]: dynamic memory managed by kernel
464 * [memory_end, _ramend]: reserved memory
3094c981 465 * [memory_mtd_start(memory_end),
856783b3
YL		 466 * memory_mtd_start + mtd_size]: rootfs (if any)
467 * [_ramend - DMA_UNCACHED_REGION,
468 * _ramend]: uncached DMA region
469 * [_ramend, physical_mem_end]: memory not managed by kernel
856783b3 470 */
8f65873e 471static __init void memory_setup(void)
1394f032 472{
c0eab3b7
MF		 473#ifdef CONFIG_MTD_UCLINUX
474 unsigned long mtd_phys = 0;
475#endif
476
856783b3 477 _rambase = (unsigned long)_stext;
b7627acc 478 _ramstart = (unsigned long)_end;
1394f032 479
856783b3
YL		 480 if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
481 console_init();
482 panic("DMA region exceeds memory limit: %lu.\n",
483 _ramend - _ramstart);
1aafd909 484 }
1394f032
BW		 485 memory_end = _ramend - DMA_UNCACHED_REGION;
486
b97b8a99 487#ifdef CONFIG_MPU
8f65873e 488 /* Round up to multiple of 4MB */
b97b8a99
BS		 489 memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
490#else
1394f032 491 memory_start = PAGE_ALIGN(_ramstart);
b97b8a99 492#endif
1394f032
BW		 493
494#if defined(CONFIG_MTD_UCLINUX)
495 /* generic memory mapped MTD driver */
496 memory_mtd_end = memory_end;
497
498 mtd_phys = _ramstart;
499 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
500
501# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
502 if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
503 mtd_size =
504 PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
505# endif
506
507# if defined(CONFIG_CRAMFS)
508 if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
509 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
510# endif
511
512# if defined(CONFIG_ROMFS_FS)
513 if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
514 && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
515 mtd_size =
516 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
3bebca2d 517# if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
1394f032
BW		 518 /* Due to a Hardware Anomaly we need to limit the size of usable
519 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
520 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
521 */
522# if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
523 if (memory_end >= 56 * 1024 * 1024)
524 memory_end = 56 * 1024 * 1024;
525# else
526 if (memory_end >= 60 * 1024 * 1024)
527 memory_end = 60 * 1024 * 1024;
528# endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
529# endif /* ANOMALY_05000263 */
530# endif /* CONFIG_ROMFS_FS */
531
532 memory_end -= mtd_size;
533
534 if (mtd_size == 0) {
535 console_init();
536 panic("Don't boot kernel without rootfs attached.\n");
537 }
538
539 /* Relocate MTD image to the top of memory after the uncached memory area */
b7627acc 540 dma_memcpy((char *)memory_end, _end, mtd_size);
1394f032
BW		 541
542 memory_mtd_start = memory_end;
543 _ebss = memory_mtd_start; /* define _ebss for compatible */
544#endif /* CONFIG_MTD_UCLINUX */
545
3bebca2d 546#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
1394f032
BW		 547 /* Due to a Hardware Anomaly we need to limit the size of usable
548 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
549 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
550 */
551#if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
552 if (memory_end >= 56 * 1024 * 1024)
553 memory_end = 56 * 1024 * 1024;
554#else
555 if (memory_end >= 60 * 1024 * 1024)
556 memory_end = 60 * 1024 * 1024;
557#endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
558 printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
559#endif /* ANOMALY_05000263 */
560
b97b8a99
BS		 561#ifdef CONFIG_MPU
562 page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
563 page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
564#endif
565
1394f032 566#if !defined(CONFIG_MTD_UCLINUX)
856783b3
YL		 567 /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
568 memory_end -= SIZE_4K;
1394f032 569#endif
856783b3 570
1394f032
BW		 571 init_mm.start_code = (unsigned long)_stext;
572 init_mm.end_code = (unsigned long)_etext;
573 init_mm.end_data = (unsigned long)_edata;
574 init_mm.brk = (unsigned long)0;
575
856783b3
YL		 576 printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
577 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
578
b7627acc 579 printk(KERN_INFO "Memory map:\n"
8929ecf8 580 KERN_INFO " fixedcode = 0x%p-0x%p\n"
856783b3
YL		 581 KERN_INFO " text = 0x%p-0x%p\n"
582 KERN_INFO " rodata = 0x%p-0x%p\n"
b7627acc 583 KERN_INFO " bss = 0x%p-0x%p\n"
856783b3
YL		 584 KERN_INFO " data = 0x%p-0x%p\n"
585 KERN_INFO " stack = 0x%p-0x%p\n"
586 KERN_INFO " init = 0x%p-0x%p\n"
856783b3
YL		 587 KERN_INFO " available = 0x%p-0x%p\n"
588#ifdef CONFIG_MTD_UCLINUX
589 KERN_INFO " rootfs = 0x%p-0x%p\n"
590#endif
591#if DMA_UNCACHED_REGION > 0
592 KERN_INFO " DMA Zone = 0x%p-0x%p\n"
593#endif
8929ecf8
MF		 594 , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
595 _stext, _etext,
856783b3 596 __start_rodata, __end_rodata,
b7627acc 597 __bss_start, __bss_stop,
856783b3
YL		 598 _sdata, _edata,
599 (void *)&init_thread_union,
600 (void *)((int)(&init_thread_union) + 0x2000),
b7627acc
MF		 601 __init_begin, __init_end,
602 (void *)_ramstart, (void *)memory_end
856783b3
YL		 603#ifdef CONFIG_MTD_UCLINUX
604 , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
605#endif
606#if DMA_UNCACHED_REGION > 0
607 , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
608#endif
609 );
610}
611
2e8d7965
YL		 612/*
613 * Find the lowest, highest page frame number we have available
614 */
615void __init find_min_max_pfn(void)
616{
617 int i;
618
619 max_pfn = 0;
620 min_low_pfn = memory_end;
621
622 for (i = 0; i < bfin_memmap.nr_map; i++) {
623 unsigned long start, end;
624 /* RAM? */
625 if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
626 continue;
627 start = PFN_UP(bfin_memmap.map[i].addr);
628 end = PFN_DOWN(bfin_memmap.map[i].addr +
629 bfin_memmap.map[i].size);
630 if (start >= end)
631 continue;
632 if (end > max_pfn)
633 max_pfn = end;
634 if (start < min_low_pfn)
635 min_low_pfn = start;
636 }
637}
638
856783b3
YL		 639static __init void setup_bootmem_allocator(void)
640{
641 int bootmap_size;
642 int i;
2e8d7965 643 unsigned long start_pfn, end_pfn;
856783b3
YL		 644 unsigned long curr_pfn, last_pfn, size;
645
646 /* mark memory between memory_start and memory_end usable */
647 add_memory_region(memory_start,
648 memory_end - memory_start, BFIN_MEMMAP_RAM);
649 /* sanity check for overlap */
650 sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
651 print_memory_map("boot memmap");
652
2e8d7965
YL		 653 /* intialize globals in linux/bootmem.h */
654 find_min_max_pfn();
655 /* pfn of the last usable page frame */
656 if (max_pfn > memory_end >> PAGE_SHIFT)
657 max_pfn = memory_end >> PAGE_SHIFT;
658 /* pfn of last page frame directly mapped by kernel */
659 max_low_pfn = max_pfn;
660 /* pfn of the first usable page frame after kernel image*/
661 if (min_low_pfn < memory_start >> PAGE_SHIFT)
662 min_low_pfn = memory_start >> PAGE_SHIFT;
663
664 start_pfn = PAGE_OFFSET >> PAGE_SHIFT;
665 end_pfn = memory_end >> PAGE_SHIFT;
856783b3
YL		 666
667 /*
8f65873e 668 * give all the memory to the bootmap allocator, tell it to put the
856783b3
YL		 669 * boot mem_map at the start of memory.
670 */
671 bootmap_size = init_bootmem_node(NODE_DATA(0),
672 memory_start >> PAGE_SHIFT, /* map goes here */
2e8d7965 673 start_pfn, end_pfn);
856783b3
YL		 674
675 /* register the memmap regions with the bootmem allocator */
676 for (i = 0; i < bfin_memmap.nr_map; i++) {
677 /*
678 * Reserve usable memory
679 */
680 if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
681 continue;
682 /*
683 * We are rounding up the start address of usable memory:
684 */
685 curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
2e8d7965 686 if (curr_pfn >= end_pfn)
856783b3
YL		 687 continue;
688 /*
689 * ... and at the end of the usable range downwards:
690 */
691 last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
692 bfin_memmap.map[i].size);
693
2e8d7965
YL		 694 if (last_pfn > end_pfn)
695 last_pfn = end_pfn;
856783b3
YL		 696
697 /*
698 * .. finally, did all the rounding and playing
699 * around just make the area go away?
700 */
701 if (last_pfn <= curr_pfn)
702 continue;
703
704 size = last_pfn - curr_pfn;
705 free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
706 }
707
708 /* reserve memory before memory_start, including bootmap */
709 reserve_bootmem(PAGE_OFFSET,
710 memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET,
711 BOOTMEM_DEFAULT);
712}
713
a086ee22
MF		 714#define EBSZ_TO_MEG(ebsz) \
715({ \
716 int meg = 0; \
717 switch (ebsz & 0xf) { \
718 case 0x1: meg = 16; break; \
719 case 0x3: meg = 32; break; \
720 case 0x5: meg = 64; break; \
721 case 0x7: meg = 128; break; \
722 case 0x9: meg = 256; break; \
723 case 0xb: meg = 512; break; \
724 } \
725 meg; \
726})
727static inline int __init get_mem_size(void)
728{
99d95bbd
MH		 729#if defined(EBIU_SDBCTL)
730# if defined(BF561_FAMILY)
a086ee22
MF		 731 int ret = 0;
732 u32 sdbctl = bfin_read_EBIU_SDBCTL();
733 ret += EBSZ_TO_MEG(sdbctl >> 0);
734 ret += EBSZ_TO_MEG(sdbctl >> 8);
735 ret += EBSZ_TO_MEG(sdbctl >> 16);
736 ret += EBSZ_TO_MEG(sdbctl >> 24);
737 return ret;
99d95bbd 738# else
a086ee22 739 return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
99d95bbd
MH		 740# endif
741#elif defined(EBIU_DDRCTL1)
1e78042c
MH		 742 u32 ddrctl = bfin_read_EBIU_DDRCTL1();
743 int ret = 0;
744 switch (ddrctl & 0xc0000) {
745 case DEVSZ_64: ret = 64 / 8;
746 case DEVSZ_128: ret = 128 / 8;
747 case DEVSZ_256: ret = 256 / 8;
748 case DEVSZ_512: ret = 512 / 8;
749 }
750 switch (ddrctl & 0x30000) {
751 case DEVWD_4: ret *= 2;
752 case DEVWD_8: ret *= 2;
753 case DEVWD_16: break;
a086ee22 754 }
b1b154e5
MF		 755 if ((ddrctl & 0xc000) == 0x4000)
756 ret *= 2;
1e78042c 757 return ret;
a086ee22
MF		 758#endif
759 BUG();
760}
761
856783b3
YL		 762void __init setup_arch(char **cmdline_p)
763{
9f8e895d 764 unsigned long sclk, cclk;
856783b3
YL		 765
766#ifdef CONFIG_DUMMY_CONSOLE
767 conswitchp = &dummy_con;
768#endif
769
770#if defined(CONFIG_CMDLINE_BOOL)
771 strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
772 command_line[sizeof(command_line) - 1] = 0;
773#endif
774
775 /* Keep a copy of command line */
776 *cmdline_p = &command_line[0];
777 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
778 boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
779
780 /* setup memory defaults from the user config */
781 physical_mem_end = 0;
a086ee22 782 _ramend = get_mem_size() * 1024 * 1024;
856783b3
YL		 783
784 memset(&bfin_memmap, 0, sizeof(bfin_memmap));
785
786 parse_cmdline_early(&command_line[0]);
787
788 if (physical_mem_end == 0)
789 physical_mem_end = _ramend;
790
791 memory_setup();
792
7e64acab
MF		 793 /* Initialize Async memory banks */
794 bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
795 bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
796 bfin_write_EBIU_AMGCTL(AMGCTLVAL);
797#ifdef CONFIG_EBIU_MBSCTLVAL
798 bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
799 bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
800 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
801#endif
802
856783b3
YL		 803 cclk = get_cclk();
804 sclk = get_sclk();
805
806#if !defined(CONFIG_BFIN_KERNEL_CLOCK)
807 if (ANOMALY_05000273 && cclk == sclk)
808 panic("ANOMALY 05000273, SCLK can not be same as CCLK");
809#endif
810
811#ifdef BF561_FAMILY
812 if (ANOMALY_05000266) {
813 bfin_read_IMDMA_D0_IRQ_STATUS();
814 bfin_read_IMDMA_D1_IRQ_STATUS();
815 }
816#endif
817 printk(KERN_INFO "Hardware Trace ");
818 if (bfin_read_TBUFCTL() & 0x1)
819 printk("Active ");
820 else
821 printk("Off ");
822 if (bfin_read_TBUFCTL() & 0x2)
823 printk("and Enabled\n");
824 else
825 printk("and Disabled\n");
826
827#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
828 /* we need to initialize the Flashrom device here since we might
829 * do things with flash early on in the boot
830 */
831 flash_probe();
832#endif
833
7728ec33
RG		 834 _bfin_swrst = bfin_read_SWRST();
835
0c7a6b21
RG		 836#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
837 bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
838#endif
839#ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
840 bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
841#endif
2d200980 842
8f65873e
GY		 843#ifdef CONFIG_SMP
844 if (_bfin_swrst & SWRST_DBL_FAULT_A) {
845#else
0c7a6b21 846 if (_bfin_swrst & RESET_DOUBLE) {
8f65873e 847#endif
0c7a6b21
RG		 848 printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
849#ifdef CONFIG_DEBUG_DOUBLEFAULT
850 /* We assume the crashing kernel, and the current symbol table match */
851 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
852 (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx);
853 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr);
854 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr);
855#endif
856 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
857 init_retx);
858 } else if (_bfin_swrst & RESET_WDOG)
7728ec33
RG		 859 printk(KERN_INFO "Recovering from Watchdog event\n");
860 else if (_bfin_swrst & RESET_SOFTWARE)
861 printk(KERN_NOTICE "Reset caused by Software reset\n");
862
550d5538 863 printk(KERN_INFO "Blackfin support (C) 2004-2008 Analog Devices, Inc.\n");
de3025f4
JZ		 864 if (bfin_compiled_revid() == 0xffff)
865 printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU);
866 else if (bfin_compiled_revid() == -1)
867 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
868 else
869 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
e482cad2
RG		 870
871 if (unlikely(CPUID != bfin_cpuid()))
872 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
873 CPU, bfin_cpuid(), bfin_revid());
874 else {
875 if (bfin_revid() != bfin_compiled_revid()) {
876 if (bfin_compiled_revid() == -1)
877 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
878 bfin_revid());
879 else if (bfin_compiled_revid() != 0xffff)
880 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
881 bfin_compiled_revid(), bfin_revid());
882 }
da986b9f 883 if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
e482cad2
RG		 884 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
885 CPU, bfin_revid());
de3025f4 886 }
0c0497c2 887
1394f032
BW		 888 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
889
b5c0e2e8 890 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
8f65873e 891 cclk / 1000000, sclk / 1000000);
1394f032 892
1aafd909 893 if (ANOMALY_05000273 && (cclk >> 1) <= sclk)
1394f032 894 printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
1394f032 895
856783b3 896 setup_bootmem_allocator();
1394f032 897
1394f032
BW		 898 paging_init();
899
7adfb58f
BS		 900 /* Copy atomic sequences to their fixed location, and sanity check that
901 these locations are the ones that we advertise to userspace. */
902 memcpy((void *)FIXED_CODE_START, &fixed_code_start,
903 FIXED_CODE_END - FIXED_CODE_START);
904 BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
905 != SIGRETURN_STUB - FIXED_CODE_START);
906 BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
907 != ATOMIC_XCHG32 - FIXED_CODE_START);
908 BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
909 != ATOMIC_CAS32 - FIXED_CODE_START);
910 BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
911 != ATOMIC_ADD32 - FIXED_CODE_START);
912 BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
913 != ATOMIC_SUB32 - FIXED_CODE_START);
914 BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
915 != ATOMIC_IOR32 - FIXED_CODE_START);
916 BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
917 != ATOMIC_AND32 - FIXED_CODE_START);
918 BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
919 != ATOMIC_XOR32 - FIXED_CODE_START);
9f336a53
RG		 920 BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
921 != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
29440a2b 922
8f65873e
GY		 923#ifdef CONFIG_SMP
924 platform_init_cpus();
925#endif
8be80ed3 926 init_exception_vectors();
8f65873e 927 bfin_cache_init(); /* Initialize caches for the boot CPU */
1394f032
BW		 928}
929
1394f032
BW		 930static int __init topology_init(void)
931{
8f65873e
GY		 932 unsigned int cpu;
933 /* Record CPU-private information for the boot processor. */
934 bfin_setup_cpudata(0);
6cda2e90
MH		 935
936 for_each_possible_cpu(cpu) {
8f65873e 937 register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
6cda2e90
MH		 938 }
939
1394f032 940 return 0;
1394f032
BW		 941}
942
943subsys_initcall(topology_init);
944
7f1e2f98
MF		 945/* Get the input clock frequency */
946static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
947static u_long get_clkin_hz(void)
948{
949 return cached_clkin_hz;
950}
951static int __init early_init_clkin_hz(char *buf)
952{
953 cached_clkin_hz = simple_strtoul(buf, NULL, 0);
508808cd
MF		 954#ifdef BFIN_KERNEL_CLOCK
955 if (cached_clkin_hz != CONFIG_CLKIN_HZ)
956 panic("cannot change clkin_hz when reprogramming clocks");
957#endif
7f1e2f98
MF		 958 return 1;
959}
960early_param("clkin_hz=", early_init_clkin_hz);
961
3a2521fa
MF		 962/* Get the voltage input multiplier */
963static u_long cached_vco_pll_ctl, cached_vco;
52a07812 964static u_long get_vco(void)
1394f032
BW		 965{
966 u_long msel;
1394f032 967
3a2521fa
MF		 968 u_long pll_ctl = bfin_read_PLL_CTL();
969 if (pll_ctl == cached_vco_pll_ctl)
970 return cached_vco;
971 else
972 cached_vco_pll_ctl = pll_ctl;
973
974 msel = (pll_ctl >> 9) & 0x3F;
1394f032
BW		 975 if (0 == msel)
976 msel = 64;
977
7f1e2f98 978 cached_vco = get_clkin_hz();
3a2521fa
MF		 979 cached_vco >>= (1 & pll_ctl); /* DF bit */
980 cached_vco *= msel;
981 return cached_vco;
1394f032
BW		 982}
983
2f6cf7bf 984/* Get the Core clock */
3a2521fa 985static u_long cached_cclk_pll_div, cached_cclk;
1394f032
BW		 986u_long get_cclk(void)
987{
988 u_long csel, ssel;
3a2521fa 989
1394f032 990 if (bfin_read_PLL_STAT() & 0x1)
7f1e2f98 991 return get_clkin_hz();
1394f032
BW		 992
993 ssel = bfin_read_PLL_DIV();
3a2521fa
MF		 994 if (ssel == cached_cclk_pll_div)
995 return cached_cclk;
996 else
997 cached_cclk_pll_div = ssel;
998
1394f032
BW		 999 csel = ((ssel >> 4) & 0x03);
1000 ssel &= 0xf;
1001 if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
3a2521fa
MF		 1002 cached_cclk = get_vco() / ssel;
1003 else
1004 cached_cclk = get_vco() >> csel;
1005 return cached_cclk;
1394f032 1006}
1394f032
BW		 1007EXPORT_SYMBOL(get_cclk);
1008
1009/* Get the System clock */
3a2521fa 1010static u_long cached_sclk_pll_div, cached_sclk;
1394f032
BW		 1011u_long get_sclk(void)
1012{
1013 u_long ssel;
1014
1015 if (bfin_read_PLL_STAT() & 0x1)
7f1e2f98 1016 return get_clkin_hz();
1394f032 1017
3a2521fa
MF		 1018 ssel = bfin_read_PLL_DIV();
1019 if (ssel == cached_sclk_pll_div)
1020 return cached_sclk;
1021 else
1022 cached_sclk_pll_div = ssel;
1023
1024 ssel &= 0xf;
1394f032
BW		 1025 if (0 == ssel) {
1026 printk(KERN_WARNING "Invalid System Clock\n");
1027 ssel = 1;
1028 }
1029
3a2521fa
MF		 1030 cached_sclk = get_vco() / ssel;
1031 return cached_sclk;
1394f032 1032}
1394f032
BW		 1033EXPORT_SYMBOL(get_sclk);
1034
2f6cf7bf
MF		 1035unsigned long sclk_to_usecs(unsigned long sclk)
1036{
1754a5d9
MF		 1037 u64 tmp = USEC_PER_SEC * (u64)sclk;
1038 do_div(tmp, get_sclk());
1039 return tmp;
2f6cf7bf
MF		 1040}
1041EXPORT_SYMBOL(sclk_to_usecs);
1042
1043unsigned long usecs_to_sclk(unsigned long usecs)
1044{
1754a5d9
MF		 1045 u64 tmp = get_sclk() * (u64)usecs;
1046 do_div(tmp, USEC_PER_SEC);
1047 return tmp;
2f6cf7bf
MF		 1048}
1049EXPORT_SYMBOL(usecs_to_sclk);
1050
1394f032
BW		 1051/*
1052 * Get CPU information for use by the procfs.
1053 */
1054static int show_cpuinfo(struct seq_file *m, void *v)
1055{
066954a3 1056 char *cpu, *mmu, *fpu, *vendor, *cache;
1394f032 1057 uint32_t revid;
275123e8 1058 int cpu_num = *(unsigned int *)v;
a5f0717e 1059 u_long sclk, cclk;
9de3a0b6 1060 u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
275123e8 1061 struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
1394f032
BW		 1062
1063 cpu = CPU;
1064 mmu = "none";
1065 fpu = "none";
1066 revid = bfin_revid();
1394f032 1067
1394f032 1068 sclk = get_sclk();
a5f0717e 1069 cclk = get_cclk();
1394f032 1070
73b0c0b0 1071 switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
066954a3
MF		 1072 case 0xca:
1073 vendor = "Analog Devices";
73b0c0b0
RG		 1074 break;
1075 default:
066954a3
MF		 1076 vendor = "unknown";
1077 break;
73b0c0b0 1078 }
1394f032 1079
275123e8 1080 seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
e482cad2
RG		 1081
1082 if (CPUID == bfin_cpuid())
1083 seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
1084 else
1085 seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
1086 CPUID, bfin_cpuid());
1087
1088 seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
1089 "stepping\t: %d\n",
a5f0717e 1090 cpu, cclk/1000000, sclk/1000000,
253bcf4f
RG		 1091#ifdef CONFIG_MPU
1092 "mpu on",
1093#else
1094 "mpu off",
1095#endif
73b0c0b0
RG		 1096 revid);
1097
1098 seq_printf(m, "cpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
a5f0717e 1099 cclk/1000000, cclk%1000000,
73b0c0b0
RG		 1100 sclk/1000000, sclk%1000000);
1101 seq_printf(m, "bogomips\t: %lu.%02lu\n"
1102 "Calibration\t: %lu loops\n",
8f65873e
GY		 1103 (cpudata->loops_per_jiffy * HZ) / 500000,
1104 ((cpudata->loops_per_jiffy * HZ) / 5000) % 100,
1105 (cpudata->loops_per_jiffy * HZ));
73b0c0b0
RG		 1106
1107 /* Check Cache configutation */
8f65873e 1108 switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
1f83b8f1 1109 case ACACHE_BSRAM:
066954a3 1110 cache = "dbank-A/B\t: cache/sram";
1f83b8f1
MF		 1111 dcache_size = 16;
1112 dsup_banks = 1;
1113 break;
1114 case ACACHE_BCACHE:
066954a3 1115 cache = "dbank-A/B\t: cache/cache";
1f83b8f1
MF		 1116 dcache_size = 32;
1117 dsup_banks = 2;
1118 break;
1119 case ASRAM_BSRAM:
066954a3 1120 cache = "dbank-A/B\t: sram/sram";
1f83b8f1
MF		 1121 dcache_size = 0;
1122 dsup_banks = 0;
1123 break;
1124 default:
066954a3 1125 cache = "unknown";
73b0c0b0
RG		 1126 dcache_size = 0;
1127 dsup_banks = 0;
1394f032
BW		 1128 break;
1129 }
1130
73b0c0b0 1131 /* Is it turned on? */
8f65873e 1132 if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
73b0c0b0 1133 dcache_size = 0;
1394f032 1134
8f65873e 1135 if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
9de3a0b6
RG		 1136 icache_size = 0;
1137
73b0c0b0
RG		 1138 seq_printf(m, "cache size\t: %d KB(L1 icache) "
1139 "%d KB(L1 dcache-%s) %d KB(L2 cache)\n",
9de3a0b6 1140 icache_size, dcache_size,
73b0c0b0
RG		 1141#if defined CONFIG_BFIN_WB
1142 "wb"
1143#elif defined CONFIG_BFIN_WT
1144 "wt"
1145#endif
da27abb7 1146 "", 0);
73b0c0b0
RG		 1147
1148 seq_printf(m, "%s\n", cache);
1149
9de3a0b6
RG		 1150 if (icache_size)
1151 seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
1152 BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
1153 else
1154 seq_printf(m, "icache setup\t: off\n");
1155
1394f032 1156 seq_printf(m,
73b0c0b0 1157 "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
3bebca2d
RG		 1158 dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
1159 BFIN_DLINES);
8f65873e 1160#ifdef __ARCH_SYNC_CORE_DCACHE
275123e8 1161 seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count);
8f65873e 1162#endif
3bebca2d 1163#ifdef CONFIG_BFIN_ICACHE_LOCK
8f65873e 1164 switch ((cpudata->imemctl >> 3) & WAYALL_L) {
1394f032
BW		 1165 case WAY0_L:
1166 seq_printf(m, "Way0 Locked-Down\n");
1167 break;
1168 case WAY1_L:
1169 seq_printf(m, "Way1 Locked-Down\n");
1170 break;
1171 case WAY01_L:
1172 seq_printf(m, "Way0,Way1 Locked-Down\n");
1173 break;
1174 case WAY2_L:
1175 seq_printf(m, "Way2 Locked-Down\n");
1176 break;
1177 case WAY02_L:
1178 seq_printf(m, "Way0,Way2 Locked-Down\n");
1179 break;
1180 case WAY12_L:
1181 seq_printf(m, "Way1,Way2 Locked-Down\n");
1182 break;
1183 case WAY012_L:
1184 seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
1185 break;
1186 case WAY3_L:
1187 seq_printf(m, "Way3 Locked-Down\n");
1188 break;
1189 case WAY03_L:
1190 seq_printf(m, "Way0,Way3 Locked-Down\n");
1191 break;
1192 case WAY13_L:
1193 seq_printf(m, "Way1,Way3 Locked-Down\n");
1194 break;
1195 case WAY013_L:
1196 seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
1197 break;
1198 case WAY32_L:
1199 seq_printf(m, "Way3,Way2 Locked-Down\n");
1200 break;
1201 case WAY320_L:
1202 seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
1203 break;
1204 case WAY321_L:
1205 seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
1206 break;
1207 case WAYALL_L:
1208 seq_printf(m, "All Ways are locked\n");
1209 break;
1210 default:
1211 seq_printf(m, "No Ways are locked\n");
1212 }
8f65873e 1213#endif
275123e8
MF		 1214
1215 if (cpu_num != num_possible_cpus() - 1)
8f65873e
GY		 1216 return 0;
1217
275123e8
MF		 1218 if (L2_LENGTH)
1219 seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
066954a3 1220 seq_printf(m, "board name\t: %s\n", bfin_board_name);
73b0c0b0
RG		 1221 seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
1222 physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
1223 seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n",
1224 ((int)memory_end - (int)_stext) >> 10,
1225 _stext,
1226 (void *)memory_end);
8f65873e 1227 seq_printf(m, "\n");
73b0c0b0 1228
1394f032
BW		 1229 return 0;
1230}
1231
1232static void *c_start(struct seq_file *m, loff_t *pos)
1233{
55f2feae
GY		 1234 if (*pos == 0)
1235 *pos = first_cpu(cpu_online_map);
1236 if (*pos >= num_online_cpus())
1237 return NULL;
1238
1239 return pos;
1394f032
BW		 1240}
1241
1242static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1243{
55f2feae
GY		 1244 *pos = next_cpu(*pos, cpu_online_map);
1245
1394f032
BW		 1246 return c_start(m, pos);
1247}
1248
1249static void c_stop(struct seq_file *m, void *v)
1250{
1251}
1252
03a44825 1253const struct seq_operations cpuinfo_op = {
1394f032
BW		 1254 .start = c_start,
1255 .next = c_next,
1256 .stop = c_stop,
1257 .show = show_cpuinfo,
1258};
1259
5e10b4a6 1260void __init cmdline_init(const char *r0)
1394f032
BW		 1261{
1262 if (r0)
52a07812 1263 strncpy(command_line, r0, COMMAND_LINE_SIZE);
1394f032 1264}
Linux kernel - Deliverables
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