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Blackfin arch: introducing bfin_addr_dcachable
[deliverable/linux.git] / arch / blackfin / mach-bf537 / boards / stamp.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/mach-bf537/boards/stamp.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
fc68911e 32#include <linux/kernel.h>
1394f032
BW		 33#include <linux/platform_device.h>
34#include <linux/mtd/mtd.h>
fc68911e 35#include <linux/mtd/nand.h>
1394f032 36#include <linux/mtd/partitions.h>
fc68911e 37#include <linux/mtd/plat-ram.h>
de8c43f2 38#include <linux/mtd/physmap.h>
1394f032
BW		 39#include <linux/spi/spi.h>
40#include <linux/spi/flash.h>
41#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5 42#include <linux/usb/isp1362.h>
1394f032 43#endif
0a87e3e9 44#include <linux/ata_platform.h>
1394f032
BW		 45#include <linux/irq.h>
46#include <linux/interrupt.h>
81d9c7f2 47#include <linux/i2c.h>
27f5d75a 48#include <linux/usb/sl811.h>
c6c4d7bb 49#include <asm/dma.h>
1f83b8f1 50#include <asm/bfin5xx_spi.h>
c6c4d7bb 51#include <asm/reboot.h>
5d448dd5 52#include <asm/portmux.h>
14b03204 53#include <asm/dpmc.h>
1394f032
BW		 54#include <linux/spi/ad7877.h>
55
56/*
57 * Name the Board for the /proc/cpuinfo
58 */
066954a3 59const char bfin_board_name[] = "ADDS-BF537-STAMP";
1394f032
BW		 60
61/*
62 * Driver needs to know address, irq and flag pin.
63 */
64
65#define ISP1761_BASE 0x203C0000
66#define ISP1761_IRQ IRQ_PF7
67
68#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
69static struct resource bfin_isp1761_resources[] = {
70 [0] = {
71 .name = "isp1761-regs",
72 .start = ISP1761_BASE + 0x00000000,
73 .end = ISP1761_BASE + 0x000fffff,
74 .flags = IORESOURCE_MEM,
75 },
76 [1] = {
77 .start = ISP1761_IRQ,
78 .end = ISP1761_IRQ,
79 .flags = IORESOURCE_IRQ,
80 },
81};
82
83static struct platform_device bfin_isp1761_device = {
84 .name = "isp1761",
85 .id = 0,
86 .num_resources = ARRAY_SIZE(bfin_isp1761_resources),
87 .resource = bfin_isp1761_resources,
88};
89
90static struct platform_device *bfin_isp1761_devices[] = {
91 &bfin_isp1761_device,
92};
93
94int __init bfin_isp1761_init(void)
95{
1f83b8f1 96 unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
1394f032 97
b85d858b 98 printk(KERN_INFO "%s(): registering device resources\n", __func__);
1394f032
BW		 99 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
100
101 return platform_add_devices(bfin_isp1761_devices, num_devices);
102}
103
104void __exit bfin_isp1761_exit(void)
105{
106 platform_device_unregister(&bfin_isp1761_device);
107}
108
109arch_initcall(bfin_isp1761_init);
110#endif
111
2463ef22
MH		 112#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
113#include <linux/input.h>
114#include <linux/gpio_keys.h>
115
116static struct gpio_keys_button bfin_gpio_keys_table[] = {
117 {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
118 {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
119 {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
120 {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
121};
122
123static struct gpio_keys_platform_data bfin_gpio_keys_data = {
124 .buttons = bfin_gpio_keys_table,
125 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
126};
127
128static struct platform_device bfin_device_gpiokeys = {
129 .name = "gpio-keys",
130 .dev = {
131 .platform_data = &bfin_gpio_keys_data,
132 },
133};
134#endif
135
cad2ab65
MF		 136static struct resource bfin_gpios_resources = {
137 .start = 0,
138 .end = MAX_BLACKFIN_GPIOS - 1,
139 .flags = IORESOURCE_IRQ,
140};
141
142static struct platform_device bfin_gpios_device = {
143 .name = "simple-gpio",
144 .id = -1,
145 .num_resources = 1,
146 .resource = &bfin_gpios_resources,
147};
148
1394f032
BW		 149#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
150static struct resource bfin_pcmcia_cf_resources[] = {
151 {
152 .start = 0x20310000, /* IO PORT */
153 .end = 0x20312000,
154 .flags = IORESOURCE_MEM,
1f83b8f1 155 }, {
d2d50aa9 156 .start = 0x20311000, /* Attribute Memory */
1394f032
BW		 157 .end = 0x20311FFF,
158 .flags = IORESOURCE_MEM,
1f83b8f1 159 }, {
1394f032
BW		 160 .start = IRQ_PF4,
161 .end = IRQ_PF4,
162 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
1f83b8f1 163 }, {
1394f032
BW		 164 .start = 6, /* Card Detect PF6 */
165 .end = 6,
166 .flags = IORESOURCE_IRQ,
167 },
168};
169
170static struct platform_device bfin_pcmcia_cf_device = {
171 .name = "bfin_cf_pcmcia",
172 .id = -1,
173 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
174 .resource = bfin_pcmcia_cf_resources,
175};
176#endif
177
178#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
179static struct platform_device rtc_device = {
180 .name = "rtc-bfin",
181 .id = -1,
182};
183#endif
184
185#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
186static struct resource smc91x_resources[] = {
187 {
188 .name = "smc91x-regs",
189 .start = 0x20300300,
190 .end = 0x20300300 + 16,
191 .flags = IORESOURCE_MEM,
1f83b8f1 192 }, {
1394f032
BW		 193
194 .start = IRQ_PF7,
195 .end = IRQ_PF7,
196 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
197 },
198};
199static struct platform_device smc91x_device = {
200 .name = "smc91x",
201 .id = 0,
202 .num_resources = ARRAY_SIZE(smc91x_resources),
203 .resource = smc91x_resources,
204};
205#endif
206
f40d24d9
AL		 207#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
208static struct resource dm9000_resources[] = {
209 [0] = {
210 .start = 0x203FB800,
211 .end = 0x203FB800 + 8,
212 .flags = IORESOURCE_MEM,
213 },
214 [1] = {
215 .start = IRQ_PF9,
216 .end = IRQ_PF9,
217 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
218 },
219};
220
221static struct platform_device dm9000_device = {
222 .name = "dm9000",
223 .id = -1,
224 .num_resources = ARRAY_SIZE(dm9000_resources),
225 .resource = dm9000_resources,
226};
227#endif
228
561cc18b
MH		 229#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
230static struct resource ax88180_resources[] = {
231 [0] = {
232 .start = 0x20300000,
233 .end = 0x20300000 + 0x8000,
234 .flags = IORESOURCE_MEM,
235 },
236 [1] = {
237 .start = IRQ_PF7,
238 .end = IRQ_PF7,
239 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL),
240 },
241};
242
243static struct platform_device ax88180_device = {
244 .name = "ax88180",
245 .id = -1,
246 .num_resources = ARRAY_SIZE(ax88180_resources),
247 .resource = ax88180_resources,
248};
249#endif
250
1394f032
BW		 251#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
252static struct resource sl811_hcd_resources[] = {
253 {
254 .start = 0x20340000,
255 .end = 0x20340000,
256 .flags = IORESOURCE_MEM,
1f83b8f1 257 }, {
1394f032
BW		 258 .start = 0x20340004,
259 .end = 0x20340004,
260 .flags = IORESOURCE_MEM,
1f83b8f1 261 }, {
1394f032
BW		 262 .start = CONFIG_USB_SL811_BFIN_IRQ,
263 .end = CONFIG_USB_SL811_BFIN_IRQ,
264 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
265 },
266};
267
268#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
269void sl811_port_power(struct device *dev, int is_on)
270{
c6c4d7bb 271 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
acbcd263 272 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
1394f032
BW		 273}
274#endif
275
276static struct sl811_platform_data sl811_priv = {
277 .potpg = 10,
278 .power = 250, /* == 500mA */
279#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
280 .port_power = &sl811_port_power,
281#endif
282};
283
284static struct platform_device sl811_hcd_device = {
285 .name = "sl811-hcd",
286 .id = 0,
287 .dev = {
288 .platform_data = &sl811_priv,
289 },
290 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
291 .resource = sl811_hcd_resources,
292};
293#endif
294
295#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
296static struct resource isp1362_hcd_resources[] = {
297 {
298 .start = 0x20360000,
299 .end = 0x20360000,
300 .flags = IORESOURCE_MEM,
1f83b8f1 301 }, {
1394f032
BW		 302 .start = 0x20360004,
303 .end = 0x20360004,
304 .flags = IORESOURCE_MEM,
1f83b8f1 305 }, {
1394f032
BW		 306 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
307 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
308 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
309 },
310};
311
312static struct isp1362_platform_data isp1362_priv = {
313 .sel15Kres = 1,
314 .clknotstop = 0,
315 .oc_enable = 0,
316 .int_act_high = 0,
317 .int_edge_triggered = 0,
318 .remote_wakeup_connected = 0,
319 .no_power_switching = 1,
320 .power_switching_mode = 0,
321};
322
323static struct platform_device isp1362_hcd_device = {
324 .name = "isp1362-hcd",
325 .id = 0,
326 .dev = {
327 .platform_data = &isp1362_priv,
328 },
329 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
330 .resource = isp1362_hcd_resources,
331};
332#endif
333
334#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
335static struct platform_device bfin_mac_device = {
336 .name = "bfin_mac",
337};
338#endif
339
340#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
341static struct resource net2272_bfin_resources[] = {
342 {
343 .start = 0x20300000,
344 .end = 0x20300000 + 0x100,
345 .flags = IORESOURCE_MEM,
1f83b8f1 346 }, {
1394f032
BW		 347 .start = IRQ_PF7,
348 .end = IRQ_PF7,
349 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
350 },
351};
352
353static struct platform_device net2272_bfin_device = {
354 .name = "net2272",
355 .id = -1,
356 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
357 .resource = net2272_bfin_resources,
358};
359#endif
360
fc68911e
MF		 361#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
362#ifdef CONFIG_MTD_PARTITIONS
363const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
364
365static struct mtd_partition bfin_plat_nand_partitions[] = {
366 {
aa582977 367 .name = "linux kernel(nand)",
fc68911e
MF		 368 .size = 0x400000,
369 .offset = 0,
370 }, {
aa582977 371 .name = "file system(nand)",
fc68911e
MF		 372 .size = MTDPART_SIZ_FULL,
373 .offset = MTDPART_OFS_APPEND,
374 },
375};
376#endif
377
378#define BFIN_NAND_PLAT_CLE 2
379#define BFIN_NAND_PLAT_ALE 1
380static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
381{
382 struct nand_chip *this = mtd->priv;
383
384 if (cmd == NAND_CMD_NONE)
385 return;
386
387 if (ctrl & NAND_CLE)
388 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
389 else
390 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
391}
392
393#define BFIN_NAND_PLAT_READY GPIO_PF3
394static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
395{
396 return gpio_get_value(BFIN_NAND_PLAT_READY);
397}
398
399static struct platform_nand_data bfin_plat_nand_data = {
400 .chip = {
401 .chip_delay = 30,
402#ifdef CONFIG_MTD_PARTITIONS
403 .part_probe_types = part_probes,
404 .partitions = bfin_plat_nand_partitions,
405 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
406#endif
407 },
408 .ctrl = {
409 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
410 .dev_ready = bfin_plat_nand_dev_ready,
411 },
412};
413
414#define MAX(x, y) (x > y ? x : y)
415static struct resource bfin_plat_nand_resources = {
416 .start = 0x20212000,
417 .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
418 .flags = IORESOURCE_IO,
419};
420
421static struct platform_device bfin_async_nand_device = {
422 .name = "gen_nand",
423 .id = -1,
424 .num_resources = 1,
425 .resource = &bfin_plat_nand_resources,
426 .dev = {
427 .platform_data = &bfin_plat_nand_data,
428 },
429};
430
431static void bfin_plat_nand_init(void)
432{
433 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
434}
435#else
436static void bfin_plat_nand_init(void) {}
437#endif
438
793dc27b 439#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF		 440static struct mtd_partition stamp_partitions[] = {
441 {
aa582977 442 .name = "bootloader(nor)",
edf05641 443 .size = 0x40000,
de8c43f2
MF		 444 .offset = 0,
445 }, {
aa582977 446 .name = "linux kernel(nor)",
de8c43f2
MF		 447 .size = 0xE0000,
448 .offset = MTDPART_OFS_APPEND,
449 }, {
aa582977 450 .name = "file system(nor)",
edf05641 451 .size = 0x400000 - 0x40000 - 0xE0000 - 0x10000,
de8c43f2
MF		 452 .offset = MTDPART_OFS_APPEND,
453 }, {
aa582977 454 .name = "MAC Address(nor)",
de8c43f2
MF		 455 .size = MTDPART_SIZ_FULL,
456 .offset = 0x3F0000,
457 .mask_flags = MTD_WRITEABLE,
458 }
459};
460
461static struct physmap_flash_data stamp_flash_data = {
462 .width = 2,
463 .parts = stamp_partitions,
464 .nr_parts = ARRAY_SIZE(stamp_partitions),
465};
466
467static struct resource stamp_flash_resource = {
468 .start = 0x20000000,
469 .end = 0x203fffff,
470 .flags = IORESOURCE_MEM,
471};
472
473static struct platform_device stamp_flash_device = {
474 .name = "physmap-flash",
475 .id = 0,
476 .dev = {
477 .platform_data = &stamp_flash_data,
478 },
479 .num_resources = 1,
480 .resource = &stamp_flash_resource,
481};
793dc27b 482#endif
de8c43f2 483
1394f032
BW		 484#if defined(CONFIG_MTD_M25P80) \
485 || defined(CONFIG_MTD_M25P80_MODULE)
486static struct mtd_partition bfin_spi_flash_partitions[] = {
487 {
aa582977 488 .name = "bootloader(spi)",
edf05641 489 .size = 0x00040000,
1394f032
BW		 490 .offset = 0,
491 .mask_flags = MTD_CAP_ROM
1f83b8f1 492 }, {
aa582977 493 .name = "linux kernel(spi)",
1394f032 494 .size = 0xe0000,
edf05641 495 .offset = MTDPART_OFS_APPEND,
1f83b8f1 496 }, {
aa582977 497 .name = "file system(spi)",
edf05641
MF		 498 .size = MTDPART_SIZ_FULL,
499 .offset = MTDPART_OFS_APPEND,
1394f032
BW		 500 }
501};
502
503static struct flash_platform_data bfin_spi_flash_data = {
504 .name = "m25p80",
505 .parts = bfin_spi_flash_partitions,
506 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
507 .type = "m25p64",
508};
509
510/* SPI flash chip (m25p64) */
511static struct bfin5xx_spi_chip spi_flash_chip_info = {
512 .enable_dma = 0, /* use dma transfer with this chip*/
513 .bits_per_word = 8,
514};
515#endif
516
517#if defined(CONFIG_SPI_ADC_BF533) \
518 || defined(CONFIG_SPI_ADC_BF533_MODULE)
519/* SPI ADC chip */
520static struct bfin5xx_spi_chip spi_adc_chip_info = {
521 .enable_dma = 1, /* use dma transfer with this chip*/
522 .bits_per_word = 16,
523};
524#endif
525
526#if defined(CONFIG_SND_BLACKFIN_AD1836) \
527 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
528static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
529 .enable_dma = 0,
530 .bits_per_word = 16,
531};
532#endif
533
534#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
535static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
536 .enable_dma = 0,
537 .bits_per_word = 16,
538};
539#endif
540
541#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
542static struct bfin5xx_spi_chip spi_mmc_chip_info = {
543 .enable_dma = 1,
544 .bits_per_word = 8,
545};
546#endif
547
548#if defined(CONFIG_PBX)
549static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
550 .ctl_reg = 0x4, /* send zero */
551 .enable_dma = 0,
552 .bits_per_word = 8,
553 .cs_change_per_word = 1,
554};
555#endif
556
1394f032
BW		 557#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
558static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
1394f032
BW		 559 .enable_dma = 0,
560 .bits_per_word = 16,
561};
562
563static const struct ad7877_platform_data bfin_ad7877_ts_info = {
564 .model = 7877,
565 .vref_delay_usecs = 50, /* internal, no capacitor */
566 .x_plate_ohms = 419,
567 .y_plate_ohms = 486,
568 .pressure_max = 1000,
569 .pressure_min = 0,
570 .stopacq_polarity = 1,
571 .first_conversion_delay = 3,
572 .acquisition_time = 1,
573 .averaging = 1,
574 .pen_down_acc_interval = 1,
575};
576#endif
577
6e668936
MH		 578#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
579static struct bfin5xx_spi_chip spidev_chip_info = {
580 .enable_dma = 0,
581 .bits_per_word = 8,
582};
583#endif
584
2043f3f7
MH		 585#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
586static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
587 .enable_dma = 0,
588 .bits_per_word = 8,
589};
590#endif
591
8e9d5c7d
MH		 592#if defined(CONFIG_MTD_DATAFLASH) \
593 || defined(CONFIG_MTD_DATAFLASH_MODULE)
ceac2651
MH		 594
595static struct mtd_partition bfin_spi_dataflash_partitions[] = {
596 {
597 .name = "bootloader(spi)",
598 .size = 0x00040000,
599 .offset = 0,
600 .mask_flags = MTD_CAP_ROM
601 }, {
602 .name = "linux kernel(spi)",
603 .size = 0xe0000,
604 .offset = MTDPART_OFS_APPEND,
605 }, {
606 .name = "file system(spi)",
607 .size = MTDPART_SIZ_FULL,
608 .offset = MTDPART_OFS_APPEND,
609 }
610};
611
612static struct flash_platform_data bfin_spi_dataflash_data = {
613 .name = "SPI Dataflash",
614 .parts = bfin_spi_dataflash_partitions,
615 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
616};
617
8e9d5c7d
MH		 618/* DataFlash chip */
619static struct bfin5xx_spi_chip data_flash_chip_info = {
620 .enable_dma = 0, /* use dma transfer with this chip*/
621 .bits_per_word = 8,
622};
623#endif
624
1394f032
BW		 625static struct spi_board_info bfin_spi_board_info[] __initdata = {
626#if defined(CONFIG_MTD_M25P80) \
627 || defined(CONFIG_MTD_M25P80_MODULE)
628 {
629 /* the modalias must be the same as spi device driver name */
630 .modalias = "m25p80", /* Name of spi_driver for this device */
631 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 632 .bus_num = 0, /* Framework bus number */
1394f032
BW		 633 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
634 .platform_data = &bfin_spi_flash_data,
635 .controller_data = &spi_flash_chip_info,
636 .mode = SPI_MODE_3,
637 },
638#endif
8e9d5c7d
MH		 639#if defined(CONFIG_MTD_DATAFLASH) \
640 || defined(CONFIG_MTD_DATAFLASH_MODULE)
641 { /* DataFlash chip */
642 .modalias = "mtd_dataflash",
ceac2651 643 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
8e9d5c7d
MH		 644 .bus_num = 0, /* Framework bus number */
645 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
ceac2651 646 .platform_data = &bfin_spi_dataflash_data,
8e9d5c7d
MH		 647 .controller_data = &data_flash_chip_info,
648 .mode = SPI_MODE_3,
649 },
650#endif
1394f032
BW		 651#if defined(CONFIG_SPI_ADC_BF533) \
652 || defined(CONFIG_SPI_ADC_BF533_MODULE)
653 {
654 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
655 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 656 .bus_num = 0, /* Framework bus number */
1394f032
BW		 657 .chip_select = 1, /* Framework chip select. */
658 .platform_data = NULL, /* No spi_driver specific config */
659 .controller_data = &spi_adc_chip_info,
660 },
661#endif
662
663#if defined(CONFIG_SND_BLACKFIN_AD1836) \
664 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
665 {
666 .modalias = "ad1836-spi",
667 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 668 .bus_num = 0,
1394f032
BW		 669 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
670 .controller_data = &ad1836_spi_chip_info,
671 },
672#endif
673#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
674 {
675 .modalias = "ad9960-spi",
676 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 677 .bus_num = 0,
1394f032
BW		 678 .chip_select = 1,
679 .controller_data = &ad9960_spi_chip_info,
680 },
681#endif
682#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
683 {
684 .modalias = "spi_mmc_dummy",
111cf97d 685 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 686 .bus_num = 0,
1394f032
BW		 687 .chip_select = 0,
688 .platform_data = NULL,
689 .controller_data = &spi_mmc_chip_info,
690 .mode = SPI_MODE_3,
691 },
692 {
693 .modalias = "spi_mmc",
111cf97d 694 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 695 .bus_num = 0,
1394f032
BW		 696 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
697 .platform_data = NULL,
698 .controller_data = &spi_mmc_chip_info,
699 .mode = SPI_MODE_3,
700 },
701#endif
702#if defined(CONFIG_PBX)
703 {
1f83b8f1
MF		 704 .modalias = "fxs-spi",
705 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb
BW		 706 .bus_num = 0,
707 .chip_select = 8 - CONFIG_J11_JUMPER,
1f83b8f1 708 .controller_data = &spi_si3xxx_chip_info,
1394f032
BW		 709 .mode = SPI_MODE_3,
710 },
711 {
1f83b8f1
MF		 712 .modalias = "fxo-spi",
713 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb
BW		 714 .bus_num = 0,
715 .chip_select = 8 - CONFIG_J19_JUMPER,
1f83b8f1 716 .controller_data = &spi_si3xxx_chip_info,
1394f032
BW		 717 .mode = SPI_MODE_3,
718 },
719#endif
1394f032
BW		 720#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
721 {
722 .modalias = "ad7877",
723 .platform_data = &bfin_ad7877_ts_info,
724 .irq = IRQ_PF6,
725 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c7d48966 726 .bus_num = 0,
1394f032
BW		 727 .chip_select = 1,
728 .controller_data = &spi_ad7877_chip_info,
729 },
730#endif
6e668936
MH		 731#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
732 {
733 .modalias = "spidev",
734 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
735 .bus_num = 0,
736 .chip_select = 1,
737 .controller_data = &spidev_chip_info,
738 },
739#endif
2043f3f7
MH		 740#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
741 {
742 .modalias = "bfin-lq035q1-spi",
743 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
744 .bus_num = 0,
745 .chip_select = 1,
746 .controller_data = &lq035q1_spi_chip_info,
747 .mode = SPI_CPHA | SPI_CPOL,
748 },
749#endif
1394f032
BW		 750};
751
5bda2723 752#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1394f032 753/* SPI controller data */
c6c4d7bb 754static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032
BW		 755 .num_chipselect = 8,
756 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 757 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032
BW		 758};
759
c6c4d7bb
BW		 760/* SPI (0) */
761static struct resource bfin_spi0_resource[] = {
762 [0] = {
763 .start = SPI0_REGBASE,
764 .end = SPI0_REGBASE + 0xFF,
765 .flags = IORESOURCE_MEM,
766 },
767 [1] = {
768 .start = CH_SPI,
769 .end = CH_SPI,
770 .flags = IORESOURCE_IRQ,
771 },
772};
773
774static struct platform_device bfin_spi0_device = {
775 .name = "bfin-spi",
776 .id = 0, /* Bus number */
777 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
778 .resource = bfin_spi0_resource,
1394f032 779 .dev = {
c6c4d7bb 780 .platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032
BW		 781 },
782};
783#endif /* spi master and devices */
784
785#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
786static struct platform_device bfin_fb_device = {
c6c4d7bb
BW		 787 .name = "bf537-lq035",
788};
789#endif
790
791#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
792static struct platform_device bfin_fb_adv7393_device = {
793 .name = "bfin-adv7393",
1394f032
BW		 794};
795#endif
796
2043f3f7
MH		 797#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
798#include <asm/bfin-lq035q1.h>
799
800static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
801 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
802 .use_bl = 1,
803 .gpio_bl = GPIO_PF7,
804};
805
806static struct resource bfin_lq035q1_resources[] = {
807 {
808 .start = IRQ_PPI_ERROR,
809 .end = IRQ_PPI_ERROR,
810 .flags = IORESOURCE_IRQ,
811 },
812};
813
814static struct platform_device bfin_lq035q1_device = {
815 .name = "bfin-lq035q1",
816 .id = -1,
817 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
818 .resource = bfin_lq035q1_resources,
819 .dev = {
820 .platform_data = &bfin_lq035q1_data,
821 },
822};
823#endif
824
1394f032
BW		 825#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
826static struct resource bfin_uart_resources[] = {
233b28a9 827#ifdef CONFIG_SERIAL_BFIN_UART0
1394f032
BW		 828 {
829 .start = 0xFFC00400,
830 .end = 0xFFC004FF,
831 .flags = IORESOURCE_MEM,
233b28a9
SZ		 832 },
833#endif
834#ifdef CONFIG_SERIAL_BFIN_UART1
835 {
1394f032
BW		 836 .start = 0xFFC02000,
837 .end = 0xFFC020FF,
838 .flags = IORESOURCE_MEM,
839 },
233b28a9 840#endif
1394f032
BW		 841};
842
843static struct platform_device bfin_uart_device = {
844 .name = "bfin-uart",
845 .id = 1,
846 .num_resources = ARRAY_SIZE(bfin_uart_resources),
847 .resource = bfin_uart_resources,
848};
849#endif
850
5be36d22
GY		 851#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
852static struct resource bfin_sir_resources[] = {
853#ifdef CONFIG_BFIN_SIR0
854 {
855 .start = 0xFFC00400,
856 .end = 0xFFC004FF,
857 .flags = IORESOURCE_MEM,
858 },
859#endif
860#ifdef CONFIG_BFIN_SIR1
861 {
862 .start = 0xFFC02000,
863 .end = 0xFFC020FF,
864 .flags = IORESOURCE_MEM,
865 },
866#endif
867};
868
869static struct platform_device bfin_sir_device = {
870 .name = "bfin_sir",
871 .id = 0,
872 .num_resources = ARRAY_SIZE(bfin_sir_resources),
873 .resource = bfin_sir_resources,
874};
875#endif
876
1394f032 877#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
c6c4d7bb
BW		 878static struct resource bfin_twi0_resource[] = {
879 [0] = {
880 .start = TWI0_REGBASE,
881 .end = TWI0_REGBASE,
882 .flags = IORESOURCE_MEM,
883 },
884 [1] = {
885 .start = IRQ_TWI,
886 .end = IRQ_TWI,
887 .flags = IORESOURCE_IRQ,
888 },
889};
890
1394f032
BW		 891static struct platform_device i2c_bfin_twi_device = {
892 .name = "i2c-bfin-twi",
893 .id = 0,
c6c4d7bb
BW		 894 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
895 .resource = bfin_twi0_resource,
1394f032
BW		 896};
897#endif
898
81d9c7f2
BW		 899#ifdef CONFIG_I2C_BOARDINFO
900static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
901#if defined(CONFIG_JOYSTICK_AD7142) || defined(CONFIG_JOYSTICK_AD7142_MODULE)
902 {
903 I2C_BOARD_INFO("ad7142_joystick", 0x2C),
81d9c7f2
BW		 904 .irq = 55,
905 },
906#endif
907#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
908 {
909 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW		 910 },
911#endif
912#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
913 {
914 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
81d9c7f2
BW		 915 .irq = 72,
916 },
917#endif
918};
919#endif
920
1394f032
BW		 921#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
922static struct platform_device bfin_sport0_uart_device = {
923 .name = "bfin-sport-uart",
924 .id = 0,
925};
926
927static struct platform_device bfin_sport1_uart_device = {
928 .name = "bfin-sport-uart",
929 .id = 1,
930};
931#endif
932
c6c4d7bb 933#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
96b86e94 934#define PATA_INT IRQ_PF5
c6c4d7bb
BW		 935
936static struct pata_platform_info bfin_pata_platform_data = {
937 .ioport_shift = 1,
64e5c512 938 .irq_flags = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
c6c4d7bb
BW		 939};
940
941static struct resource bfin_pata_resources[] = {
942 {
943 .start = 0x20314020,
944 .end = 0x2031403F,
945 .flags = IORESOURCE_MEM,
946 },
947 {
948 .start = 0x2031401C,
949 .end = 0x2031401F,
950 .flags = IORESOURCE_MEM,
951 },
952 {
953 .start = PATA_INT,
954 .end = PATA_INT,
955 .flags = IORESOURCE_IRQ,
956 },
957};
958
959static struct platform_device bfin_pata_device = {
960 .name = "pata_platform",
961 .id = -1,
962 .num_resources = ARRAY_SIZE(bfin_pata_resources),
963 .resource = bfin_pata_resources,
964 .dev = {
965 .platform_data = &bfin_pata_platform_data,
966 }
967};
968#endif
969
14b03204
MH		 970static const unsigned int cclk_vlev_datasheet[] =
971{
972 VRPAIR(VLEV_085, 250000000),
973 VRPAIR(VLEV_090, 376000000),
974 VRPAIR(VLEV_095, 426000000),
975 VRPAIR(VLEV_100, 426000000),
976 VRPAIR(VLEV_105, 476000000),
977 VRPAIR(VLEV_110, 476000000),
978 VRPAIR(VLEV_115, 476000000),
979 VRPAIR(VLEV_120, 500000000),
980 VRPAIR(VLEV_125, 533000000),
981 VRPAIR(VLEV_130, 600000000),
982};
983
984static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
985 .tuple_tab = cclk_vlev_datasheet,
986 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
987 .vr_settling_time = 25 /* us */,
988};
989
990static struct platform_device bfin_dpmc = {
991 .name = "bfin dpmc",
992 .dev = {
993 .platform_data = &bfin_dmpc_vreg_data,
994 },
995};
996
1394f032 997static struct platform_device *stamp_devices[] __initdata = {
14b03204
MH		 998
999 &bfin_dpmc,
1000
1394f032
BW		 1001#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
1002 &bfin_pcmcia_cf_device,
1003#endif
1004
1005#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1006 &rtc_device,
1007#endif
1008
1009#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
1010 &sl811_hcd_device,
1011#endif
1012
1013#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
1014 &isp1362_hcd_device,
1015#endif
1016
1017#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
1018 &smc91x_device,
1019#endif
1020
f40d24d9
AL		 1021#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
1022 &dm9000_device,
1023#endif
1024
561cc18b
MH		 1025#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE)
1026 &ax88180_device,
1027#endif
1028
1394f032
BW		 1029#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1030 &bfin_mac_device,
1031#endif
1032
1033#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
1034 &net2272_bfin_device,
1035#endif
1036
1037#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb 1038 &bfin_spi0_device,
1394f032
BW		 1039#endif
1040
1041#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1042 &bfin_fb_device,
1043#endif
1044
2043f3f7
MH		 1045#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
1046 &bfin_lq035q1_device,
1047#endif
1048
c6c4d7bb
BW		 1049#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
1050 &bfin_fb_adv7393_device,
1051#endif
1052
1394f032
BW		 1053#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1054 &bfin_uart_device,
1055#endif
1056
5be36d22
GY		 1057#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
1058 &bfin_sir_device,
1059#endif
1060
1394f032
BW		 1061#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1062 &i2c_bfin_twi_device,
1063#endif
1064
1065#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1066 &bfin_sport0_uart_device,
1067 &bfin_sport1_uart_device,
1068#endif
c6c4d7bb
BW		 1069
1070#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
1071 &bfin_pata_device,
1072#endif
2463ef22
MH		 1073
1074#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1075 &bfin_device_gpiokeys,
1076#endif
cad2ab65
MF		 1077
1078 &bfin_gpios_device,
793dc27b 1079
fc68911e
MF		 1080#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
1081 &bfin_async_nand_device,
1082#endif
1083
793dc27b 1084#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 1085 &stamp_flash_device,
793dc27b 1086#endif
1394f032
BW		 1087};
1088
1089static int __init stamp_init(void)
1090{
b85d858b 1091 printk(KERN_INFO "%s(): registering device resources\n", __func__);
81d9c7f2
BW		 1092
1093#ifdef CONFIG_I2C_BOARDINFO
1094 i2c_register_board_info(0, bfin_i2c_board_info,
1095 ARRAY_SIZE(bfin_i2c_board_info));
1096#endif
1097
fc68911e 1098 bfin_plat_nand_init();
1394f032 1099 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
5bda2723 1100 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb
BW		 1101
1102#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
1103 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
1104#endif
81d9c7f2 1105
1394f032
BW		 1106 return 0;
1107}
1108
1109arch_initcall(stamp_init);
c6c4d7bb
BW		 1110
1111void native_machine_restart(char *cmd)
1112{
1113 /* workaround reboot hang when booting from SPI */
1114 if ((bfin_read_SYSCR() & 0x7) == 0x3)
1115 bfin_gpio_reset_spi0_ssel1();
1116}
137b1529
MF		 1117
1118/*
1119 * Currently the MAC address is saved in Flash by U-Boot
1120 */
1121#define FLASH_MAC 0x203f0000
9862cc52 1122void bfin_get_ether_addr(char *addr)
137b1529
MF		 1123{
1124 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
1125 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
1126}
9862cc52 1127EXPORT_SYMBOL(bfin_get_ether_addr);
Linux kernel - Deliverables
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