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Blackfin: net2272: move pin setup to boards files
[deliverable/linux.git] / arch / blackfin / mach-bf537 / boards / stamp.c
CommitLineData
1394f032 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
1394f032 5 *
96f1050d 6 * Licensed under the GPL-2 or later.
1394f032
BW		 7 */
8
9#include <linux/device.h>
fc68911e 10#include <linux/kernel.h>
1394f032 11#include <linux/platform_device.h>
6e364755 12#include <linux/io.h>
1394f032 13#include <linux/mtd/mtd.h>
fc68911e 14#include <linux/mtd/nand.h>
1394f032 15#include <linux/mtd/partitions.h>
fc68911e 16#include <linux/mtd/plat-ram.h>
de8c43f2 17#include <linux/mtd/physmap.h>
1394f032
BW		 18#include <linux/spi/spi.h>
19#include <linux/spi/flash.h>
20#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5 21#include <linux/usb/isp1362.h>
1394f032 22#endif
7a9cc489
SZ		 23#include <linux/i2c.h>
24#include <linux/i2c/adp5588.h>
0531c467 25#include <linux/etherdevice.h>
0a87e3e9 26#include <linux/ata_platform.h>
1394f032
BW		 27#include <linux/irq.h>
28#include <linux/interrupt.h>
27f5d75a 29#include <linux/usb/sl811.h>
f79ea4cb 30#include <linux/spi/mmc_spi.h>
78756c62
MH		 31#include <linux/leds.h>
32#include <linux/input.h>
c6c4d7bb 33#include <asm/dma.h>
1f83b8f1 34#include <asm/bfin5xx_spi.h>
c6c4d7bb 35#include <asm/reboot.h>
5d448dd5 36#include <asm/portmux.h>
14b03204 37#include <asm/dpmc.h>
6f53dbbb 38#include <asm/bfin_sport.h>
1b04cbea
SZ		 39#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
40#include <linux/regulator/fixed.h>
f8e6dbff 41#endif
1b04cbea 42#include <linux/regulator/machine.h>
f32792d0
SZ		 43#include <linux/regulator/consumer.h>
44#include <linux/regulator/userspace-consumer.h>
1394f032
BW		 45
46/*
47 * Name the Board for the /proc/cpuinfo
48 */
fe85cad2 49const char bfin_board_name[] = "ADI BF537-STAMP";
1394f032
BW		 50
51/*
52 * Driver needs to know address, irq and flag pin.
53 */
54
1394f032 55#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 56#include <linux/usb/isp1760.h>
57static struct resource bfin_isp1760_resources[] = {
1394f032 58 [0] = {
3f375690
MH		 59 .start = 0x203C0000,
60 .end = 0x203C0000 + 0x000fffff,
1394f032
BW		 61 .flags = IORESOURCE_MEM,
62 },
63 [1] = {
3f375690
MH		 64 .start = IRQ_PF7,
65 .end = IRQ_PF7,
6a6be3d1 66 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
1394f032
BW		 67 },
68};
69
3f375690
MH		 70static struct isp1760_platform_data isp1760_priv = {
71 .is_isp1761 = 0,
3f375690
MH		 72 .bus_width_16 = 1,
73 .port1_otg = 0,
74 .analog_oc = 0,
75 .dack_polarity_high = 0,
76 .dreq_polarity_high = 0,
1394f032
BW		 77};
78
3f375690 79static struct platform_device bfin_isp1760_device = {
c6feb768 80 .name = "isp1760",
3f375690
MH		 81 .id = 0,
82 .dev = {
83 .platform_data = &isp1760_priv,
84 },
85 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
86 .resource = bfin_isp1760_resources,
1394f032 87};
1394f032
BW		 88#endif
89
2463ef22 90#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
2463ef22
MH		 91#include <linux/gpio_keys.h>
92
93static struct gpio_keys_button bfin_gpio_keys_table[] = {
94 {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
95 {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
96 {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
97 {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
98};
99
100static struct gpio_keys_platform_data bfin_gpio_keys_data = {
101 .buttons = bfin_gpio_keys_table,
102 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
103};
104
105static struct platform_device bfin_device_gpiokeys = {
106 .name = "gpio-keys",
107 .dev = {
108 .platform_data = &bfin_gpio_keys_data,
109 },
110};
111#endif
112
1394f032
BW		 113#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
114static struct resource bfin_pcmcia_cf_resources[] = {
115 {
116 .start = 0x20310000, /* IO PORT */
117 .end = 0x20312000,
118 .flags = IORESOURCE_MEM,
1f83b8f1 119 }, {
d2d50aa9 120 .start = 0x20311000, /* Attribute Memory */
1394f032
BW		 121 .end = 0x20311FFF,
122 .flags = IORESOURCE_MEM,
1f83b8f1 123 }, {
1394f032
BW		 124 .start = IRQ_PF4,
125 .end = IRQ_PF4,
126 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
1f83b8f1 127 }, {
1394f032
BW		 128 .start = 6, /* Card Detect PF6 */
129 .end = 6,
130 .flags = IORESOURCE_IRQ,
131 },
132};
133
134static struct platform_device bfin_pcmcia_cf_device = {
135 .name = "bfin_cf_pcmcia",
136 .id = -1,
137 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
138 .resource = bfin_pcmcia_cf_resources,
139};
140#endif
141
142#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
143static struct platform_device rtc_device = {
144 .name = "rtc-bfin",
145 .id = -1,
146};
147#endif
148
149#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 150#include <linux/smc91x.h>
151
152static struct smc91x_platdata smc91x_info = {
153 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
154 .leda = RPC_LED_100_10,
155 .ledb = RPC_LED_TX_RX,
156};
157
1394f032
BW		 158static struct resource smc91x_resources[] = {
159 {
160 .name = "smc91x-regs",
161 .start = 0x20300300,
162 .end = 0x20300300 + 16,
163 .flags = IORESOURCE_MEM,
1f83b8f1 164 }, {
1394f032
BW		 165
166 .start = IRQ_PF7,
167 .end = IRQ_PF7,
168 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
169 },
170};
171static struct platform_device smc91x_device = {
172 .name = "smc91x",
173 .id = 0,
174 .num_resources = ARRAY_SIZE(smc91x_resources),
175 .resource = smc91x_resources,
61f09b5a
MH		 176 .dev = {
177 .platform_data = &smc91x_info,
178 },
1394f032
BW		 179};
180#endif
181
f40d24d9
AL		 182#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
183static struct resource dm9000_resources[] = {
184 [0] = {
185 .start = 0x203FB800,
b3dec4a4 186 .end = 0x203FB800 + 1,
f40d24d9
AL		 187 .flags = IORESOURCE_MEM,
188 },
189 [1] = {
b3dec4a4
BS		 190 .start = 0x203FB804,
191 .end = 0x203FB804 + 1,
192 .flags = IORESOURCE_MEM,
193 },
194 [2] = {
f40d24d9
AL		 195 .start = IRQ_PF9,
196 .end = IRQ_PF9,
197 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
198 },
199};
200
201static struct platform_device dm9000_device = {
202 .name = "dm9000",
203 .id = -1,
204 .num_resources = ARRAY_SIZE(dm9000_resources),
205 .resource = dm9000_resources,
206};
207#endif
208
1394f032
BW		 209#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
210static struct resource sl811_hcd_resources[] = {
211 {
212 .start = 0x20340000,
213 .end = 0x20340000,
214 .flags = IORESOURCE_MEM,
1f83b8f1 215 }, {
1394f032
BW		 216 .start = 0x20340004,
217 .end = 0x20340004,
218 .flags = IORESOURCE_MEM,
1f83b8f1 219 }, {
01218654
MF		 220 .start = IRQ_PF4,
221 .end = IRQ_PF4,
1394f032
BW		 222 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
223 },
224};
225
226#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
227void sl811_port_power(struct device *dev, int is_on)
228{
c6c4d7bb 229 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
acbcd263 230 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
1394f032
BW		 231}
232#endif
233
234static struct sl811_platform_data sl811_priv = {
235 .potpg = 10,
236 .power = 250, /* == 500mA */
237#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
238 .port_power = &sl811_port_power,
239#endif
240};
241
242static struct platform_device sl811_hcd_device = {
243 .name = "sl811-hcd",
244 .id = 0,
245 .dev = {
246 .platform_data = &sl811_priv,
247 },
248 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
249 .resource = sl811_hcd_resources,
250};
251#endif
252
253#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
254static struct resource isp1362_hcd_resources[] = {
255 {
256 .start = 0x20360000,
257 .end = 0x20360000,
258 .flags = IORESOURCE_MEM,
1f83b8f1 259 }, {
1394f032
BW		 260 .start = 0x20360004,
261 .end = 0x20360004,
262 .flags = IORESOURCE_MEM,
1f83b8f1 263 }, {
21b03cfe
MF		 264 .start = IRQ_PF3,
265 .end = IRQ_PF3,
9e75894c 266 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
1394f032
BW		 267 },
268};
269
270static struct isp1362_platform_data isp1362_priv = {
271 .sel15Kres = 1,
272 .clknotstop = 0,
273 .oc_enable = 0,
274 .int_act_high = 0,
275 .int_edge_triggered = 0,
276 .remote_wakeup_connected = 0,
277 .no_power_switching = 1,
278 .power_switching_mode = 0,
279};
280
281static struct platform_device isp1362_hcd_device = {
282 .name = "isp1362-hcd",
283 .id = 0,
284 .dev = {
285 .platform_data = &isp1362_priv,
286 },
287 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
288 .resource = isp1362_hcd_resources,
289};
290#endif
291
706a01b1 292#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
a8b19886 293static unsigned short bfin_can_peripherals[] = {
706a01b1
BS		 294 P_CAN0_RX, P_CAN0_TX, 0
295};
296
297static struct resource bfin_can_resources[] = {
298 {
299 .start = 0xFFC02A00,
300 .end = 0xFFC02FFF,
301 .flags = IORESOURCE_MEM,
302 },
303 {
304 .start = IRQ_CAN_RX,
305 .end = IRQ_CAN_RX,
306 .flags = IORESOURCE_IRQ,
307 },
308 {
309 .start = IRQ_CAN_TX,
310 .end = IRQ_CAN_TX,
311 .flags = IORESOURCE_IRQ,
312 },
313 {
314 .start = IRQ_CAN_ERROR,
315 .end = IRQ_CAN_ERROR,
316 .flags = IORESOURCE_IRQ,
317 },
318};
319
320static struct platform_device bfin_can_device = {
321 .name = "bfin_can",
322 .num_resources = ARRAY_SIZE(bfin_can_resources),
323 .resource = bfin_can_resources,
324 .dev = {
325 .platform_data = &bfin_can_peripherals, /* Passed to driver */
326 },
327};
328#endif
329
1394f032 330#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
02460d08
SZ		 331#include <linux/bfin_mac.h>
332static const unsigned short bfin_mac_peripherals[] = P_MII0;
333
334static struct bfin_phydev_platform_data bfin_phydev_data[] = {
335 {
336 .addr = 1,
337 .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
338 },
339};
340
341static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
342 .phydev_number = 1,
343 .phydev_data = bfin_phydev_data,
344 .phy_mode = PHY_INTERFACE_MODE_MII,
345 .mac_peripherals = bfin_mac_peripherals,
346};
347
65319628
GY		 348static struct platform_device bfin_mii_bus = {
349 .name = "bfin_mii_bus",
02460d08
SZ		 350 .dev = {
351 .platform_data = &bfin_mii_bus_data,
352 }
65319628
GY		 353};
354
1394f032
BW		 355static struct platform_device bfin_mac_device = {
356 .name = "bfin_mac",
02460d08
SZ		 357 .dev = {
358 .platform_data = &bfin_mii_bus,
359 }
1394f032
BW		 360};
361#endif
362
363#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
364static struct resource net2272_bfin_resources[] = {
365 {
366 .start = 0x20300000,
367 .end = 0x20300000 + 0x100,
368 .flags = IORESOURCE_MEM,
9be8631b
MF		 369 }, {
370 .start = 1,
371 .flags = IORESOURCE_BUS,
1f83b8f1 372 }, {
1394f032
BW		 373 .start = IRQ_PF7,
374 .end = IRQ_PF7,
375 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
376 },
377};
378
379static struct platform_device net2272_bfin_device = {
380 .name = "net2272",
381 .id = -1,
382 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
383 .resource = net2272_bfin_resources,
384};
385#endif
386
fc68911e 387#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
fc68911e
MF		 388const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
389
390static struct mtd_partition bfin_plat_nand_partitions[] = {
391 {
aa582977 392 .name = "linux kernel(nand)",
fc68911e
MF		 393 .size = 0x400000,
394 .offset = 0,
395 }, {
aa582977 396 .name = "file system(nand)",
fc68911e
MF		 397 .size = MTDPART_SIZ_FULL,
398 .offset = MTDPART_OFS_APPEND,
399 },
400};
fc68911e
MF		 401
402#define BFIN_NAND_PLAT_CLE 2
403#define BFIN_NAND_PLAT_ALE 1
404static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
405{
406 struct nand_chip *this = mtd->priv;
407
408 if (cmd == NAND_CMD_NONE)
409 return;
410
411 if (ctrl & NAND_CLE)
412 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
413 else
414 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
415}
416
417#define BFIN_NAND_PLAT_READY GPIO_PF3
418static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
419{
420 return gpio_get_value(BFIN_NAND_PLAT_READY);
421}
422
423static struct platform_nand_data bfin_plat_nand_data = {
424 .chip = {
ef56609f 425 .nr_chips = 1,
fc68911e 426 .chip_delay = 30,
fc68911e
MF		 427 .part_probe_types = part_probes,
428 .partitions = bfin_plat_nand_partitions,
429 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
fc68911e
MF		 430 },
431 .ctrl = {
432 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
433 .dev_ready = bfin_plat_nand_dev_ready,
434 },
435};
436
437#define MAX(x, y) (x > y ? x : y)
438static struct resource bfin_plat_nand_resources = {
439 .start = 0x20212000,
440 .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
67d9963b 441 .flags = IORESOURCE_MEM,
fc68911e
MF		 442};
443
444static struct platform_device bfin_async_nand_device = {
445 .name = "gen_nand",
446 .id = -1,
447 .num_resources = 1,
448 .resource = &bfin_plat_nand_resources,
449 .dev = {
450 .platform_data = &bfin_plat_nand_data,
451 },
452};
453
454static void bfin_plat_nand_init(void)
455{
456 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
457}
458#else
459static void bfin_plat_nand_init(void) {}
460#endif
461
793dc27b 462#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2
MF		 463static struct mtd_partition stamp_partitions[] = {
464 {
aa582977 465 .name = "bootloader(nor)",
edf05641 466 .size = 0x40000,
de8c43f2
MF		 467 .offset = 0,
468 }, {
aa582977 469 .name = "linux kernel(nor)",
6ecb5b6d 470 .size = 0x180000,
de8c43f2
MF		 471 .offset = MTDPART_OFS_APPEND,
472 }, {
aa582977 473 .name = "file system(nor)",
6ecb5b6d 474 .size = 0x400000 - 0x40000 - 0x180000 - 0x10000,
de8c43f2
MF		 475 .offset = MTDPART_OFS_APPEND,
476 }, {
aa582977 477 .name = "MAC Address(nor)",
de8c43f2
MF		 478 .size = MTDPART_SIZ_FULL,
479 .offset = 0x3F0000,
480 .mask_flags = MTD_WRITEABLE,
481 }
482};
483
484static struct physmap_flash_data stamp_flash_data = {
485 .width = 2,
486 .parts = stamp_partitions,
487 .nr_parts = ARRAY_SIZE(stamp_partitions),
38e7673f
BS		 488#ifdef CONFIG_ROMKERNEL
489 .probe_type = "map_rom",
490#endif
de8c43f2
MF		 491};
492
493static struct resource stamp_flash_resource = {
494 .start = 0x20000000,
495 .end = 0x203fffff,
496 .flags = IORESOURCE_MEM,
497};
498
499static struct platform_device stamp_flash_device = {
500 .name = "physmap-flash",
501 .id = 0,
502 .dev = {
503 .platform_data = &stamp_flash_data,
504 },
505 .num_resources = 1,
506 .resource = &stamp_flash_resource,
507};
793dc27b 508#endif
de8c43f2 509
1394f032
BW		 510#if defined(CONFIG_MTD_M25P80) \
511 || defined(CONFIG_MTD_M25P80_MODULE)
512static struct mtd_partition bfin_spi_flash_partitions[] = {
513 {
aa582977 514 .name = "bootloader(spi)",
edf05641 515 .size = 0x00040000,
1394f032
BW		 516 .offset = 0,
517 .mask_flags = MTD_CAP_ROM
1f83b8f1 518 }, {
aa582977 519 .name = "linux kernel(spi)",
6ecb5b6d 520 .size = 0x180000,
edf05641 521 .offset = MTDPART_OFS_APPEND,
1f83b8f1 522 }, {
aa582977 523 .name = "file system(spi)",
edf05641
MF		 524 .size = MTDPART_SIZ_FULL,
525 .offset = MTDPART_OFS_APPEND,
1394f032
BW		 526 }
527};
528
529static struct flash_platform_data bfin_spi_flash_data = {
530 .name = "m25p80",
531 .parts = bfin_spi_flash_partitions,
532 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
88a8078b 533 /* .type = "m25p64", */
1394f032
BW		 534};
535
536/* SPI flash chip (m25p64) */
537static struct bfin5xx_spi_chip spi_flash_chip_info = {
538 .enable_dma = 0, /* use dma transfer with this chip*/
539 .bits_per_word = 8,
540};
541#endif
542
a261eec0
MF		 543#if defined(CONFIG_BFIN_SPI_ADC) \
544 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
1394f032
BW		 545/* SPI ADC chip */
546static struct bfin5xx_spi_chip spi_adc_chip_info = {
547 .enable_dma = 1, /* use dma transfer with this chip*/
548 .bits_per_word = 16,
549};
550#endif
551
d40bd71f
BS		 552#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
553 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
1394f032
BW		 554static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
555 .enable_dma = 0,
556 .bits_per_word = 16,
557};
558#endif
559
3b82790c
BS		 560#if defined(CONFIG_SND_BF5XX_SOC_AD193X) \
561 || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE)
d4b834c1
BS		 562static struct bfin5xx_spi_chip ad1938_spi_chip_info = {
563 .enable_dma = 0,
564 .bits_per_word = 8,
d4b834c1
BS		 565};
566#endif
567
a65912ca
YL		 568#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) \
569 || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
570static struct bfin5xx_spi_chip adav801_spi_chip_info = {
571 .enable_dma = 0,
572 .bits_per_word = 8,
573};
574#endif
575
5b7c5775 576#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
427f277e
BS		 577#include <linux/input/ad714x.h>
578static struct bfin5xx_spi_chip ad7147_spi_chip_info = {
579 .enable_dma = 0,
580 .bits_per_word = 16,
581};
582
5b7c5775 583static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
427f277e
BS		 584 {
585 .start_stage = 0,
586 .end_stage = 7,
587 .max_coord = 128,
588 },
589};
590
5b7c5775 591static struct ad714x_button_plat ad7147_spi_button_plat[] = {
427f277e
BS		 592 {
593 .keycode = BTN_FORWARD,
594 .l_mask = 0,
595 .h_mask = 0x600,
596 },
597 {
598 .keycode = BTN_LEFT,
599 .l_mask = 0,
600 .h_mask = 0x500,
601 },
602 {
603 .keycode = BTN_MIDDLE,
604 .l_mask = 0,
605 .h_mask = 0x800,
606 },
607 {
608 .keycode = BTN_RIGHT,
609 .l_mask = 0x100,
610 .h_mask = 0x400,
611 },
612 {
613 .keycode = BTN_BACK,
614 .l_mask = 0x200,
615 .h_mask = 0x400,
616 },
617};
5b7c5775 618static struct ad714x_platform_data ad7147_spi_platform_data = {
427f277e
BS		 619 .slider_num = 1,
620 .button_num = 5,
5b7c5775
MF		 621 .slider = ad7147_spi_slider_plat,
622 .button = ad7147_spi_button_plat,
427f277e
BS		 623 .stage_cfg_reg = {
624 {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600},
625 {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650},
626 {0xFFFF, 0x1FFE, 0, 0x2626, 1650, 1650, 1650, 1650},
627 {0xFFFF, 0x1FFB, 0, 0x2626, 1650, 1650, 1650, 1650},
628 {0xFFFF, 0x1FEF, 0, 0x2626, 1650, 1650, 1650, 1650},
629 {0xFFFF, 0x1FBF, 0, 0x2626, 1650, 1650, 1650, 1650},
630 {0xFFFF, 0x1EFF, 0, 0x2626, 1650, 1650, 1650, 1650},
631 {0xFFFF, 0x1BFF, 0, 0x2626, 1600, 1600, 1600, 1600},
632 {0xFF7B, 0x3FFF, 0x506, 0x2626, 1100, 1100, 1150, 1150},
633 {0xFDFE, 0x3FFF, 0x606, 0x2626, 1100, 1100, 1150, 1150},
634 {0xFEBA, 0x1FFF, 0x1400, 0x2626, 1200, 1200, 1300, 1300},
635 {0xFFEF, 0x1FFF, 0x0, 0x2626, 1100, 1100, 1150, 1150},
636 },
637 .sys_cfg_reg = {0x2B2, 0x0, 0x3233, 0x819, 0x832, 0xCFF, 0xCFF, 0x0},
638};
639#endif
640
5b7c5775 641#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
427f277e 642#include <linux/input/ad714x.h>
5b7c5775 643static struct ad714x_button_plat ad7142_i2c_button_plat[] = {
427f277e
BS		 644 {
645 .keycode = BTN_1,
646 .l_mask = 0,
647 .h_mask = 0x1,
648 },
649 {
650 .keycode = BTN_2,
651 .l_mask = 0,
652 .h_mask = 0x2,
653 },
654 {
655 .keycode = BTN_3,
656 .l_mask = 0,
657 .h_mask = 0x4,
658 },
659 {
660 .keycode = BTN_4,
661 .l_mask = 0x0,
662 .h_mask = 0x8,
663 },
664};
5b7c5775 665static struct ad714x_platform_data ad7142_i2c_platform_data = {
427f277e 666 .button_num = 4,
5b7c5775 667 .button = ad7142_i2c_button_plat,
427f277e
BS		 668 .stage_cfg_reg = {
669 /* fixme: figure out right setting for all comoponent according
670 * to hardware feature of EVAL-AD7142EB board */
671 {0xE7FF, 0x3FFF, 0x0005, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
672 {0xFDBF, 0x3FFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
673 {0xFFFF, 0x2DFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
674 {0xFFFF, 0x37BF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
675 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
676 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
677 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
678 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
679 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
680 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
681 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
682 {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
683 },
684 .sys_cfg_reg = {0x0B2, 0x0, 0x690, 0x664, 0x290F, 0xF, 0xF, 0x0},
685};
686#endif
687
f5f9531c
GY		 688#if defined(CONFIG_AD2S90) || defined(CONFIG_AD2S90_MODULE)
689static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
690 .enable_dma = 0,
691 .bits_per_word = 16,
692};
693#endif
694
df6a949b 695#if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE)
a8b19886 696static unsigned short ad2s120x_platform_data[] = {
df6a949b
GY		 697 /* used as SAMPLE and RDVEL */
698 GPIO_PF5, GPIO_PF6, 0
699};
700
701static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = {
702 .enable_dma = 0,
703 .bits_per_word = 16,
704};
705#endif
706
848c51cc 707#if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE)
a8b19886 708static unsigned short ad2s1210_platform_data[] = {
848c51cc
GY		 709 /* use as SAMPLE, A0, A1 */
710 GPIO_PF7, GPIO_PF8, GPIO_PF9,
711# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT)
712 /* the RES0 and RES1 pins */
713 GPIO_PF4, GPIO_PF5,
714# endif
715 0,
716};
717
718static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = {
719 .enable_dma = 0,
720 .bits_per_word = 8,
721};
722#endif
723
0891baef
MH		 724#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE)
725static struct bfin5xx_spi_chip ad7314_spi_chip_info = {
726 .enable_dma = 0,
727 .bits_per_word = 16,
728};
729#endif
730
731#if defined(CONFIG_AD7816) || defined(CONFIG_AD7816_MODULE)
732static unsigned short ad7816_platform_data[] = {
733 GPIO_PF4, /* rdwr_pin */
734 GPIO_PF5, /* convert_pin */
735 GPIO_PF7, /* busy_pin */
736 0,
737};
738
739static struct bfin5xx_spi_chip ad7816_spi_chip_info = {
740 .enable_dma = 0,
741 .bits_per_word = 8,
742};
743#endif
744
745#if defined(CONFIG_ADT7310) || defined(CONFIG_ADT7310_MODULE)
746static unsigned long adt7310_platform_data[3] = {
747/* INT bound temperature alarm event. line 1 */
748 IRQ_PG4, IRQF_TRIGGER_LOW,
749/* CT bound temperature alarm event irq_flags. line 0 */
750 IRQF_TRIGGER_LOW,
751};
752
753static struct bfin5xx_spi_chip adt7310_spi_chip_info = {
754 .enable_dma = 0,
755 .bits_per_word = 8,
756};
757#endif
758
759#if defined(CONFIG_AD7298) || defined(CONFIG_AD7298_MODULE)
760static unsigned short ad7298_platform_data[] = {
761 GPIO_PF7, /* busy_pin */
762 0,
763};
764
765static struct bfin5xx_spi_chip ad7298_spi_chip_info = {
766 .enable_dma = 0,
767 .bits_per_word = 16,
768};
769#endif
770
771#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE)
772static unsigned long adt7316_spi_data[2] = {
773 IRQF_TRIGGER_LOW, /* interrupt flags */
774 GPIO_PF7, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
775};
776
777static struct bfin5xx_spi_chip adt7316_spi_chip_info = {
778 .enable_dma = 0,
779 .bits_per_word = 8,
780};
781#endif
782
f79ea4cb
YL		 783#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
784#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
785
786static int bfin_mmc_spi_init(struct device *dev,
787 irqreturn_t (*detect_int)(int, void *), void *data)
788{
789 return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
790 IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
791}
792
793static void bfin_mmc_spi_exit(struct device *dev, void *data)
794{
795 free_irq(MMC_SPI_CARD_DETECT_INT, data);
796}
797
798static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
799 .init = bfin_mmc_spi_init,
800 .exit = bfin_mmc_spi_exit,
801 .detect_delay = 100, /* msecs */
802};
803
804static struct bfin5xx_spi_chip mmc_spi_chip_info = {
805 .enable_dma = 0,
806 .bits_per_word = 8,
e68d1ebc 807 .pio_interrupt = 0,
f79ea4cb
YL		 808};
809#endif
810
1394f032 811#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
46aa04f9 812#include <linux/spi/ad7877.h>
1394f032 813static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
1394f032
BW		 814 .enable_dma = 0,
815 .bits_per_word = 16,
816};
817
818static const struct ad7877_platform_data bfin_ad7877_ts_info = {
819 .model = 7877,
820 .vref_delay_usecs = 50, /* internal, no capacitor */
821 .x_plate_ohms = 419,
822 .y_plate_ohms = 486,
823 .pressure_max = 1000,
824 .pressure_min = 0,
6ba255f4
MH		 825 .stopacq_polarity = 1,
826 .first_conversion_delay = 3,
827 .acquisition_time = 1,
828 .averaging = 1,
829 .pen_down_acc_interval = 1,
1394f032
BW		 830};
831#endif
832
46aa04f9
MH		 833#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
834#include <linux/spi/ad7879.h>
46aa04f9
MH		 835static const struct ad7879_platform_data bfin_ad7879_ts_info = {
836 .model = 7879, /* Model = AD7879 */
837 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
838 .pressure_max = 10000,
839 .pressure_min = 0,
6ba255f4
MH		 840 .first_conversion_delay = 3, /* wait 512us before do a first conversion */
841 .acquisition_time = 1, /* 4us acquisition time per sample */
46aa04f9 842 .median = 2, /* do 8 measurements */
6ba255f4
MH		 843 .averaging = 1, /* take the average of 4 middle samples */
844 .pen_down_acc_interval = 255, /* 9.4 ms */
244d3423
MH		 845 .gpio_export = 1, /* Export GPIO to gpiolib */
846 .gpio_base = -1, /* Dynamic allocation */
46aa04f9
MH		 847};
848#endif
849
ffc4d8bc 850#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
57af8edf 851#include <linux/input/adxl34x.h>
ffc4d8bc
MH		 852static const struct adxl34x_platform_data adxl34x_info = {
853 .x_axis_offset = 0,
854 .y_axis_offset = 0,
855 .z_axis_offset = 0,
856 .tap_threshold = 0x31,
857 .tap_duration = 0x10,
858 .tap_latency = 0x60,
859 .tap_window = 0xF0,
860 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
861 .act_axis_control = 0xFF,
862 .activity_threshold = 5,
863 .inactivity_threshold = 3,
864 .inactivity_time = 4,
865 .free_fall_threshold = 0x7,
866 .free_fall_time = 0x20,
867 .data_rate = 0x8,
868 .data_range = ADXL_FULL_RES,
869
870 .ev_type = EV_ABS,
871 .ev_code_x = ABS_X, /* EV_REL */
872 .ev_code_y = ABS_Y, /* EV_REL */
873 .ev_code_z = ABS_Z, /* EV_REL */
874
57af8edf 875 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
ffc4d8bc
MH		 876
877/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
878/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
879 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
880 .fifo_mode = ADXL_FIFO_STREAM,
6ba255f4
MH		 881 .orientation_enable = ADXL_EN_ORIENTATION_3D,
882 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
883 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
884 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
885 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
ffc4d8bc
MH		 886};
887#endif
888
f5150155
MH		 889#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
890static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
891 .enable_dma = 0,
892 .bits_per_word = 16,
893};
894#endif
895
6e668936
MH		 896#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
897static struct bfin5xx_spi_chip spidev_chip_info = {
898 .enable_dma = 0,
899 .bits_per_word = 8,
900};
901#endif
902
2043f3f7
MH		 903#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
904static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
905 .enable_dma = 0,
906 .bits_per_word = 8,
907};
908#endif
909
85a192e9
MH		 910#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
911static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
912 .enable_dma = 1,
913 .bits_per_word = 8,
85a192e9
MH		 914};
915#endif
916
efaf7cd9
MH		 917#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
918static struct bfin5xx_spi_chip adf7021_spi_chip_info = {
919 .bits_per_word = 16,
efaf7cd9
MH		 920};
921
922#include <linux/spi/adf702x.h>
923#define TXREG 0x0160A470
924static const u32 adf7021_regs[] = {
925 0x09608FA0,
926 0x00575011,
927 0x00A7F092,
928 0x2B141563,
929 0x81F29E94,
930 0x00003155,
931 0x050A4F66,
932 0x00000007,
933 0x00000008,
934 0x000231E9,
935 0x3296354A,
936 0x891A2B3B,
937 0x00000D9C,
938 0x0000000D,
939 0x0000000E,
940 0x0000000F,
941};
942
943static struct adf702x_platform_data adf7021_platform_data = {
944 .regs_base = (void *)SPORT1_TCR1,
945 .dma_ch_rx = CH_SPORT1_RX,
946 .dma_ch_tx = CH_SPORT1_TX,
947 .irq_sport_err = IRQ_SPORT1_ERROR,
948 .gpio_int_rfs = GPIO_PF8,
949 .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI,
950 P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0},
951 .adf702x_model = MODEL_ADF7021,
952 .adf702x_regs = adf7021_regs,
953 .tx_reg = TXREG,
954};
0531c467
MF		 955static inline void adf702x_mac_init(void)
956{
957 random_ether_addr(adf7021_platform_data.mac_addr);
958}
959#else
960static inline void adf702x_mac_init(void) {}
efaf7cd9
MH		 961#endif
962
fe5b25c0
MH		 963#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
964#include <linux/spi/ads7846.h>
965static struct bfin5xx_spi_chip ad7873_spi_chip_info = {
966 .bits_per_word = 8,
967};
968
969static int ads7873_get_pendown_state(void)
970{
971 return gpio_get_value(GPIO_PF6);
972}
973
974static struct ads7846_platform_data __initdata ad7873_pdata = {
975 .model = 7873, /* AD7873 */
976 .x_max = 0xfff,
977 .y_max = 0xfff,
978 .x_plate_ohms = 620,
979 .debounce_max = 1,
980 .debounce_rep = 0,
981 .debounce_tol = (~0),
982 .get_pendown_state = ads7873_get_pendown_state,
983};
984#endif
985
8e9d5c7d
MH		 986#if defined(CONFIG_MTD_DATAFLASH) \
987 || defined(CONFIG_MTD_DATAFLASH_MODULE)
ceac2651
MH		 988
989static struct mtd_partition bfin_spi_dataflash_partitions[] = {
990 {
991 .name = "bootloader(spi)",
992 .size = 0x00040000,
993 .offset = 0,
994 .mask_flags = MTD_CAP_ROM
995 }, {
996 .name = "linux kernel(spi)",
6ecb5b6d 997 .size = 0x180000,
ceac2651
MH		 998 .offset = MTDPART_OFS_APPEND,
999 }, {
1000 .name = "file system(spi)",
1001 .size = MTDPART_SIZ_FULL,
1002 .offset = MTDPART_OFS_APPEND,
1003 }
1004};
1005
1006static struct flash_platform_data bfin_spi_dataflash_data = {
1007 .name = "SPI Dataflash",
1008 .parts = bfin_spi_dataflash_partitions,
1009 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
1010};
1011
8e9d5c7d
MH		 1012/* DataFlash chip */
1013static struct bfin5xx_spi_chip data_flash_chip_info = {
1014 .enable_dma = 0, /* use dma transfer with this chip*/
1015 .bits_per_word = 8,
1016};
1017#endif
1018
57af8edf
MH		 1019#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1020static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
1021 .enable_dma = 0, /* use dma transfer with this chip*/
1022 .bits_per_word = 8,
1023};
1024#endif
1025
0891baef
MH		 1026#if defined(CONFIG_AD7476) || defined(CONFIG_AD7476_MODULE)
1027static struct bfin5xx_spi_chip spi_ad7476_chip_info = {
1028 .enable_dma = 0, /* use dma transfer with this chip*/
1029 .bits_per_word = 8,
1030};
1031#endif
1032
1394f032
BW		 1033static struct spi_board_info bfin_spi_board_info[] __initdata = {
1034#if defined(CONFIG_MTD_M25P80) \
1035 || defined(CONFIG_MTD_M25P80_MODULE)
1036 {
1037 /* the modalias must be the same as spi device driver name */
1038 .modalias = "m25p80", /* Name of spi_driver for this device */
1039 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 1040 .bus_num = 0, /* Framework bus number */
1394f032
BW		 1041 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
1042 .platform_data = &bfin_spi_flash_data,
1043 .controller_data = &spi_flash_chip_info,
1044 .mode = SPI_MODE_3,
1045 },
1046#endif
8e9d5c7d
MH		 1047#if defined(CONFIG_MTD_DATAFLASH) \
1048 || defined(CONFIG_MTD_DATAFLASH_MODULE)
1049 { /* DataFlash chip */
1050 .modalias = "mtd_dataflash",
ceac2651 1051 .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
8e9d5c7d
MH		 1052 .bus_num = 0, /* Framework bus number */
1053 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
ceac2651 1054 .platform_data = &bfin_spi_dataflash_data,
8e9d5c7d
MH		 1055 .controller_data = &data_flash_chip_info,
1056 .mode = SPI_MODE_3,
1057 },
1058#endif
a261eec0
MF		 1059#if defined(CONFIG_BFIN_SPI_ADC) \
1060 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
1394f032
BW		 1061 {
1062 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
1063 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 1064 .bus_num = 0, /* Framework bus number */
1394f032
BW		 1065 .chip_select = 1, /* Framework chip select. */
1066 .platform_data = NULL, /* No spi_driver specific config */
1067 .controller_data = &spi_adc_chip_info,
1068 },
1069#endif
1070
d40bd71f
BS		 1071#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
1072 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
1394f032 1073 {
d40bd71f 1074 .modalias = "ad183x",
1394f032 1075 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 1076 .bus_num = 0,
7ba80063 1077 .chip_select = 4,
d40bd71f 1078 .platform_data = "ad1836", /* only includes chip name for the moment */
1394f032 1079 .controller_data = &ad1836_spi_chip_info,
8312440e 1080 .mode = SPI_MODE_3,
1394f032
BW		 1081 },
1082#endif
d4b834c1 1083
3b82790c 1084#if defined(CONFIG_SND_BF5XX_SOC_AD193X) || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE)
d4b834c1 1085 {
3b82790c 1086 .modalias = "ad193x",
d4b834c1
BS		 1087 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1088 .bus_num = 0,
08a54bff 1089 .chip_select = 5,
d4b834c1
BS		 1090 .controller_data = &ad1938_spi_chip_info,
1091 .mode = SPI_MODE_3,
1092 },
1093#endif
1094
a65912ca
YL		 1095#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
1096 {
1097 .modalias = "adav80x",
1098 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1099 .bus_num = 0,
1100 .chip_select = 1,
1101 .controller_data = &adav801_spi_chip_info,
1102 .mode = SPI_MODE_3,
1103 },
1104#endif
1105
5b7c5775 1106#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
427f277e
BS		 1107 {
1108 .modalias = "ad714x_captouch",
1109 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1110 .irq = IRQ_PF4,
1111 .bus_num = 0,
1112 .chip_select = 5,
1113 .mode = SPI_MODE_3,
5b7c5775 1114 .platform_data = &ad7147_spi_platform_data,
427f277e
BS		 1115 .controller_data = &ad7147_spi_chip_info,
1116 },
1117#endif
1118
f5f9531c
GY		 1119#if defined(CONFIG_AD2S90) || defined(CONFIG_AD2S90_MODULE)
1120 {
1121 .modalias = "ad2s90",
1122 .bus_num = 0,
1123 .chip_select = 3, /* change it for your board */
6fbfa0c4 1124 .mode = SPI_MODE_3,
f5f9531c
GY		 1125 .platform_data = NULL,
1126 .controller_data = &ad2s90_spi_chip_info,
1127 },
1128#endif
1129
df6a949b
GY		 1130#if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE)
1131 {
1132 .modalias = "ad2s120x",
1133 .bus_num = 0,
1134 .chip_select = 4, /* CS, change it for your board */
1135 .platform_data = ad2s120x_platform_data,
1136 .controller_data = &ad2s120x_spi_chip_info,
1137 },
1138#endif
1139
848c51cc
GY		 1140#if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE)
1141 {
1142 .modalias = "ad2s1210",
1143 .max_speed_hz = 8192000,
1144 .bus_num = 0,
1145 .chip_select = 4, /* CS, change it for your board */
1146 .platform_data = ad2s1210_platform_data,
1147 .controller_data = &ad2s1210_spi_chip_info,
1148 },
1149#endif
1150
0891baef
MH		 1151#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE)
1152 {
1153 .modalias = "ad7314",
1154 .max_speed_hz = 1000000,
1155 .bus_num = 0,
1156 .chip_select = 4, /* CS, change it for your board */
1157 .controller_data = &ad7314_spi_chip_info,
1158 .mode = SPI_MODE_1,
1159 },
1160#endif
1161
1162#if defined(CONFIG_AD7816) || defined(CONFIG_AD7816_MODULE)
1163 {
1164 .modalias = "ad7818",
1165 .max_speed_hz = 1000000,
1166 .bus_num = 0,
1167 .chip_select = 4, /* CS, change it for your board */
1168 .platform_data = ad7816_platform_data,
1169 .controller_data = &ad7816_spi_chip_info,
1170 .mode = SPI_MODE_3,
1171 },
1172#endif
1173
1174#if defined(CONFIG_ADT7310) || defined(CONFIG_ADT7310_MODULE)
1175 {
1176 .modalias = "adt7310",
1177 .max_speed_hz = 1000000,
1178 .irq = IRQ_PG5, /* CT alarm event. Line 0 */
1179 .bus_num = 0,
1180 .chip_select = 4, /* CS, change it for your board */
1181 .platform_data = adt7310_platform_data,
1182 .controller_data = &adt7310_spi_chip_info,
1183 .mode = SPI_MODE_3,
1184 },
1185#endif
1186
1187#if defined(CONFIG_AD7298) || defined(CONFIG_AD7298_MODULE)
1188 {
1189 .modalias = "ad7298",
1190 .max_speed_hz = 1000000,
1191 .bus_num = 0,
1192 .chip_select = 4, /* CS, change it for your board */
1193 .platform_data = ad7298_platform_data,
1194 .controller_data = &ad7298_spi_chip_info,
1195 .mode = SPI_MODE_3,
1196 },
1197#endif
1198
1199#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE)
1200 {
1201 .modalias = "adt7316",
1202 .max_speed_hz = 1000000,
1203 .irq = IRQ_PG5, /* interrupt line */
1204 .bus_num = 0,
1205 .chip_select = 4, /* CS, change it for your board */
1206 .platform_data = adt7316_spi_data,
1207 .controller_data = &adt7316_spi_chip_info,
1208 .mode = SPI_MODE_3,
1209 },
1210#endif
1211
f79ea4cb
YL		 1212#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
1213 {
1214 .modalias = "mmc_spi",
1215 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
1216 .bus_num = 0,
1217 .chip_select = 4,
1218 .platform_data = &bfin_mmc_spi_pdata,
1219 .controller_data = &mmc_spi_chip_info,
1220 .mode = SPI_MODE_3,
1221 },
1222#endif
1394f032
BW		 1223#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1224 {
1225 .modalias = "ad7877",
1226 .platform_data = &bfin_ad7877_ts_info,
1227 .irq = IRQ_PF6,
1228 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
c7d48966 1229 .bus_num = 0,
1394f032
BW		 1230 .chip_select = 1,
1231 .controller_data = &spi_ad7877_chip_info,
1232 },
1233#endif
f5150155 1234#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
46aa04f9
MH		 1235 {
1236 .modalias = "ad7879",
1237 .platform_data = &bfin_ad7879_ts_info,
1238 .irq = IRQ_PF7,
1239 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1240 .bus_num = 0,
1241 .chip_select = 1,
1242 .controller_data = &spi_ad7879_chip_info,
1243 .mode = SPI_CPHA | SPI_CPOL,
1244 },
1245#endif
6e668936
MH		 1246#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1247 {
1248 .modalias = "spidev",
1249 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1250 .bus_num = 0,
1251 .chip_select = 1,
1252 .controller_data = &spidev_chip_info,
1253 },
1254#endif
2043f3f7
MH		 1255#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
1256 {
1257 .modalias = "bfin-lq035q1-spi",
1258 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
1259 .bus_num = 0,
46aa04f9 1260 .chip_select = 2,
2043f3f7
MH		 1261 .controller_data = &lq035q1_spi_chip_info,
1262 .mode = SPI_CPHA | SPI_CPOL,
1263 },
1264#endif
85a192e9
MH		 1265#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
1266 {
1267 .modalias = "enc28j60",
1268 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
1269 .irq = IRQ_PF6,
1270 .bus_num = 0,
f9f0e3b1 1271 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
85a192e9
MH		 1272 .controller_data = &enc28j60_spi_chip_info,
1273 .mode = SPI_MODE_0,
1274 },
1275#endif
57af8edf
MH		 1276#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1277 {
1278 .modalias = "adxl34x",
1279 .platform_data = &adxl34x_info,
1280 .irq = IRQ_PF6,
1281 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1282 .bus_num = 0,
1283 .chip_select = 2,
1284 .controller_data = &spi_adxl34x_chip_info,
1285 .mode = SPI_MODE_3,
1286 },
1287#endif
efaf7cd9
MH		 1288#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
1289 {
1290 .modalias = "adf702x",
1291 .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */
1292 .bus_num = 0,
f9f0e3b1 1293 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
efaf7cd9
MH		 1294 .controller_data = &adf7021_spi_chip_info,
1295 .platform_data = &adf7021_platform_data,
1296 .mode = SPI_MODE_0,
1297 },
1298#endif
fe5b25c0
MH		 1299#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
1300 {
1301 .modalias = "ads7846",
1302 .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */
1303 .bus_num = 0,
1304 .irq = IRQ_PF6,
1305 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
1306 .controller_data = &ad7873_spi_chip_info,
1307 .platform_data = &ad7873_pdata,
1308 .mode = SPI_MODE_0,
1309 },
1310#endif
0891baef
MH		 1311#if defined(CONFIG_AD7476) \
1312 || defined(CONFIG_AD7476_MODULE)
1313 {
1314 .modalias = "ad7476", /* Name of spi_driver for this device */
1315 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
1316 .bus_num = 0, /* Framework bus number */
1317 .chip_select = 1, /* Framework chip select. */
1318 .platform_data = NULL, /* No spi_driver specific config */
1319 .controller_data = &spi_ad7476_chip_info,
1320 .mode = SPI_MODE_3,
1321 },
1322#endif
1323#if defined(CONFIG_ADE7753) \
1324 || defined(CONFIG_ADE7753_MODULE)
1325 {
1326 .modalias = "ade7753",
1327 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1328 .bus_num = 0,
1329 .chip_select = 1, /* CS, change it for your board */
1330 .platform_data = NULL, /* No spi_driver specific config */
1331 .mode = SPI_MODE_1,
1332 },
1333#endif
1334#if defined(CONFIG_ADE7754) \
1335 || defined(CONFIG_ADE7754_MODULE)
1336 {
1337 .modalias = "ade7754",
1338 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1339 .bus_num = 0,
1340 .chip_select = 1, /* CS, change it for your board */
1341 .platform_data = NULL, /* No spi_driver specific config */
1342 .mode = SPI_MODE_1,
1343 },
1344#endif
1345#if defined(CONFIG_ADE7758) \
1346 || defined(CONFIG_ADE7758_MODULE)
1347 {
1348 .modalias = "ade7758",
1349 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1350 .bus_num = 0,
1351 .chip_select = 1, /* CS, change it for your board */
1352 .platform_data = NULL, /* No spi_driver specific config */
1353 .mode = SPI_MODE_1,
1354 },
1355#endif
1356#if defined(CONFIG_ADE7759) \
1357 || defined(CONFIG_ADE7759_MODULE)
1358 {
1359 .modalias = "ade7759",
1360 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1361 .bus_num = 0,
1362 .chip_select = 1, /* CS, change it for your board */
1363 .platform_data = NULL, /* No spi_driver specific config */
1364 .mode = SPI_MODE_1,
1365 },
1366#endif
1367#if defined(CONFIG_ADE7854_SPI) \
1368 || defined(CONFIG_ADE7854_SPI_MODULE)
1369 {
1370 .modalias = "ade7854",
1371 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1372 .bus_num = 0,
1373 .chip_select = 1, /* CS, change it for your board */
1374 .platform_data = NULL, /* No spi_driver specific config */
1375 .mode = SPI_MODE_3,
1376 },
1377#endif
1378#if defined(CONFIG_ADIS16060) \
1379 || defined(CONFIG_ADIS16060_MODULE)
1380 {
1381 .modalias = "adis16060_r",
1382 .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
1383 .bus_num = 0,
1384 .chip_select = MAX_CTRL_CS + 1, /* CS for read, change it for your board */
1385 .platform_data = NULL, /* No spi_driver specific config */
1386 .mode = SPI_MODE_0,
1387 },
1388 {
1389 .modalias = "adis16060_w",
1390 .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
1391 .bus_num = 0,
1392 .chip_select = 2, /* CS for write, change it for your board */
1393 .platform_data = NULL, /* No spi_driver specific config */
1394 .mode = SPI_MODE_1,
1395 },
1396#endif
1397#if defined(CONFIG_ADIS16130) \
1398 || defined(CONFIG_ADIS16130_MODULE)
1399 {
1400 .modalias = "adis16130",
1401 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1402 .bus_num = 0,
1403 .chip_select = 1, /* CS for read, change it for your board */
1404 .platform_data = NULL, /* No spi_driver specific config */
1405 .mode = SPI_MODE_3,
1406 },
1407#endif
1408#if defined(CONFIG_ADIS16201) \
1409 || defined(CONFIG_ADIS16201_MODULE)
1410 {
1411 .modalias = "adis16201",
1412 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1413 .bus_num = 0,
1414 .chip_select = 5, /* CS, change it for your board */
1415 .platform_data = NULL, /* No spi_driver specific config */
1416 .mode = SPI_MODE_3,
1417 .irq = IRQ_PF4,
1418 },
1419#endif
1420#if defined(CONFIG_ADIS16203) \
1421 || defined(CONFIG_ADIS16203_MODULE)
1422 {
1423 .modalias = "adis16203",
1424 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1425 .bus_num = 0,
1426 .chip_select = 5, /* CS, change it for your board */
1427 .platform_data = NULL, /* No spi_driver specific config */
1428 .mode = SPI_MODE_3,
1429 .irq = IRQ_PF4,
1430 },
1431#endif
1432#if defined(CONFIG_ADIS16204) \
1433 || defined(CONFIG_ADIS16204_MODULE)
1434 {
1435 .modalias = "adis16204",
1436 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1437 .bus_num = 0,
1438 .chip_select = 5, /* CS, change it for your board */
1439 .platform_data = NULL, /* No spi_driver specific config */
1440 .mode = SPI_MODE_3,
1441 .irq = IRQ_PF4,
1442 },
1443#endif
1444#if defined(CONFIG_ADIS16209) \
1445 || defined(CONFIG_ADIS16209_MODULE)
1446 {
1447 .modalias = "adis16209",
1448 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1449 .bus_num = 0,
1450 .chip_select = 5, /* CS, change it for your board */
1451 .platform_data = NULL, /* No spi_driver specific config */
1452 .mode = SPI_MODE_3,
1453 .irq = IRQ_PF4,
1454 },
1455#endif
1456#if defined(CONFIG_ADIS16220) \
1457 || defined(CONFIG_ADIS16220_MODULE)
1458 {
1459 .modalias = "adis16220",
1460 .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */
1461 .bus_num = 0,
1462 .chip_select = 5, /* CS, change it for your board */
1463 .platform_data = NULL, /* No spi_driver specific config */
1464 .mode = SPI_MODE_3,
1465 .irq = IRQ_PF4,
1466 },
1467#endif
1468#if defined(CONFIG_ADIS16240) \
1469 || defined(CONFIG_ADIS16240_MODULE)
1470 {
1471 .modalias = "adis16240",
1472 .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
1473 .bus_num = 0,
1474 .chip_select = 5, /* CS, change it for your board */
1475 .platform_data = NULL, /* No spi_driver specific config */
1476 .mode = SPI_MODE_3,
1477 .irq = IRQ_PF4,
1478 },
1479#endif
1480#if defined(CONFIG_ADIS16260) \
1481 || defined(CONFIG_ADIS16260_MODULE)
1482 {
1483 .modalias = "adis16260",
1484 .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
1485 .bus_num = 0,
1486 .chip_select = 5, /* CS, change it for your board */
1487 .platform_data = NULL, /* No spi_driver specific config */
1488 .mode = SPI_MODE_3,
1489 .irq = IRQ_PF4,
1490 },
1491#endif
1492#if defined(CONFIG_ADIS16261) \
1493 || defined(CONFIG_ADIS16261_MODULE)
1494 {
1495 .modalias = "adis16261",
1496 .max_speed_hz = 2500000, /* max spi clock (SCK) speed in HZ */
1497 .bus_num = 0,
1498 .chip_select = 1, /* CS, change it for your board */
1499 .platform_data = NULL, /* No spi_driver specific config */
1500 .mode = SPI_MODE_3,
1501 },
1502#endif
1503#if defined(CONFIG_ADIS16300) \
1504 || defined(CONFIG_ADIS16300_MODULE)
1505 {
1506 .modalias = "adis16300",
1507 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1508 .bus_num = 0,
1509 .chip_select = 5, /* CS, change it for your board */
1510 .platform_data = NULL, /* No spi_driver specific config */
1511 .mode = SPI_MODE_3,
1512 .irq = IRQ_PF4,
1513 },
1514#endif
1515#if defined(CONFIG_ADIS16350) \
1516 || defined(CONFIG_ADIS16350_MODULE)
1517 {
1518 .modalias = "adis16364",
1519 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1520 .bus_num = 0,
1521 .chip_select = 5, /* CS, change it for your board */
1522 .platform_data = NULL, /* No spi_driver specific config */
1523 .mode = SPI_MODE_3,
1524 .irq = IRQ_PF4,
1525 },
1526#endif
1527#if defined(CONFIG_ADIS16400) \
1528 || defined(CONFIG_ADIS16400_MODULE)
1529 {
1530 .modalias = "adis16400",
1531 .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
1532 .bus_num = 0,
1533 .chip_select = 1, /* CS, change it for your board */
1534 .platform_data = NULL, /* No spi_driver specific config */
1535 .mode = SPI_MODE_3,
1536 },
1537#endif
1394f032
BW		 1538};
1539
5bda2723 1540#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1394f032 1541/* SPI controller data */
c6c4d7bb 1542static struct bfin5xx_spi_master bfin_spi0_info = {
f9f0e3b1 1543 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
1394f032 1544 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 1545 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032
BW		 1546};
1547
c6c4d7bb
BW		 1548/* SPI (0) */
1549static struct resource bfin_spi0_resource[] = {
1550 [0] = {
1551 .start = SPI0_REGBASE,
1552 .end = SPI0_REGBASE + 0xFF,
1553 .flags = IORESOURCE_MEM,
1554 },
1555 [1] = {
1556 .start = CH_SPI,
1557 .end = CH_SPI,
e68d1ebc
YL		 1558 .flags = IORESOURCE_DMA,
1559 },
1560 [2] = {
1561 .start = IRQ_SPI,
1562 .end = IRQ_SPI,
c6c4d7bb
BW		 1563 .flags = IORESOURCE_IRQ,
1564 },
1565};
1566
1567static struct platform_device bfin_spi0_device = {
1568 .name = "bfin-spi",
1569 .id = 0, /* Bus number */
1570 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1571 .resource = bfin_spi0_resource,
1394f032 1572 .dev = {
c6c4d7bb 1573 .platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032
BW		 1574 },
1575};
1576#endif /* spi master and devices */
1577
1e9aa955
CC		 1578#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
1579
1580/* SPORT SPI controller data */
1581static struct bfin5xx_spi_master bfin_sport_spi0_info = {
1582 .num_chipselect = 1, /* master only supports one device */
1583 .enable_dma = 0, /* master don't support DMA */
1584 .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
1585 P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
1586};
1587
1588static struct resource bfin_sport_spi0_resource[] = {
1589 [0] = {
1590 .start = SPORT0_TCR1,
1591 .end = SPORT0_TCR1 + 0xFF,
1592 .flags = IORESOURCE_MEM,
1593 },
1594 [1] = {
1595 .start = IRQ_SPORT0_ERROR,
1596 .end = IRQ_SPORT0_ERROR,
1597 .flags = IORESOURCE_IRQ,
1598 },
1599};
1600
1601static struct platform_device bfin_sport_spi0_device = {
1602 .name = "bfin-sport-spi",
1603 .id = 1, /* Bus number */
1604 .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
1605 .resource = bfin_sport_spi0_resource,
1606 .dev = {
1607 .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
1608 },
1609};
1610
1611static struct bfin5xx_spi_master bfin_sport_spi1_info = {
1612 .num_chipselect = 1, /* master only supports one device */
1613 .enable_dma = 0, /* master don't support DMA */
1614 .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
1615 P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
1616};
1617
1618static struct resource bfin_sport_spi1_resource[] = {
1619 [0] = {
1620 .start = SPORT1_TCR1,
1621 .end = SPORT1_TCR1 + 0xFF,
1622 .flags = IORESOURCE_MEM,
1623 },
1624 [1] = {
1625 .start = IRQ_SPORT1_ERROR,
1626 .end = IRQ_SPORT1_ERROR,
1627 .flags = IORESOURCE_IRQ,
1628 },
1629};
1630
1631static struct platform_device bfin_sport_spi1_device = {
1632 .name = "bfin-sport-spi",
1633 .id = 2, /* Bus number */
1634 .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
1635 .resource = bfin_sport_spi1_resource,
1636 .dev = {
1637 .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
1638 },
1639};
1640
1641#endif /* sport spi master and devices */
1642
1394f032
BW		 1643#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1644static struct platform_device bfin_fb_device = {
c6c4d7bb
BW		 1645 .name = "bf537-lq035",
1646};
1647#endif
1648
2043f3f7
MH		 1649#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
1650#include <asm/bfin-lq035q1.h>
1651
1652static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
d94a1aa4
MH		 1653 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
1654 .ppi_mode = USE_RGB565_16_BIT_PPI,
1655 .use_bl = 0, /* let something else control the LCD Blacklight */
1656 .gpio_bl = GPIO_PF7,
2043f3f7
MH		 1657};
1658
1659static struct resource bfin_lq035q1_resources[] = {
1660 {
1661 .start = IRQ_PPI_ERROR,
1662 .end = IRQ_PPI_ERROR,
1663 .flags = IORESOURCE_IRQ,
1664 },
1665};
1666
1667static struct platform_device bfin_lq035q1_device = {
1668 .name = "bfin-lq035q1",
1669 .id = -1,
d94a1aa4
MH		 1670 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
1671 .resource = bfin_lq035q1_resources,
2043f3f7
MH		 1672 .dev = {
1673 .platform_data = &bfin_lq035q1_data,
1674 },
1675};
1676#endif
1677
1394f032 1678#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
233b28a9 1679#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 1680static struct resource bfin_uart0_resources[] = {
1394f032 1681 {
6bd1fbea
SZ		 1682 .start = UART0_THR,
1683 .end = UART0_GCTL+2,
1394f032 1684 .flags = IORESOURCE_MEM,
233b28a9 1685 },
6bd1fbea
SZ		 1686 {
1687 .start = IRQ_UART0_RX,
1688 .end = IRQ_UART0_RX+1,
1689 .flags = IORESOURCE_IRQ,
1690 },
1691 {
1692 .start = IRQ_UART0_ERROR,
1693 .end = IRQ_UART0_ERROR,
1694 .flags = IORESOURCE_IRQ,
1695 },
1696 {
1697 .start = CH_UART0_TX,
1698 .end = CH_UART0_TX,
1699 .flags = IORESOURCE_DMA,
1700 },
1701 {
1702 .start = CH_UART0_RX,
1703 .end = CH_UART0_RX,
1704 .flags = IORESOURCE_DMA,
1705 },
1706#ifdef CONFIG_BFIN_UART0_CTSRTS
1707 { /* CTS pin */
1708 .start = GPIO_PG7,
1709 .end = GPIO_PG7,
1710 .flags = IORESOURCE_IO,
1711 },
1712 { /* RTS pin */
1713 .start = GPIO_PG6,
1714 .end = GPIO_PG6,
1715 .flags = IORESOURCE_IO,
1716 },
1717#endif
1718};
1719
a8b19886 1720static unsigned short bfin_uart0_peripherals[] = {
6bd1fbea
SZ		 1721 P_UART0_TX, P_UART0_RX, 0
1722};
1723
1724static struct platform_device bfin_uart0_device = {
1725 .name = "bfin-uart",
1726 .id = 0,
1727 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
1728 .resource = bfin_uart0_resources,
1729 .dev = {
1730 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
1731 },
1732};
233b28a9
SZ		 1733#endif
1734#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 1735static struct resource bfin_uart1_resources[] = {
233b28a9 1736 {
6bd1fbea
SZ		 1737 .start = UART1_THR,
1738 .end = UART1_GCTL+2,
1394f032
BW		 1739 .flags = IORESOURCE_MEM,
1740 },
6bd1fbea
SZ		 1741 {
1742 .start = IRQ_UART1_RX,
1743 .end = IRQ_UART1_RX+1,
1744 .flags = IORESOURCE_IRQ,
1745 },
1746 {
1747 .start = IRQ_UART1_ERROR,
1748 .end = IRQ_UART1_ERROR,
1749 .flags = IORESOURCE_IRQ,
1750 },
1751 {
1752 .start = CH_UART1_TX,
1753 .end = CH_UART1_TX,
1754 .flags = IORESOURCE_DMA,
1755 },
1756 {
1757 .start = CH_UART1_RX,
1758 .end = CH_UART1_RX,
1759 .flags = IORESOURCE_DMA,
1760 },
1761};
1762
a8b19886 1763static unsigned short bfin_uart1_peripherals[] = {
6bd1fbea 1764 P_UART1_TX, P_UART1_RX, 0
1394f032
BW		 1765};
1766
6bd1fbea 1767static struct platform_device bfin_uart1_device = {
1394f032
BW		 1768 .name = "bfin-uart",
1769 .id = 1,
6bd1fbea
SZ		 1770 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
1771 .resource = bfin_uart1_resources,
1772 .dev = {
1773 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
1774 },
1394f032
BW		 1775};
1776#endif
6bd1fbea 1777#endif
1394f032 1778
5be36d22 1779#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 1780#ifdef CONFIG_BFIN_SIR0
42bd8bcb 1781static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 1782 {
1783 .start = 0xFFC00400,
1784 .end = 0xFFC004FF,
1785 .flags = IORESOURCE_MEM,
1786 },
42bd8bcb
GY		 1787 {
1788 .start = IRQ_UART0_RX,
1789 .end = IRQ_UART0_RX+1,
1790 .flags = IORESOURCE_IRQ,
1791 },
1792 {
1793 .start = CH_UART0_RX,
1794 .end = CH_UART0_RX+1,
1795 .flags = IORESOURCE_DMA,
1796 },
1797};
1798
1799static struct platform_device bfin_sir0_device = {
1800 .name = "bfin_sir",
1801 .id = 0,
1802 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
1803 .resource = bfin_sir0_resources,
1804};
5be36d22
GY		 1805#endif
1806#ifdef CONFIG_BFIN_SIR1
42bd8bcb 1807static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 1808 {
1809 .start = 0xFFC02000,
1810 .end = 0xFFC020FF,
1811 .flags = IORESOURCE_MEM,
1812 },
42bd8bcb
GY		 1813 {
1814 .start = IRQ_UART1_RX,
1815 .end = IRQ_UART1_RX+1,
1816 .flags = IORESOURCE_IRQ,
1817 },
1818 {
1819 .start = CH_UART1_RX,
1820 .end = CH_UART1_RX+1,
1821 .flags = IORESOURCE_DMA,
1822 },
5be36d22
GY		 1823};
1824
42bd8bcb 1825static struct platform_device bfin_sir1_device = {
5be36d22 1826 .name = "bfin_sir",
42bd8bcb
GY		 1827 .id = 1,
1828 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
1829 .resource = bfin_sir1_resources,
5be36d22
GY		 1830};
1831#endif
42bd8bcb 1832#endif
5be36d22 1833
1394f032 1834#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
c6c4d7bb
BW		 1835static struct resource bfin_twi0_resource[] = {
1836 [0] = {
1837 .start = TWI0_REGBASE,
1838 .end = TWI0_REGBASE,
1839 .flags = IORESOURCE_MEM,
1840 },
1841 [1] = {
1842 .start = IRQ_TWI,
1843 .end = IRQ_TWI,
1844 .flags = IORESOURCE_IRQ,
1845 },
1846};
1847
1394f032
BW		 1848static struct platform_device i2c_bfin_twi_device = {
1849 .name = "i2c-bfin-twi",
1850 .id = 0,
c6c4d7bb
BW		 1851 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1852 .resource = bfin_twi0_resource,
1394f032
BW		 1853};
1854#endif
1855
51ed9ad7 1856#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
51ed9ad7
MH		 1857static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
1858 [0] = KEY_GRAVE,
1859 [1] = KEY_1,
1860 [2] = KEY_2,
1861 [3] = KEY_3,
1862 [4] = KEY_4,
1863 [5] = KEY_5,
1864 [6] = KEY_6,
1865 [7] = KEY_7,
1866 [8] = KEY_8,
1867 [9] = KEY_9,
1868 [10] = KEY_0,
1869 [11] = KEY_MINUS,
1870 [12] = KEY_EQUAL,
1871 [13] = KEY_BACKSLASH,
1872 [15] = KEY_KP0,
1873 [16] = KEY_Q,
1874 [17] = KEY_W,
1875 [18] = KEY_E,
1876 [19] = KEY_R,
1877 [20] = KEY_T,
1878 [21] = KEY_Y,
1879 [22] = KEY_U,
1880 [23] = KEY_I,
1881 [24] = KEY_O,
1882 [25] = KEY_P,
1883 [26] = KEY_LEFTBRACE,
1884 [27] = KEY_RIGHTBRACE,
1885 [29] = KEY_KP1,
1886 [30] = KEY_KP2,
1887 [31] = KEY_KP3,
1888 [32] = KEY_A,
1889 [33] = KEY_S,
1890 [34] = KEY_D,
1891 [35] = KEY_F,
1892 [36] = KEY_G,
1893 [37] = KEY_H,
1894 [38] = KEY_J,
1895 [39] = KEY_K,
1896 [40] = KEY_L,
1897 [41] = KEY_SEMICOLON,
1898 [42] = KEY_APOSTROPHE,
1899 [43] = KEY_BACKSLASH,
1900 [45] = KEY_KP4,
1901 [46] = KEY_KP5,
1902 [47] = KEY_KP6,
1903 [48] = KEY_102ND,
1904 [49] = KEY_Z,
1905 [50] = KEY_X,
1906 [51] = KEY_C,
1907 [52] = KEY_V,
1908 [53] = KEY_B,
1909 [54] = KEY_N,
1910 [55] = KEY_M,
1911 [56] = KEY_COMMA,
1912 [57] = KEY_DOT,
1913 [58] = KEY_SLASH,
1914 [60] = KEY_KPDOT,
1915 [61] = KEY_KP7,
1916 [62] = KEY_KP8,
1917 [63] = KEY_KP9,
1918 [64] = KEY_SPACE,
1919 [65] = KEY_BACKSPACE,
1920 [66] = KEY_TAB,
1921 [67] = KEY_KPENTER,
1922 [68] = KEY_ENTER,
1923 [69] = KEY_ESC,
1924 [70] = KEY_DELETE,
1925 [74] = KEY_KPMINUS,
1926 [76] = KEY_UP,
1927 [77] = KEY_DOWN,
1928 [78] = KEY_RIGHT,
1929 [79] = KEY_LEFT,
1930};
1931
1932static struct adp5588_kpad_platform_data adp5588_kpad_data = {
1933 .rows = 8,
1934 .cols = 10,
1935 .keymap = adp5588_keymap,
1936 .keymapsize = ARRAY_SIZE(adp5588_keymap),
1937 .repeat = 0,
1938};
1939#endif
1940
3ea57218
MH		 1941#if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE)
1942#include <linux/mfd/adp5520.h>
1943
1944 /*
1945 * ADP5520/5501 Backlight Data
1946 */
1947
1d23dc89
MH		 1948static struct adp5520_backlight_platform_data adp5520_backlight_data = {
1949 .fade_in = ADP5520_FADE_T_1200ms,
1950 .fade_out = ADP5520_FADE_T_1200ms,
1951 .fade_led_law = ADP5520_BL_LAW_LINEAR,
1952 .en_ambl_sens = 1,
1953 .abml_filt = ADP5520_BL_AMBL_FILT_640ms,
1954 .l1_daylight_max = ADP5520_BL_CUR_mA(15),
1955 .l1_daylight_dim = ADP5520_BL_CUR_mA(0),
1956 .l2_office_max = ADP5520_BL_CUR_mA(7),
1957 .l2_office_dim = ADP5520_BL_CUR_mA(0),
1958 .l3_dark_max = ADP5520_BL_CUR_mA(3),
1959 .l3_dark_dim = ADP5520_BL_CUR_mA(0),
1960 .l2_trip = ADP5520_L2_COMP_CURR_uA(700),
1961 .l2_hyst = ADP5520_L2_COMP_CURR_uA(50),
1962 .l3_trip = ADP5520_L3_COMP_CURR_uA(80),
1963 .l3_hyst = ADP5520_L3_COMP_CURR_uA(20),
3ea57218
MH		 1964};
1965
1966 /*
1967 * ADP5520/5501 LEDs Data
1968 */
1969
3ea57218
MH		 1970static struct led_info adp5520_leds[] = {
1971 {
1972 .name = "adp5520-led1",
1973 .default_trigger = "none",
1d23dc89 1974 .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
3ea57218
MH		 1975 },
1976#ifdef ADP5520_EN_ALL_LEDS
1977 {
1978 .name = "adp5520-led2",
1979 .default_trigger = "none",
1980 .flags = FLAG_ID_ADP5520_LED2_ADP5501_LED1,
1981 },
1982 {
1983 .name = "adp5520-led3",
1984 .default_trigger = "none",
1985 .flags = FLAG_ID_ADP5520_LED3_ADP5501_LED2,
1986 },
1987#endif
1988};
1989
1d23dc89 1990static struct adp5520_leds_platform_data adp5520_leds_data = {
3ea57218
MH		 1991 .num_leds = ARRAY_SIZE(adp5520_leds),
1992 .leds = adp5520_leds,
1d23dc89
MH		 1993 .fade_in = ADP5520_FADE_T_600ms,
1994 .fade_out = ADP5520_FADE_T_600ms,
1995 .led_on_time = ADP5520_LED_ONT_600ms,
3ea57218
MH		 1996};
1997
1998 /*
1999 * ADP5520 GPIO Data
2000 */
2001
1d23dc89 2002static struct adp5520_gpio_platform_data adp5520_gpio_data = {
3ea57218 2003 .gpio_start = 50,
1d23dc89
MH		 2004 .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
2005 .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
3ea57218
MH		 2006};
2007
2008 /*
2009 * ADP5520 Keypad Data
2010 */
2011
3ea57218 2012static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
1d23dc89
MH		 2013 [ADP5520_KEY(0, 0)] = KEY_GRAVE,
2014 [ADP5520_KEY(0, 1)] = KEY_1,
2015 [ADP5520_KEY(0, 2)] = KEY_2,
2016 [ADP5520_KEY(0, 3)] = KEY_3,
2017 [ADP5520_KEY(1, 0)] = KEY_4,
2018 [ADP5520_KEY(1, 1)] = KEY_5,
2019 [ADP5520_KEY(1, 2)] = KEY_6,
2020 [ADP5520_KEY(1, 3)] = KEY_7,
2021 [ADP5520_KEY(2, 0)] = KEY_8,
2022 [ADP5520_KEY(2, 1)] = KEY_9,
2023 [ADP5520_KEY(2, 2)] = KEY_0,
2024 [ADP5520_KEY(2, 3)] = KEY_MINUS,
2025 [ADP5520_KEY(3, 0)] = KEY_EQUAL,
2026 [ADP5520_KEY(3, 1)] = KEY_BACKSLASH,
2027 [ADP5520_KEY(3, 2)] = KEY_BACKSPACE,
2028 [ADP5520_KEY(3, 3)] = KEY_ENTER,
2029};
2030
2031static struct adp5520_keys_platform_data adp5520_keys_data = {
2032 .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
2033 .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
3ea57218
MH		 2034 .keymap = adp5520_keymap,
2035 .keymapsize = ARRAY_SIZE(adp5520_keymap),
2036 .repeat = 0,
2037};
2038
2039 /*
eef35c2d 2040 * ADP5520/5501 Multifunction Device Init Data
3ea57218
MH		 2041 */
2042
3ea57218 2043static struct adp5520_platform_data adp5520_pdev_data = {
1d23dc89
MH		 2044 .backlight = &adp5520_backlight_data,
2045 .leds = &adp5520_leds_data,
2046 .gpio = &adp5520_gpio_data,
2047 .keys = &adp5520_keys_data,
3ea57218
MH		 2048};
2049
2050#endif
2051
ba877d44 2052#if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE)
1d23dc89 2053static struct adp5588_gpio_platform_data adp5588_gpio_data = {
ba877d44
MH		 2054 .gpio_start = 50,
2055 .pullup_dis_mask = 0,
2056};
2057#endif
2058
78756c62
MH		 2059#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
2060#include <linux/i2c/adp8870.h>
2061static struct led_info adp8870_leds[] = {
2062 {
2063 .name = "adp8870-led7",
2064 .default_trigger = "none",
2065 .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms,
2066 },
2067};
2068
2069
2070static struct adp8870_backlight_platform_data adp8870_pdata = {
2071 .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 |
2072 ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6, /* 1 = Backlight 0 = Individual LED */
2073 .pwm_assign = 0, /* 1 = Enables PWM mode */
2074
2075 .bl_fade_in = ADP8870_FADE_T_1200ms, /* Backlight Fade-In Timer */
2076 .bl_fade_out = ADP8870_FADE_T_1200ms, /* Backlight Fade-Out Timer */
2077 .bl_fade_law = ADP8870_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */
2078
2079 .en_ambl_sens = 1, /* 1 = enable ambient light sensor */
2080 .abml_filt = ADP8870_BL_AMBL_FILT_320ms, /* Light sensor filter time */
2081
2082 .l1_daylight_max = ADP8870_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
2083 .l1_daylight_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
2084 .l2_bright_max = ADP8870_BL_CUR_mA(14), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
2085 .l2_bright_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
2086 .l3_office_max = ADP8870_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
2087 .l3_office_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
2088 .l4_indoor_max = ADP8870_BL_CUR_mA(3), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
2089 .l4_indor_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
2090 .l5_dark_max = ADP8870_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
2091 .l5_dark_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
2092
2093 .l2_trip = ADP8870_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
2094 .l2_hyst = ADP8870_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
2095 .l3_trip = ADP8870_L3_COMP_CURR_uA(389), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
2096 .l3_hyst = ADP8870_L3_COMP_CURR_uA(54), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
2097 .l4_trip = ADP8870_L4_COMP_CURR_uA(167), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
2098 .l4_hyst = ADP8870_L4_COMP_CURR_uA(16), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
2099 .l5_trip = ADP8870_L5_COMP_CURR_uA(43), /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */
2100 .l5_hyst = ADP8870_L5_COMP_CURR_uA(11), /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */
2101
2102 .leds = adp8870_leds,
2103 .num_leds = ARRAY_SIZE(adp8870_leds),
2104 .led_fade_law = ADP8870_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */
2105 .led_fade_in = ADP8870_FADE_T_600ms,
2106 .led_fade_out = ADP8870_FADE_T_600ms,
2107 .led_on_time = ADP8870_LED_ONT_200ms,
2108};
2109#endif
2110
72fa2e92
MH		 2111#if defined(CONFIG_BACKLIGHT_ADP8860) || defined(CONFIG_BACKLIGHT_ADP8860_MODULE)
2112#include <linux/i2c/adp8860.h>
2113static struct led_info adp8860_leds[] = {
2114 {
2115 .name = "adp8860-led7",
2116 .default_trigger = "none",
2117 .flags = ADP8860_LED_D7 | ADP8860_LED_OFFT_600ms,
2118 },
2119};
2120
2121static struct adp8860_backlight_platform_data adp8860_pdata = {
2122 .bl_led_assign = ADP8860_BL_D1 | ADP8860_BL_D2 | ADP8860_BL_D3 |
2123 ADP8860_BL_D4 | ADP8860_BL_D5 | ADP8860_BL_D6, /* 1 = Backlight 0 = Individual LED */
2124
2125 .bl_fade_in = ADP8860_FADE_T_1200ms, /* Backlight Fade-In Timer */
2126 .bl_fade_out = ADP8860_FADE_T_1200ms, /* Backlight Fade-Out Timer */
2127 .bl_fade_law = ADP8860_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */
2128
2129 .en_ambl_sens = 1, /* 1 = enable ambient light sensor */
2130 .abml_filt = ADP8860_BL_AMBL_FILT_320ms, /* Light sensor filter time */
2131
2132 .l1_daylight_max = ADP8860_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
2133 .l1_daylight_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
2134 .l2_office_max = ADP8860_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
2135 .l2_office_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
2136 .l3_dark_max = ADP8860_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
2137 .l3_dark_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
2138
2139 .l2_trip = ADP8860_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
2140 .l2_hyst = ADP8860_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
2141 .l3_trip = ADP8860_L3_COMP_CURR_uA(43), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */
2142 .l3_hyst = ADP8860_L3_COMP_CURR_uA(11), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */
2143
2144 .leds = adp8860_leds,
2145 .num_leds = ARRAY_SIZE(adp8860_leds),
2146 .led_fade_law = ADP8860_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */
2147 .led_fade_in = ADP8860_FADE_T_600ms,
2148 .led_fade_out = ADP8860_FADE_T_600ms,
2149 .led_on_time = ADP8860_LED_ONT_200ms,
2150};
2151#endif
2152
f32792d0
SZ		 2153#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
2154static struct regulator_consumer_supply ad5398_consumer = {
2155 .supply = "current",
2156};
2157
2158static struct regulator_init_data ad5398_regulator_data = {
2159 .constraints = {
2160 .name = "current range",
2161 .max_uA = 120000,
2162 .valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS,
2163 },
2164 .num_consumer_supplies = 1,
2165 .consumer_supplies = &ad5398_consumer,
2166};
2167
f32792d0
SZ		 2168#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \
2169 defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE)
2170static struct platform_device ad5398_virt_consumer_device = {
2171 .name = "reg-virt-consumer",
2172 .id = 0,
2173 .dev = {
2174 .platform_data = "current", /* Passed to driver */
2175 },
2176};
2177#endif
2178#if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \
2179 defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE)
2180static struct regulator_bulk_data ad5398_bulk_data = {
2181 .supply = "current",
2182};
2183
2184static struct regulator_userspace_consumer_data ad5398_userspace_comsumer_data = {
2185 .name = "ad5398",
2186 .num_supplies = 1,
2187 .supplies = &ad5398_bulk_data,
2188};
2189
2190static struct platform_device ad5398_userspace_consumer_device = {
2191 .name = "reg-userspace-consumer",
2192 .id = 0,
2193 .dev = {
2194 .platform_data = &ad5398_userspace_comsumer_data,
2195 },
2196};
2197#endif
2198#endif
2199
0891baef
MH		 2200#if defined(CONFIG_ADT7410) || defined(CONFIG_ADT7410_MODULE)
2201/* INT bound temperature alarm event. line 1 */
2202static unsigned long adt7410_platform_data[2] = {
2203 IRQ_PG4, IRQF_TRIGGER_LOW,
2204};
2205#endif
2206
2207#if defined(CONFIG_ADT7316_I2C) || defined(CONFIG_ADT7316_I2C_MODULE)
2208/* INT bound temperature alarm event. line 1 */
2209static unsigned long adt7316_i2c_data[2] = {
2210 IRQF_TRIGGER_LOW, /* interrupt flags */
2211 GPIO_PF4, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
2212};
2213#endif
2214
81d9c7f2 2215static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
92b20f7f
BS		 2216#if defined(CONFIG_SND_BF5XX_SOC_AD193X) || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE)
2217 {
2218 I2C_BOARD_INFO("ad1937", 0x04),
2219 },
2220#endif
2221
a65912ca
YL		 2222#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
2223 {
2224 I2C_BOARD_INFO("adav803", 0x10),
2225 },
2226#endif
2227
5b7c5775 2228#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE)
81d9c7f2 2229 {
427f277e 2230 I2C_BOARD_INFO("ad7142_captouch", 0x2C),
4c94c3e0 2231 .irq = IRQ_PG5,
5b7c5775 2232 .platform_data = (void *)&ad7142_i2c_platform_data,
81d9c7f2
BW		 2233 },
2234#endif
ad6720c0
BS		 2235
2236#if defined(CONFIG_AD7150) || defined(CONFIG_AD7150_MODULE)
2237 {
2238 I2C_BOARD_INFO("ad7150", 0x48),
2239 .irq = IRQ_PG5, /* fixme: use real interrupt number */
2240 },
2241#endif
2242
2243#if defined(CONFIG_AD7152) || defined(CONFIG_AD7152_MODULE)
2244 {
2245 I2C_BOARD_INFO("ad7152", 0x48),
2246 },
2247#endif
2248
2249#if defined(CONFIG_AD774X) || defined(CONFIG_AD774X_MODULE)
2250 {
2251 I2C_BOARD_INFO("ad774x", 0x48),
2252 },
2253#endif
2254
5f022594
SZ		 2255#if defined(CONFIG_AD7414) || defined(CONFIG_AD7414_MODULE)
2256 {
2257 I2C_BOARD_INFO("ad7414", 0x9),
2258 .irq = IRQ_PG5,
0891baef 2259 .irq_flags = IRQF_TRIGGER_LOW,
5f022594
SZ		 2260 },
2261#endif
2262
ef8873e0
SZ		 2263#if defined(CONFIG_AD7416) || defined(CONFIG_AD7416_MODULE)
2264 {
2265 I2C_BOARD_INFO("ad7417", 0xb),
2266 .irq = IRQ_PG5,
0891baef
MH		 2267 .irq_flags = IRQF_TRIGGER_LOW,
2268 .platform_data = (void *)GPIO_PF4,
2269 },
2270#endif
2271
2272#if defined(CONFIG_ADE7854_I2C) || defined(CONFIG_ADE7854_I2C_MODULE)
2273 {
2274 I2C_BOARD_INFO("ade7854", 0x38),
2275 },
2276#endif
2277
2278#if defined(CONFIG_ADT75) || defined(CONFIG_ADT75_MODULE)
2279 {
2280 I2C_BOARD_INFO("adt75", 0x9),
2281 .irq = IRQ_PG5,
2282 .irq_flags = IRQF_TRIGGER_LOW,
2283 },
2284#endif
2285
2286#if defined(CONFIG_ADT7408) || defined(CONFIG_ADT7408_MODULE)
2287 {
2288 I2C_BOARD_INFO("adt7408", 0x18),
2289 .irq = IRQ_PG5,
2290 .irq_flags = IRQF_TRIGGER_LOW,
2291 },
2292#endif
2293
2294#if defined(CONFIG_ADT7410) || defined(CONFIG_ADT7410_MODULE)
2295 {
2296 I2C_BOARD_INFO("adt7410", 0x48),
2297 /* CT critical temperature event. line 0 */
2298 .irq = IRQ_PG5,
2299 .irq_flags = IRQF_TRIGGER_LOW,
2300 .platform_data = (void *)&adt7410_platform_data,
2301 },
2302#endif
2303
2304#if defined(CONFIG_AD7291) || defined(CONFIG_AD7291_MODULE)
2305 {
2306 I2C_BOARD_INFO("ad7291", 0x20),
2307 .irq = IRQ_PG5,
2308 .irq_flags = IRQF_TRIGGER_LOW,
2309 },
2310#endif
2311
2312#if defined(CONFIG_ADT7316_I2C) || defined(CONFIG_ADT7316_I2C_MODULE)
2313 {
2314 I2C_BOARD_INFO("adt7316", 0x48),
2315 .irq = IRQ_PG6,
2316 .platform_data = (void *)&adt7316_i2c_data,
ef8873e0
SZ		 2317 },
2318#endif
2319
ebd58333 2320#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
81d9c7f2
BW		 2321 {
2322 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
81d9c7f2
BW		 2323 },
2324#endif
204844eb 2325#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
81d9c7f2
BW		 2326 {
2327 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
f5150155
MH		 2328 .irq = IRQ_PG6,
2329 },
2330#endif
2331#if defined(CONFIG_TOUCHSCREEN_AD7879_I2C) || defined(CONFIG_TOUCHSCREEN_AD7879_I2C_MODULE)
2332 {
2333 I2C_BOARD_INFO("ad7879", 0x2F),
2334 .irq = IRQ_PG5,
2335 .platform_data = (void *)&bfin_ad7879_ts_info,
81d9c7f2
BW		 2336 },
2337#endif
51ed9ad7
MH		 2338#if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE)
2339 {
2340 I2C_BOARD_INFO("adp5588-keys", 0x34),
2341 .irq = IRQ_PG0,
2342 .platform_data = (void *)&adp5588_kpad_data,
2343 },
2344#endif
3ea57218
MH		 2345#if defined(CONFIG_PMIC_ADP5520) || defined(CONFIG_PMIC_ADP5520_MODULE)
2346 {
2347 I2C_BOARD_INFO("pmic-adp5520", 0x32),
4f84b6e0 2348 .irq = IRQ_PG0,
3ea57218
MH		 2349 .platform_data = (void *)&adp5520_pdev_data,
2350 },
2351#endif
ffc4d8bc
MH		 2352#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
2353 {
2354 I2C_BOARD_INFO("adxl34x", 0x53),
2355 .irq = IRQ_PG3,
2356 .platform_data = (void *)&adxl34x_info,
2357 },
2358#endif
ba877d44
MH		 2359#if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE)
2360 {
2361 I2C_BOARD_INFO("adp5588-gpio", 0x34),
2362 .platform_data = (void *)&adp5588_gpio_data,
2363 },
2364#endif
50c4c086
MH		 2365#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
2366 {
2367 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
2368 },
2369#endif
ddcd7cb8
MH		 2370#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
2371 {
948ca1a7 2372 I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F),
ddcd7cb8
MH		 2373 },
2374#endif
78756c62
MH		 2375#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE)
2376 {
2377 I2C_BOARD_INFO("adp8870", 0x2B),
2378 .platform_data = (void *)&adp8870_pdata,
2379 },
2380#endif
d53127ff
CC		 2381#if defined(CONFIG_SND_SOC_ADAU1371) || defined(CONFIG_SND_SOC_ADAU1371_MODULE)
2382 {
2383 I2C_BOARD_INFO("adau1371", 0x1A),
2384 },
2385#endif
04267638
CC		 2386#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
2387 {
2388 I2C_BOARD_INFO("adau1761", 0x38),
2389 },
2390#endif
c48d7675
CC		 2391#if defined(CONFIG_SND_SOC_ADAU1361) || defined(CONFIG_SND_SOC_ADAU1361_MODULE)
2392 {
2393 I2C_BOARD_INFO("adau1361", 0x38),
2394 },
2395#endif
1f13f2fd
MH		 2396#if defined(CONFIG_AD525X_DPOT) || defined(CONFIG_AD525X_DPOT_MODULE)
2397 {
2398 I2C_BOARD_INFO("ad5258", 0x18),
2399 },
2400#endif
29bb3bc0
CC		 2401#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
2402 {
2403 I2C_BOARD_INFO("ssm2602", 0x1b),
2404 },
2405#endif
f32792d0
SZ		 2406#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
2407 {
2408 I2C_BOARD_INFO("ad5398", 0xC),
27e9f0b4 2409 .platform_data = (void *)&ad5398_regulator_data,
f32792d0
SZ		 2410 },
2411#endif
72fa2e92
MH		 2412#if defined(CONFIG_BACKLIGHT_ADP8860) || defined(CONFIG_BACKLIGHT_ADP8860_MODULE)
2413 {
2414 I2C_BOARD_INFO("adp8860", 0x2A),
2415 .platform_data = (void *)&adp8860_pdata,
2416 },
2417#endif
3cbcb161
CC		 2418#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE)
2419 {
2420 I2C_BOARD_INFO("adau1373", 0x1A),
2421 },
2422#endif
39d3c1ca 2423#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
2424 {
2425 I2C_BOARD_INFO("ad5252", 0x2e),
2426 },
2427#endif
81d9c7f2 2428};
81d9c7f2 2429
1394f032 2430#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261
SZ		 2431#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2432static struct resource bfin_sport0_uart_resources[] = {
2433 {
2434 .start = SPORT0_TCR1,
2435 .end = SPORT0_MRCS3+4,
2436 .flags = IORESOURCE_MEM,
2437 },
2438 {
2439 .start = IRQ_SPORT0_RX,
2440 .end = IRQ_SPORT0_RX+1,
2441 .flags = IORESOURCE_IRQ,
2442 },
2443 {
2444 .start = IRQ_SPORT0_ERROR,
2445 .end = IRQ_SPORT0_ERROR,
2446 .flags = IORESOURCE_IRQ,
2447 },
2448};
2449
a8b19886 2450static unsigned short bfin_sport0_peripherals[] = {
df5de261 2451 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
e54b6730 2452 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
df5de261
SZ		 2453};
2454
1394f032
BW		 2455static struct platform_device bfin_sport0_uart_device = {
2456 .name = "bfin-sport-uart",
2457 .id = 0,
df5de261
SZ		 2458 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
2459 .resource = bfin_sport0_uart_resources,
2460 .dev = {
2461 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
2462 },
2463};
2464#endif
2465#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2466static struct resource bfin_sport1_uart_resources[] = {
2467 {
2468 .start = SPORT1_TCR1,
2469 .end = SPORT1_MRCS3+4,
2470 .flags = IORESOURCE_MEM,
2471 },
2472 {
2473 .start = IRQ_SPORT1_RX,
2474 .end = IRQ_SPORT1_RX+1,
2475 .flags = IORESOURCE_IRQ,
2476 },
2477 {
2478 .start = IRQ_SPORT1_ERROR,
2479 .end = IRQ_SPORT1_ERROR,
2480 .flags = IORESOURCE_IRQ,
2481 },
2482};
2483
a8b19886 2484static unsigned short bfin_sport1_peripherals[] = {
df5de261 2485 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
e54b6730 2486 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
1394f032
BW		 2487};
2488
2489static struct platform_device bfin_sport1_uart_device = {
2490 .name = "bfin-sport-uart",
2491 .id = 1,
df5de261
SZ		 2492 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
2493 .resource = bfin_sport1_uart_resources,
2494 .dev = {
2495 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
2496 },
1394f032
BW		 2497};
2498#endif
df5de261 2499#endif
1394f032 2500
c6c4d7bb 2501#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
2c8beb2c
MH		 2502#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
2503/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */
c6c4d7bb 2504
2c8beb2c
MH		 2505#ifdef CF_IDE_NAND_CARD_USE_HDD_INTERFACE
2506#define PATA_INT IRQ_PF5
c6c4d7bb
BW		 2507static struct pata_platform_info bfin_pata_platform_data = {
2508 .ioport_shift = 1,
64e5c512 2509 .irq_flags = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
c6c4d7bb
BW		 2510};
2511
2512static struct resource bfin_pata_resources[] = {
2513 {
2514 .start = 0x20314020,
2515 .end = 0x2031403F,
2516 .flags = IORESOURCE_MEM,
2517 },
2518 {
2519 .start = 0x2031401C,
2520 .end = 0x2031401F,
2521 .flags = IORESOURCE_MEM,
2522 },
2523 {
2524 .start = PATA_INT,
2525 .end = PATA_INT,
2526 .flags = IORESOURCE_IRQ,
2527 },
2528};
2c8beb2c
MH		 2529#elif defined(CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE)
2530static struct pata_platform_info bfin_pata_platform_data = {
2531 .ioport_shift = 0,
2532};
25985edc 2533/* CompactFlash Storage Card Memory Mapped Addressing
648882d9
MH		 2534 * /REG = A11 = 1
2535 */
2c8beb2c
MH		 2536static struct resource bfin_pata_resources[] = {
2537 {
648882d9
MH		 2538 .start = 0x20211800,
2539 .end = 0x20211807,
2c8beb2c
MH		 2540 .flags = IORESOURCE_MEM,
2541 },
2542 {
648882d9
MH		 2543 .start = 0x2021180E, /* Device Ctl */
2544 .end = 0x2021180E,
2c8beb2c
MH		 2545 .flags = IORESOURCE_MEM,
2546 },
2547};
2548#endif
c6c4d7bb
BW		 2549
2550static struct platform_device bfin_pata_device = {
2551 .name = "pata_platform",
2552 .id = -1,
2553 .num_resources = ARRAY_SIZE(bfin_pata_resources),
2554 .resource = bfin_pata_resources,
2555 .dev = {
2556 .platform_data = &bfin_pata_platform_data,
2557 }
2558};
2559#endif
2560
14b03204
MH		 2561static const unsigned int cclk_vlev_datasheet[] =
2562{
2563 VRPAIR(VLEV_085, 250000000),
2564 VRPAIR(VLEV_090, 376000000),
2565 VRPAIR(VLEV_095, 426000000),
2566 VRPAIR(VLEV_100, 426000000),
2567 VRPAIR(VLEV_105, 476000000),
2568 VRPAIR(VLEV_110, 476000000),
2569 VRPAIR(VLEV_115, 476000000),
2570 VRPAIR(VLEV_120, 500000000),
2571 VRPAIR(VLEV_125, 533000000),
2572 VRPAIR(VLEV_130, 600000000),
2573};
2574
2575static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
2576 .tuple_tab = cclk_vlev_datasheet,
2577 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
2578 .vr_settling_time = 25 /* us */,
2579};
2580
2581static struct platform_device bfin_dpmc = {
2582 .name = "bfin dpmc",
2583 .dev = {
2584 .platform_data = &bfin_dmpc_vreg_data,
2585 },
2586};
2587
6f53dbbb
SJ		 2588#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
2589 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
2590 defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
2591
2592#define SPORT_REQ(x) \
2593 [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
2594 P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
2595
2596static const u16 bfin_snd_pin[][7] = {
2597 SPORT_REQ(0),
2598 SPORT_REQ(1),
2599};
2600
2601static struct bfin_snd_platform_data bfin_snd_data[] = {
2602 {
2603 .pin_req = &bfin_snd_pin[0][0],
2604 },
2605 {
2606 .pin_req = &bfin_snd_pin[1][0],
2607 },
2608};
2609
2610#define BFIN_SND_RES(x) \
2611 [x] = { \
2612 { \
2613 .start = SPORT##x##_TCR1, \
2614 .end = SPORT##x##_TCR1, \
2615 .flags = IORESOURCE_MEM \
2616 }, \
2617 { \
2618 .start = CH_SPORT##x##_RX, \
2619 .end = CH_SPORT##x##_RX, \
2620 .flags = IORESOURCE_DMA, \
2621 }, \
2622 { \
2623 .start = CH_SPORT##x##_TX, \
2624 .end = CH_SPORT##x##_TX, \
2625 .flags = IORESOURCE_DMA, \
2626 }, \
2627 { \
2628 .start = IRQ_SPORT##x##_ERROR, \
2629 .end = IRQ_SPORT##x##_ERROR, \
2630 .flags = IORESOURCE_IRQ, \
2631 } \
2632 }
2633
2634static struct resource bfin_snd_resources[][4] = {
2635 BFIN_SND_RES(0),
2636 BFIN_SND_RES(1),
2637};
2638
2639static struct platform_device bfin_pcm = {
2640 .name = "bfin-pcm-audio",
2641 .id = -1,
2642};
2643#endif
2644
2645#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
2646static struct platform_device bfin_ad73311_codec_device = {
2647 .name = "ad73311",
2648 .id = -1,
2649};
2650#endif
2651
2652#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
336746ed
BS		 2653static struct platform_device bfin_i2s = {
2654 .name = "bfin-i2s",
2655 .id = CONFIG_SND_BF5XX_SPORT_NUM,
6f53dbbb
SJ		 2656 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
2657 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
2658 .dev = {
2659 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
2660 },
336746ed
BS		 2661};
2662#endif
2663
6f53dbbb 2664#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
8312440e
BS		 2665static struct platform_device bfin_tdm = {
2666 .name = "bfin-tdm",
336746ed 2667 .id = CONFIG_SND_BF5XX_SPORT_NUM,
6f53dbbb
SJ		 2668 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
2669 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
2670 .dev = {
2671 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
2672 },
336746ed
BS		 2673};
2674#endif
2675
6f53dbbb 2676#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
336746ed
BS		 2677static struct platform_device bfin_ac97 = {
2678 .name = "bfin-ac97",
2679 .id = CONFIG_SND_BF5XX_SPORT_NUM,
6f53dbbb
SJ		 2680 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
2681 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
2682 .dev = {
2683 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
2684 },
8312440e
BS		 2685};
2686#endif
2687
1b04cbea
SZ		 2688#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
2689#define REGULATOR_ADP122 "adp122"
2690#define REGULATOR_ADP122_UV 2500000
f8e6dbff
SZ		 2691
2692static struct regulator_consumer_supply adp122_consumers = {
2693 .supply = REGULATOR_ADP122,
2694};
2695
1b04cbea
SZ		 2696static struct regulator_init_data adp_switch_regulator_data = {
2697 .constraints = {
2698 .name = REGULATOR_ADP122,
2699 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2700 .min_uV = REGULATOR_ADP122_UV,
2701 .max_uV = REGULATOR_ADP122_UV,
2702 .min_uA = 0,
2703 .max_uA = 300000,
f8e6dbff 2704 },
1b04cbea
SZ		 2705 .num_consumer_supplies = 1, /* only 1 */
2706 .consumer_supplies = &adp122_consumers,
f8e6dbff
SZ		 2707};
2708
1b04cbea
SZ		 2709static struct fixed_voltage_config adp_switch_pdata = {
2710 .supply_name = REGULATOR_ADP122,
2711 .microvolts = REGULATOR_ADP122_UV,
2712 .gpio = GPIO_PF2,
2713 .enable_high = 1,
2714 .enabled_at_boot = 0,
2715 .init_data = &adp_switch_regulator_data,
f8e6dbff
SZ		 2716};
2717
2718static struct platform_device adp_switch_device = {
1b04cbea 2719 .name = "reg-fixed-voltage",
f8e6dbff
SZ		 2720 .id = 0,
2721 .dev = {
2722 .platform_data = &adp_switch_pdata,
2723 },
2724};
2725
2726#if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \
2727 defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE)
2728static struct regulator_bulk_data adp122_bulk_data = {
2729 .supply = REGULATOR_ADP122,
2730};
2731
2732static struct regulator_userspace_consumer_data adp122_userspace_comsumer_data = {
2733 .name = REGULATOR_ADP122,
2734 .num_supplies = 1,
2735 .supplies = &adp122_bulk_data,
2736};
2737
2738static struct platform_device adp122_userspace_consumer_device = {
2739 .name = "reg-userspace-consumer",
2740 .id = 0,
2741 .dev = {
2742 .platform_data = &adp122_userspace_comsumer_data,
2743 },
2744};
f8e6dbff
SZ		 2745#endif
2746#endif
2747
0891baef
MH		 2748#if defined(CONFIG_IIO_GPIO_TRIGGER) || \
2749 defined(CONFIG_IIO_GPIO_TRIGGER_MODULE)
2750
2751static struct resource iio_gpio_trigger_resources[] = {
2752 [0] = {
2753 .start = IRQ_PF5,
2754 .end = IRQ_PF5,
2755 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
2756 },
2757};
2758
2759static struct platform_device iio_gpio_trigger = {
2760 .name = "iio_gpio_trigger",
2761 .num_resources = ARRAY_SIZE(iio_gpio_trigger_resources),
2762 .resource = iio_gpio_trigger_resources,
2763};
2764#endif
f8e6dbff 2765
1394f032 2766static struct platform_device *stamp_devices[] __initdata = {
14b03204
MH		 2767
2768 &bfin_dpmc,
2769
1394f032
BW		 2770#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
2771 &bfin_pcmcia_cf_device,
2772#endif
2773
2774#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
2775 &rtc_device,
2776#endif
2777
2778#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
2779 &sl811_hcd_device,
2780#endif
2781
2782#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
2783 &isp1362_hcd_device,
2784#endif
2785
3f375690
MH		 2786#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
2787 &bfin_isp1760_device,
2788#endif
2789
1394f032
BW		 2790#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
2791 &smc91x_device,
2792#endif
2793
f40d24d9
AL		 2794#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
2795 &dm9000_device,
2796#endif
2797
706a01b1
BS		 2798#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
2799 &bfin_can_device,
2800#endif
2801
1394f032 2802#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 2803 &bfin_mii_bus,
1394f032
BW		 2804 &bfin_mac_device,
2805#endif
2806
2807#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
2808 &net2272_bfin_device,
2809#endif
2810
2811#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb 2812 &bfin_spi0_device,
1394f032
BW		 2813#endif
2814
1e9aa955
CC		 2815#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
2816 &bfin_sport_spi0_device,
2817 &bfin_sport_spi1_device,
2818#endif
2819
1394f032
BW		 2820#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
2821 &bfin_fb_device,
2822#endif
2823
2043f3f7
MH		 2824#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
2825 &bfin_lq035q1_device,
2826#endif
2827
1394f032 2828#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 2829#ifdef CONFIG_SERIAL_BFIN_UART0
2830 &bfin_uart0_device,
2831#endif
2832#ifdef CONFIG_SERIAL_BFIN_UART1
2833 &bfin_uart1_device,
2834#endif
1394f032
BW		 2835#endif
2836
5be36d22 2837#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 2838#ifdef CONFIG_BFIN_SIR0
2839 &bfin_sir0_device,
2840#endif
2841#ifdef CONFIG_BFIN_SIR1
2842 &bfin_sir1_device,
2843#endif
5be36d22
GY		 2844#endif
2845
1394f032
BW		 2846#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
2847 &i2c_bfin_twi_device,
2848#endif
2849
2850#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261 2851#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1394f032 2852 &bfin_sport0_uart_device,
df5de261
SZ		 2853#endif
2854#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1394f032
BW		 2855 &bfin_sport1_uart_device,
2856#endif
df5de261 2857#endif
c6c4d7bb
BW		 2858
2859#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
2860 &bfin_pata_device,
2861#endif
2463ef22
MH		 2862
2863#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
2864 &bfin_device_gpiokeys,
2865#endif
cad2ab65 2866
fc68911e
MF		 2867#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
2868 &bfin_async_nand_device,
2869#endif
2870
793dc27b 2871#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
de8c43f2 2872 &stamp_flash_device,
793dc27b 2873#endif
8312440e 2874
6f53dbbb
SJ		 2875#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
2876 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
2877 defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
2878 &bfin_pcm,
2879#endif
2880
2881#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
2882 &bfin_ad73311_codec_device,
2883#endif
2884
2885#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
336746ed
BS		 2886 &bfin_i2s,
2887#endif
2888
6f53dbbb 2889#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
8312440e
BS		 2890 &bfin_tdm,
2891#endif
336746ed 2892
6f53dbbb 2893#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
336746ed
BS		 2894 &bfin_ac97,
2895#endif
6f53dbbb 2896
f32792d0
SZ		 2897#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
2898#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \
2899 defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE)
2900 &ad5398_virt_consumer_device,
2901#endif
2902#if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \
2903 defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE)
2904 &ad5398_userspace_consumer_device,
2905#endif
2906#endif
f8e6dbff 2907
1b04cbea 2908#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
f8e6dbff
SZ		 2909 &adp_switch_device,
2910#if defined(CONFIG_REGULATOR_USERSPACE_CONSUMER) || \
2911 defined(CONFIG_REGULATOR_USERSPACE_CONSUMER_MODULE)
2912 &adp122_userspace_consumer_device,
f8e6dbff
SZ		 2913#endif
2914#endif
0891baef
MH		 2915
2916#if defined(CONFIG_IIO_GPIO_TRIGGER) || \
2917 defined(CONFIG_IIO_GPIO_TRIGGER_MODULE)
2918 &iio_gpio_trigger,
2919#endif
1394f032
BW		 2920};
2921
9be8631b
MF		 2922static int __init net2272_init(void)
2923{
2924#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
2925 int ret;
2926
2927 ret = gpio_request(GPIO_PF6, "net2272");
2928 if (ret)
2929 return ret;
2930
2931 /* Reset the USB chip */
2932 gpio_direction_output(GPIO_PF6, 0);
2933 mdelay(2);
2934 gpio_set_value(GPIO_PF6, 1);
2935#endif
2936
2937 return 0;
2938}
2939
1394f032
BW		 2940static int __init stamp_init(void)
2941{
b85d858b 2942 printk(KERN_INFO "%s(): registering device resources\n", __func__);
fc68911e 2943 bfin_plat_nand_init();
0531c467 2944 adf702x_mac_init();
1394f032 2945 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
df5de261
SZ		 2946 i2c_register_board_info(0, bfin_i2c_board_info,
2947 ARRAY_SIZE(bfin_i2c_board_info));
5bda2723 2948 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
c6c4d7bb 2949
9be8631b
MF		 2950 if (net2272_init())
2951 pr_warning("unable to configure net2272; it probably won't work\n");
2952
1394f032
BW		 2953 return 0;
2954}
2955
2956arch_initcall(stamp_init);
c6c4d7bb 2957
c13ce9fd
SZ		 2958
2959static struct platform_device *stamp_early_devices[] __initdata = {
2960#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
2961#ifdef CONFIG_SERIAL_BFIN_UART0
2962 &bfin_uart0_device,
2963#endif
2964#ifdef CONFIG_SERIAL_BFIN_UART1
2965 &bfin_uart1_device,
2966#endif
2967#endif
2968
2969#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
2970#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2971 &bfin_sport0_uart_device,
2972#endif
2973#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2974 &bfin_sport1_uart_device,
2975#endif
2976#endif
2977};
2978
2979void __init native_machine_early_platform_add_devices(void)
2980{
2981 printk(KERN_INFO "register early platform devices\n");
2982 early_platform_add_devices(stamp_early_devices,
2983 ARRAY_SIZE(stamp_early_devices));
2984}
2985
c6c4d7bb
BW		 2986void native_machine_restart(char *cmd)
2987{
2988 /* workaround reboot hang when booting from SPI */
2989 if ((bfin_read_SYSCR() & 0x7) == 0x3)
b52dae31 2990 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
c6c4d7bb 2991}
137b1529
MF		 2992
2993/*
2994 * Currently the MAC address is saved in Flash by U-Boot
2995 */
2996#define FLASH_MAC 0x203f0000
9862cc52 2997void bfin_get_ether_addr(char *addr)
137b1529
MF		 2998{
2999 *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
3000 *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
3001}
9862cc52 3002EXPORT_SYMBOL(bfin_get_ether_addr);
Linux kernel - Deliverables
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