Commit | Line | Data |
---|---|---|
24a07a12 | 1 | /* |
96f1050d RG |
2 | * Copyright 2004-2009 Analog Devices Inc. |
3 | * 2005 National ICT Australia (NICTA) | |
4 | * Aidan Williams <aidan@nicta.com.au> | |
24a07a12 | 5 | * |
96f1050d | 6 | * Licensed under the GPL-2 or later. |
24a07a12 RH |
7 | */ |
8 | ||
9 | #include <linux/device.h> | |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/mtd/mtd.h> | |
12 | #include <linux/mtd/partitions.h> | |
de8c43f2 | 13 | #include <linux/mtd/physmap.h> |
24a07a12 RH |
14 | #include <linux/spi/spi.h> |
15 | #include <linux/spi/flash.h> | |
1f83b8f1 | 16 | #include <linux/irq.h> |
81d9c7f2 | 17 | #include <linux/i2c.h> |
24a07a12 | 18 | #include <linux/interrupt.h> |
c6c4d7bb | 19 | #include <linux/usb/musb.h> |
54e4ff4d SZ |
20 | #include <linux/pinctrl/machine.h> |
21 | #include <linux/pinctrl/pinconf-generic.h> | |
22 | #include <linux/platform_data/pinctrl-adi2.h> | |
24a07a12 | 23 | #include <asm/bfin5xx_spi.h> |
c6c4d7bb BW |
24 | #include <asm/dma.h> |
25 | #include <asm/gpio.h> | |
26 | #include <asm/nand.h> | |
14b03204 | 27 | #include <asm/dpmc.h> |
6f53dbbb | 28 | #include <asm/bfin_sport.h> |
5d448dd5 | 29 | #include <asm/portmux.h> |
501674a5 | 30 | #include <asm/bfin_sdh.h> |
639f6571 | 31 | #include <mach/bf54x_keys.h> |
c6c4d7bb BW |
32 | #include <linux/input.h> |
33 | #include <linux/spi/ad7877.h> | |
24a07a12 RH |
34 | |
35 | /* | |
36 | * Name the Board for the /proc/cpuinfo | |
37 | */ | |
fe85cad2 | 38 | const char bfin_board_name[] = "ADI BF548-EZKIT"; |
24a07a12 RH |
39 | |
40 | /* | |
41 | * Driver needs to know address, irq and flag pin. | |
42 | */ | |
43 | ||
0a6304a9 | 44 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) |
3f375690 MH |
45 | #include <linux/usb/isp1760.h> |
46 | static struct resource bfin_isp1760_resources[] = { | |
0a6304a9 | 47 | [0] = { |
0a6304a9 MH |
48 | .start = 0x2C0C0000, |
49 | .end = 0x2C0C0000 + 0xfffff, | |
50 | .flags = IORESOURCE_MEM, | |
51 | }, | |
52 | [1] = { | |
53 | .start = IRQ_PG7, | |
54 | .end = IRQ_PG7, | |
55 | .flags = IORESOURCE_IRQ, | |
56 | }, | |
57 | }; | |
58 | ||
3f375690 MH |
59 | static struct isp1760_platform_data isp1760_priv = { |
60 | .is_isp1761 = 0, | |
3f375690 MH |
61 | .bus_width_16 = 1, |
62 | .port1_otg = 0, | |
63 | .analog_oc = 0, | |
64 | .dack_polarity_high = 0, | |
65 | .dreq_polarity_high = 0, | |
0a6304a9 MH |
66 | }; |
67 | ||
3f375690 | 68 | static struct platform_device bfin_isp1760_device = { |
c6feb768 | 69 | .name = "isp1760", |
3f375690 MH |
70 | .id = 0, |
71 | .dev = { | |
72 | .platform_data = &isp1760_priv, | |
73 | }, | |
74 | .num_resources = ARRAY_SIZE(bfin_isp1760_resources), | |
75 | .resource = bfin_isp1760_resources, | |
0a6304a9 | 76 | }; |
0a6304a9 MH |
77 | #endif |
78 | ||
c6c4d7bb BW |
79 | #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) |
80 | ||
639f6571 | 81 | #include <mach/bf54x-lq043.h> |
c6c4d7bb BW |
82 | |
83 | static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { | |
0e101ec1 SP |
84 | .width = 95, |
85 | .height = 54, | |
c6c4d7bb BW |
86 | .xres = {480, 480, 480}, |
87 | .yres = {272, 272, 272}, | |
88 | .bpp = {24, 24, 24}, | |
89 | .disp = GPIO_PE3, | |
90 | }; | |
91 | ||
92 | static struct resource bf54x_lq043_resources[] = { | |
93 | { | |
94 | .start = IRQ_EPPI0_ERR, | |
95 | .end = IRQ_EPPI0_ERR, | |
96 | .flags = IORESOURCE_IRQ, | |
97 | }, | |
98 | }; | |
99 | ||
100 | static struct platform_device bf54x_lq043_device = { | |
101 | .name = "bf54x-lq043", | |
102 | .id = -1, | |
103 | .num_resources = ARRAY_SIZE(bf54x_lq043_resources), | |
104 | .resource = bf54x_lq043_resources, | |
105 | .dev = { | |
106 | .platform_data = &bf54x_lq043_data, | |
107 | }, | |
108 | }; | |
109 | #endif | |
110 | ||
111 | #if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE) | |
8f740ef3 | 112 | static const unsigned int bf548_keymap[] = { |
c6c4d7bb BW |
113 | KEYVAL(0, 0, KEY_ENTER), |
114 | KEYVAL(0, 1, KEY_HELP), | |
115 | KEYVAL(0, 2, KEY_0), | |
116 | KEYVAL(0, 3, KEY_BACKSPACE), | |
117 | KEYVAL(1, 0, KEY_TAB), | |
118 | KEYVAL(1, 1, KEY_9), | |
119 | KEYVAL(1, 2, KEY_8), | |
120 | KEYVAL(1, 3, KEY_7), | |
121 | KEYVAL(2, 0, KEY_DOWN), | |
122 | KEYVAL(2, 1, KEY_6), | |
123 | KEYVAL(2, 2, KEY_5), | |
124 | KEYVAL(2, 3, KEY_4), | |
125 | KEYVAL(3, 0, KEY_UP), | |
126 | KEYVAL(3, 1, KEY_3), | |
127 | KEYVAL(3, 2, KEY_2), | |
128 | KEYVAL(3, 3, KEY_1), | |
129 | }; | |
130 | ||
131 | static struct bfin_kpad_platform_data bf54x_kpad_data = { | |
132 | .rows = 4, | |
133 | .cols = 4, | |
8f740ef3 MH |
134 | .keymap = bf548_keymap, |
135 | .keymapsize = ARRAY_SIZE(bf548_keymap), | |
c6c4d7bb BW |
136 | .repeat = 0, |
137 | .debounce_time = 5000, /* ns (5ms) */ | |
138 | .coldrive_time = 1000, /* ns (1ms) */ | |
139 | .keyup_test_interval = 50, /* ms (50ms) */ | |
140 | }; | |
141 | ||
142 | static struct resource bf54x_kpad_resources[] = { | |
143 | { | |
144 | .start = IRQ_KEY, | |
145 | .end = IRQ_KEY, | |
146 | .flags = IORESOURCE_IRQ, | |
147 | }, | |
148 | }; | |
149 | ||
150 | static struct platform_device bf54x_kpad_device = { | |
151 | .name = "bf54x-keys", | |
152 | .id = -1, | |
153 | .num_resources = ARRAY_SIZE(bf54x_kpad_resources), | |
154 | .resource = bf54x_kpad_resources, | |
155 | .dev = { | |
156 | .platform_data = &bf54x_kpad_data, | |
157 | }, | |
158 | }; | |
159 | #endif | |
160 | ||
adfc0467 | 161 | #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) |
aca5e4aa MH |
162 | #include <asm/bfin_rotary.h> |
163 | ||
164 | static struct bfin_rotary_platform_data bfin_rotary_data = { | |
165 | /*.rotary_up_key = KEY_UP,*/ | |
166 | /*.rotary_down_key = KEY_DOWN,*/ | |
167 | .rotary_rel_code = REL_WHEEL, | |
168 | .rotary_button_key = KEY_ENTER, | |
169 | .debounce = 10, /* 0..17 */ | |
170 | .mode = ROT_QUAD_ENC | ROT_DEBE, | |
5b8163a3 | 171 | .pm_wakeup = 1, |
aca5e4aa MH |
172 | }; |
173 | ||
174 | static struct resource bfin_rotary_resources[] = { | |
175 | { | |
176 | .start = IRQ_CNT, | |
177 | .end = IRQ_CNT, | |
178 | .flags = IORESOURCE_IRQ, | |
179 | }, | |
180 | }; | |
181 | ||
182 | static struct platform_device bfin_rotary_device = { | |
183 | .name = "bfin-rotary", | |
184 | .id = -1, | |
185 | .num_resources = ARRAY_SIZE(bfin_rotary_resources), | |
186 | .resource = bfin_rotary_resources, | |
187 | .dev = { | |
188 | .platform_data = &bfin_rotary_data, | |
189 | }, | |
190 | }; | |
191 | #endif | |
192 | ||
ffc4d8bc | 193 | #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE) |
57af8edf | 194 | #include <linux/input/adxl34x.h> |
ffc4d8bc MH |
195 | static const struct adxl34x_platform_data adxl34x_info = { |
196 | .x_axis_offset = 0, | |
197 | .y_axis_offset = 0, | |
198 | .z_axis_offset = 0, | |
199 | .tap_threshold = 0x31, | |
200 | .tap_duration = 0x10, | |
201 | .tap_latency = 0x60, | |
202 | .tap_window = 0xF0, | |
203 | .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, | |
204 | .act_axis_control = 0xFF, | |
205 | .activity_threshold = 5, | |
206 | .inactivity_threshold = 3, | |
207 | .inactivity_time = 4, | |
208 | .free_fall_threshold = 0x7, | |
209 | .free_fall_time = 0x20, | |
210 | .data_rate = 0x8, | |
211 | .data_range = ADXL_FULL_RES, | |
212 | ||
213 | .ev_type = EV_ABS, | |
214 | .ev_code_x = ABS_X, /* EV_REL */ | |
215 | .ev_code_y = ABS_Y, /* EV_REL */ | |
216 | .ev_code_z = ABS_Z, /* EV_REL */ | |
217 | ||
57af8edf | 218 | .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ |
ffc4d8bc MH |
219 | |
220 | /* .ev_code_ff = KEY_F,*/ /* EV_KEY */ | |
221 | /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ | |
222 | .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, | |
223 | .fifo_mode = ADXL_FIFO_STREAM, | |
5db4036b MH |
224 | .orientation_enable = ADXL_EN_ORIENTATION_3D, |
225 | .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8, | |
226 | .divisor_length = ADXL_LP_FILTER_DIVISOR_16, | |
227 | /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */ | |
228 | .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C}, | |
ffc4d8bc MH |
229 | }; |
230 | #endif | |
231 | ||
24a07a12 RH |
232 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
233 | static struct platform_device rtc_device = { | |
234 | .name = "rtc-bfin", | |
235 | .id = -1, | |
236 | }; | |
237 | #endif | |
238 | ||
239 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
24a07a12 | 240 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
6bd1fbea | 241 | static struct resource bfin_uart0_resources[] = { |
24a07a12 | 242 | { |
6bd1fbea SZ |
243 | .start = UART0_DLL, |
244 | .end = UART0_RBR+2, | |
24a07a12 RH |
245 | .flags = IORESOURCE_MEM, |
246 | }, | |
edb0a640 SZ |
247 | { |
248 | .start = IRQ_UART0_TX, | |
249 | .end = IRQ_UART0_TX, | |
250 | .flags = IORESOURCE_IRQ, | |
251 | }, | |
6bd1fbea SZ |
252 | { |
253 | .start = IRQ_UART0_RX, | |
edb0a640 | 254 | .end = IRQ_UART0_RX, |
6bd1fbea SZ |
255 | .flags = IORESOURCE_IRQ, |
256 | }, | |
257 | { | |
258 | .start = IRQ_UART0_ERROR, | |
259 | .end = IRQ_UART0_ERROR, | |
260 | .flags = IORESOURCE_IRQ, | |
261 | }, | |
262 | { | |
263 | .start = CH_UART0_TX, | |
264 | .end = CH_UART0_TX, | |
265 | .flags = IORESOURCE_DMA, | |
266 | }, | |
267 | { | |
268 | .start = CH_UART0_RX, | |
269 | .end = CH_UART0_RX, | |
270 | .flags = IORESOURCE_DMA, | |
271 | }, | |
272 | }; | |
273 | ||
a8b19886 | 274 | static unsigned short bfin_uart0_peripherals[] = { |
6bd1fbea SZ |
275 | P_UART0_TX, P_UART0_RX, 0 |
276 | }; | |
277 | ||
278 | static struct platform_device bfin_uart0_device = { | |
279 | .name = "bfin-uart", | |
280 | .id = 0, | |
281 | .num_resources = ARRAY_SIZE(bfin_uart0_resources), | |
282 | .resource = bfin_uart0_resources, | |
283 | .dev = { | |
284 | .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ | |
285 | }, | |
286 | }; | |
24a07a12 RH |
287 | #endif |
288 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
6bd1fbea | 289 | static struct resource bfin_uart1_resources[] = { |
24a07a12 | 290 | { |
6bd1fbea SZ |
291 | .start = UART1_DLL, |
292 | .end = UART1_RBR+2, | |
24a07a12 RH |
293 | .flags = IORESOURCE_MEM, |
294 | }, | |
edb0a640 SZ |
295 | { |
296 | .start = IRQ_UART1_TX, | |
297 | .end = IRQ_UART1_TX, | |
298 | .flags = IORESOURCE_IRQ, | |
299 | }, | |
6bd1fbea SZ |
300 | { |
301 | .start = IRQ_UART1_RX, | |
edb0a640 | 302 | .end = IRQ_UART1_RX, |
6bd1fbea SZ |
303 | .flags = IORESOURCE_IRQ, |
304 | }, | |
305 | { | |
306 | .start = IRQ_UART1_ERROR, | |
307 | .end = IRQ_UART1_ERROR, | |
308 | .flags = IORESOURCE_IRQ, | |
309 | }, | |
310 | { | |
311 | .start = CH_UART1_TX, | |
312 | .end = CH_UART1_TX, | |
313 | .flags = IORESOURCE_DMA, | |
314 | }, | |
315 | { | |
316 | .start = CH_UART1_RX, | |
317 | .end = CH_UART1_RX, | |
318 | .flags = IORESOURCE_DMA, | |
319 | }, | |
320 | #ifdef CONFIG_BFIN_UART1_CTSRTS | |
321 | { /* CTS pin -- 0 means not supported */ | |
322 | .start = GPIO_PE10, | |
323 | .end = GPIO_PE10, | |
324 | .flags = IORESOURCE_IO, | |
325 | }, | |
326 | { /* RTS pin -- 0 means not supported */ | |
327 | .start = GPIO_PE9, | |
328 | .end = GPIO_PE9, | |
329 | .flags = IORESOURCE_IO, | |
330 | }, | |
331 | #endif | |
332 | }; | |
333 | ||
a8b19886 | 334 | static unsigned short bfin_uart1_peripherals[] = { |
6bd1fbea SZ |
335 | P_UART1_TX, P_UART1_RX, |
336 | #ifdef CONFIG_BFIN_UART1_CTSRTS | |
337 | P_UART1_RTS, P_UART1_CTS, | |
338 | #endif | |
339 | 0 | |
340 | }; | |
341 | ||
342 | static struct platform_device bfin_uart1_device = { | |
343 | .name = "bfin-uart", | |
344 | .id = 1, | |
345 | .num_resources = ARRAY_SIZE(bfin_uart1_resources), | |
346 | .resource = bfin_uart1_resources, | |
347 | .dev = { | |
348 | .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ | |
349 | }, | |
350 | }; | |
24a07a12 RH |
351 | #endif |
352 | #ifdef CONFIG_SERIAL_BFIN_UART2 | |
6bd1fbea | 353 | static struct resource bfin_uart2_resources[] = { |
24a07a12 | 354 | { |
6bd1fbea SZ |
355 | .start = UART2_DLL, |
356 | .end = UART2_RBR+2, | |
24a07a12 RH |
357 | .flags = IORESOURCE_MEM, |
358 | }, | |
edb0a640 SZ |
359 | { |
360 | .start = IRQ_UART2_TX, | |
361 | .end = IRQ_UART2_TX, | |
362 | .flags = IORESOURCE_IRQ, | |
363 | }, | |
6bd1fbea SZ |
364 | { |
365 | .start = IRQ_UART2_RX, | |
edb0a640 | 366 | .end = IRQ_UART2_RX, |
6bd1fbea SZ |
367 | .flags = IORESOURCE_IRQ, |
368 | }, | |
369 | { | |
370 | .start = IRQ_UART2_ERROR, | |
371 | .end = IRQ_UART2_ERROR, | |
372 | .flags = IORESOURCE_IRQ, | |
373 | }, | |
374 | { | |
375 | .start = CH_UART2_TX, | |
376 | .end = CH_UART2_TX, | |
377 | .flags = IORESOURCE_DMA, | |
378 | }, | |
379 | { | |
380 | .start = CH_UART2_RX, | |
381 | .end = CH_UART2_RX, | |
382 | .flags = IORESOURCE_DMA, | |
383 | }, | |
384 | }; | |
385 | ||
a8b19886 | 386 | static unsigned short bfin_uart2_peripherals[] = { |
6bd1fbea SZ |
387 | P_UART2_TX, P_UART2_RX, 0 |
388 | }; | |
389 | ||
390 | static struct platform_device bfin_uart2_device = { | |
391 | .name = "bfin-uart", | |
392 | .id = 2, | |
393 | .num_resources = ARRAY_SIZE(bfin_uart2_resources), | |
394 | .resource = bfin_uart2_resources, | |
395 | .dev = { | |
396 | .platform_data = &bfin_uart2_peripherals, /* Passed to driver */ | |
397 | }, | |
398 | }; | |
24a07a12 RH |
399 | #endif |
400 | #ifdef CONFIG_SERIAL_BFIN_UART3 | |
6bd1fbea | 401 | static struct resource bfin_uart3_resources[] = { |
24a07a12 | 402 | { |
6bd1fbea SZ |
403 | .start = UART3_DLL, |
404 | .end = UART3_RBR+2, | |
cc2e16bd | 405 | .flags = IORESOURCE_MEM, |
24a07a12 | 406 | }, |
edb0a640 SZ |
407 | { |
408 | .start = IRQ_UART3_TX, | |
409 | .end = IRQ_UART3_TX, | |
410 | .flags = IORESOURCE_IRQ, | |
411 | }, | |
6bd1fbea SZ |
412 | { |
413 | .start = IRQ_UART3_RX, | |
edb0a640 | 414 | .end = IRQ_UART3_RX, |
6bd1fbea SZ |
415 | .flags = IORESOURCE_IRQ, |
416 | }, | |
417 | { | |
418 | .start = IRQ_UART3_ERROR, | |
419 | .end = IRQ_UART3_ERROR, | |
420 | .flags = IORESOURCE_IRQ, | |
421 | }, | |
422 | { | |
423 | .start = CH_UART3_TX, | |
424 | .end = CH_UART3_TX, | |
425 | .flags = IORESOURCE_DMA, | |
426 | }, | |
427 | { | |
428 | .start = CH_UART3_RX, | |
429 | .end = CH_UART3_RX, | |
430 | .flags = IORESOURCE_DMA, | |
431 | }, | |
432 | #ifdef CONFIG_BFIN_UART3_CTSRTS | |
433 | { /* CTS pin -- 0 means not supported */ | |
434 | .start = GPIO_PB3, | |
435 | .end = GPIO_PB3, | |
436 | .flags = IORESOURCE_IO, | |
437 | }, | |
438 | { /* RTS pin -- 0 means not supported */ | |
439 | .start = GPIO_PB2, | |
440 | .end = GPIO_PB2, | |
441 | .flags = IORESOURCE_IO, | |
442 | }, | |
24a07a12 RH |
443 | #endif |
444 | }; | |
445 | ||
a8b19886 | 446 | static unsigned short bfin_uart3_peripherals[] = { |
6bd1fbea SZ |
447 | P_UART3_TX, P_UART3_RX, |
448 | #ifdef CONFIG_BFIN_UART3_CTSRTS | |
449 | P_UART3_RTS, P_UART3_CTS, | |
450 | #endif | |
451 | 0 | |
452 | }; | |
453 | ||
454 | static struct platform_device bfin_uart3_device = { | |
24a07a12 | 455 | .name = "bfin-uart", |
6bd1fbea SZ |
456 | .id = 3, |
457 | .num_resources = ARRAY_SIZE(bfin_uart3_resources), | |
458 | .resource = bfin_uart3_resources, | |
459 | .dev = { | |
460 | .platform_data = &bfin_uart3_peripherals, /* Passed to driver */ | |
461 | }, | |
24a07a12 RH |
462 | }; |
463 | #endif | |
6bd1fbea | 464 | #endif |
24a07a12 | 465 | |
5be36d22 | 466 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
5be36d22 | 467 | #ifdef CONFIG_BFIN_SIR0 |
42bd8bcb | 468 | static struct resource bfin_sir0_resources[] = { |
5be36d22 GY |
469 | { |
470 | .start = 0xFFC00400, | |
471 | .end = 0xFFC004FF, | |
472 | .flags = IORESOURCE_MEM, | |
473 | }, | |
42bd8bcb GY |
474 | { |
475 | .start = IRQ_UART0_RX, | |
476 | .end = IRQ_UART0_RX+1, | |
477 | .flags = IORESOURCE_IRQ, | |
478 | }, | |
479 | { | |
480 | .start = CH_UART0_RX, | |
481 | .end = CH_UART0_RX+1, | |
482 | .flags = IORESOURCE_DMA, | |
483 | }, | |
484 | }; | |
485 | static struct platform_device bfin_sir0_device = { | |
486 | .name = "bfin_sir", | |
487 | .id = 0, | |
488 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | |
489 | .resource = bfin_sir0_resources, | |
490 | }; | |
5be36d22 GY |
491 | #endif |
492 | #ifdef CONFIG_BFIN_SIR1 | |
42bd8bcb | 493 | static struct resource bfin_sir1_resources[] = { |
5be36d22 GY |
494 | { |
495 | .start = 0xFFC02000, | |
496 | .end = 0xFFC020FF, | |
497 | .flags = IORESOURCE_MEM, | |
498 | }, | |
42bd8bcb GY |
499 | { |
500 | .start = IRQ_UART1_RX, | |
501 | .end = IRQ_UART1_RX+1, | |
502 | .flags = IORESOURCE_IRQ, | |
503 | }, | |
504 | { | |
505 | .start = CH_UART1_RX, | |
506 | .end = CH_UART1_RX+1, | |
507 | .flags = IORESOURCE_DMA, | |
508 | }, | |
509 | }; | |
510 | static struct platform_device bfin_sir1_device = { | |
511 | .name = "bfin_sir", | |
512 | .id = 1, | |
513 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), | |
514 | .resource = bfin_sir1_resources, | |
515 | }; | |
5be36d22 GY |
516 | #endif |
517 | #ifdef CONFIG_BFIN_SIR2 | |
42bd8bcb | 518 | static struct resource bfin_sir2_resources[] = { |
5be36d22 GY |
519 | { |
520 | .start = 0xFFC02100, | |
521 | .end = 0xFFC021FF, | |
522 | .flags = IORESOURCE_MEM, | |
523 | }, | |
42bd8bcb GY |
524 | { |
525 | .start = IRQ_UART2_RX, | |
526 | .end = IRQ_UART2_RX+1, | |
527 | .flags = IORESOURCE_IRQ, | |
528 | }, | |
529 | { | |
530 | .start = CH_UART2_RX, | |
531 | .end = CH_UART2_RX+1, | |
532 | .flags = IORESOURCE_DMA, | |
533 | }, | |
534 | }; | |
535 | static struct platform_device bfin_sir2_device = { | |
536 | .name = "bfin_sir", | |
537 | .id = 2, | |
538 | .num_resources = ARRAY_SIZE(bfin_sir2_resources), | |
539 | .resource = bfin_sir2_resources, | |
540 | }; | |
5be36d22 GY |
541 | #endif |
542 | #ifdef CONFIG_BFIN_SIR3 | |
42bd8bcb | 543 | static struct resource bfin_sir3_resources[] = { |
5be36d22 GY |
544 | { |
545 | .start = 0xFFC03100, | |
546 | .end = 0xFFC031FF, | |
547 | .flags = IORESOURCE_MEM, | |
548 | }, | |
42bd8bcb GY |
549 | { |
550 | .start = IRQ_UART3_RX, | |
551 | .end = IRQ_UART3_RX+1, | |
552 | .flags = IORESOURCE_IRQ, | |
553 | }, | |
554 | { | |
555 | .start = CH_UART3_RX, | |
556 | .end = CH_UART3_RX+1, | |
557 | .flags = IORESOURCE_DMA, | |
558 | }, | |
5be36d22 | 559 | }; |
42bd8bcb | 560 | static struct platform_device bfin_sir3_device = { |
5be36d22 | 561 | .name = "bfin_sir", |
42bd8bcb GY |
562 | .id = 3, |
563 | .num_resources = ARRAY_SIZE(bfin_sir3_resources), | |
564 | .resource = bfin_sir3_resources, | |
5be36d22 GY |
565 | }; |
566 | #endif | |
42bd8bcb | 567 | #endif |
5be36d22 | 568 | |
c6c4d7bb | 569 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) |
7a8b71db MF |
570 | #include <linux/smsc911x.h> |
571 | ||
c6c4d7bb BW |
572 | static struct resource smsc911x_resources[] = { |
573 | { | |
574 | .name = "smsc911x-memory", | |
575 | .start = 0x24000000, | |
576 | .end = 0x24000000 + 0xFF, | |
577 | .flags = IORESOURCE_MEM, | |
578 | }, | |
579 | { | |
580 | .start = IRQ_PE8, | |
581 | .end = IRQ_PE8, | |
582 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | |
583 | }, | |
584 | }; | |
7a8b71db MF |
585 | |
586 | static struct smsc911x_platform_config smsc911x_config = { | |
587 | .flags = SMSC911X_USE_32BIT, | |
588 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | |
589 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, | |
590 | .phy_interface = PHY_INTERFACE_MODE_MII, | |
591 | }; | |
592 | ||
c6c4d7bb BW |
593 | static struct platform_device smsc911x_device = { |
594 | .name = "smsc911x", | |
595 | .id = 0, | |
596 | .num_resources = ARRAY_SIZE(smsc911x_resources), | |
597 | .resource = smsc911x_resources, | |
7a8b71db MF |
598 | .dev = { |
599 | .platform_data = &smsc911x_config, | |
600 | }, | |
c6c4d7bb BW |
601 | }; |
602 | #endif | |
603 | ||
c6c4d7bb BW |
604 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) |
605 | static struct resource musb_resources[] = { | |
606 | [0] = { | |
607 | .start = 0xFFC03C00, | |
608 | .end = 0xFFC040FF, | |
609 | .flags = IORESOURCE_MEM, | |
610 | }, | |
611 | [1] = { /* general IRQ */ | |
612 | .start = IRQ_USB_INT0, | |
613 | .end = IRQ_USB_INT0, | |
614 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
fcf173e4 | 615 | .name = "mc" |
c6c4d7bb BW |
616 | }, |
617 | [2] = { /* DMA IRQ */ | |
618 | .start = IRQ_USB_DMA, | |
619 | .end = IRQ_USB_DMA, | |
620 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
fcf173e4 | 621 | .name = "dma" |
c6c4d7bb BW |
622 | }, |
623 | }; | |
624 | ||
50041acb BW |
625 | static struct musb_hdrc_config musb_config = { |
626 | .multipoint = 0, | |
627 | .dyn_fifo = 0, | |
628 | .soft_con = 1, | |
629 | .dma = 1, | |
fea05dac BW |
630 | .num_eps = 8, |
631 | .dma_channels = 8, | |
50041acb | 632 | .gpio_vrsel = GPIO_PE7, |
85eb0e4b CC |
633 | /* Some custom boards need to be active low, just set it to "0" |
634 | * if it is the case. | |
635 | */ | |
636 | .gpio_vrsel_active = 1, | |
759a3f3f | 637 | .clkin = 24, /* musb CLKIN in MHZ */ |
50041acb BW |
638 | }; |
639 | ||
c6c4d7bb | 640 | static struct musb_hdrc_platform_data musb_plat = { |
b091694b | 641 | #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC) |
c6c4d7bb | 642 | .mode = MUSB_OTG, |
b091694b | 643 | #elif defined(CONFIG_USB_MUSB_HDRC) |
c6c4d7bb | 644 | .mode = MUSB_HOST, |
2935077e | 645 | #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) |
c6c4d7bb BW |
646 | .mode = MUSB_PERIPHERAL, |
647 | #endif | |
50041acb | 648 | .config = &musb_config, |
c6c4d7bb BW |
649 | }; |
650 | ||
651 | static u64 musb_dmamask = ~(u32)0; | |
652 | ||
653 | static struct platform_device musb_device = { | |
9cb0308e | 654 | .name = "musb-blackfin", |
c6c4d7bb BW |
655 | .id = 0, |
656 | .dev = { | |
657 | .dma_mask = &musb_dmamask, | |
658 | .coherent_dma_mask = 0xffffffff, | |
659 | .platform_data = &musb_plat, | |
660 | }, | |
661 | .num_resources = ARRAY_SIZE(musb_resources), | |
662 | .resource = musb_resources, | |
663 | }; | |
664 | #endif | |
665 | ||
df5de261 SZ |
666 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
667 | #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART | |
668 | static struct resource bfin_sport0_uart_resources[] = { | |
669 | { | |
670 | .start = SPORT0_TCR1, | |
671 | .end = SPORT0_MRCS3+4, | |
672 | .flags = IORESOURCE_MEM, | |
673 | }, | |
674 | { | |
675 | .start = IRQ_SPORT0_RX, | |
676 | .end = IRQ_SPORT0_RX+1, | |
677 | .flags = IORESOURCE_IRQ, | |
678 | }, | |
679 | { | |
680 | .start = IRQ_SPORT0_ERROR, | |
681 | .end = IRQ_SPORT0_ERROR, | |
682 | .flags = IORESOURCE_IRQ, | |
683 | }, | |
684 | }; | |
685 | ||
a8b19886 | 686 | static unsigned short bfin_sport0_peripherals[] = { |
df5de261 | 687 | P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, |
e54b6730 | 688 | P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 |
df5de261 SZ |
689 | }; |
690 | ||
691 | static struct platform_device bfin_sport0_uart_device = { | |
692 | .name = "bfin-sport-uart", | |
693 | .id = 0, | |
694 | .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), | |
695 | .resource = bfin_sport0_uart_resources, | |
696 | .dev = { | |
697 | .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ | |
698 | }, | |
699 | }; | |
700 | #endif | |
701 | #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART | |
702 | static struct resource bfin_sport1_uart_resources[] = { | |
703 | { | |
704 | .start = SPORT1_TCR1, | |
705 | .end = SPORT1_MRCS3+4, | |
706 | .flags = IORESOURCE_MEM, | |
707 | }, | |
708 | { | |
709 | .start = IRQ_SPORT1_RX, | |
710 | .end = IRQ_SPORT1_RX+1, | |
711 | .flags = IORESOURCE_IRQ, | |
712 | }, | |
713 | { | |
714 | .start = IRQ_SPORT1_ERROR, | |
715 | .end = IRQ_SPORT1_ERROR, | |
716 | .flags = IORESOURCE_IRQ, | |
717 | }, | |
718 | }; | |
719 | ||
a8b19886 | 720 | static unsigned short bfin_sport1_peripherals[] = { |
df5de261 | 721 | P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, |
e54b6730 | 722 | P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 |
df5de261 SZ |
723 | }; |
724 | ||
725 | static struct platform_device bfin_sport1_uart_device = { | |
726 | .name = "bfin-sport-uart", | |
727 | .id = 1, | |
728 | .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), | |
729 | .resource = bfin_sport1_uart_resources, | |
730 | .dev = { | |
731 | .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ | |
732 | }, | |
733 | }; | |
734 | #endif | |
735 | #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART | |
736 | static struct resource bfin_sport2_uart_resources[] = { | |
737 | { | |
738 | .start = SPORT2_TCR1, | |
739 | .end = SPORT2_MRCS3+4, | |
740 | .flags = IORESOURCE_MEM, | |
741 | }, | |
742 | { | |
743 | .start = IRQ_SPORT2_RX, | |
744 | .end = IRQ_SPORT2_RX+1, | |
745 | .flags = IORESOURCE_IRQ, | |
746 | }, | |
747 | { | |
748 | .start = IRQ_SPORT2_ERROR, | |
749 | .end = IRQ_SPORT2_ERROR, | |
750 | .flags = IORESOURCE_IRQ, | |
751 | }, | |
752 | }; | |
753 | ||
a8b19886 | 754 | static unsigned short bfin_sport2_peripherals[] = { |
df5de261 SZ |
755 | P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, |
756 | P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 | |
757 | }; | |
758 | ||
759 | static struct platform_device bfin_sport2_uart_device = { | |
760 | .name = "bfin-sport-uart", | |
761 | .id = 2, | |
762 | .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources), | |
763 | .resource = bfin_sport2_uart_resources, | |
764 | .dev = { | |
765 | .platform_data = &bfin_sport2_peripherals, /* Passed to driver */ | |
766 | }, | |
767 | }; | |
768 | #endif | |
769 | #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART | |
770 | static struct resource bfin_sport3_uart_resources[] = { | |
771 | { | |
772 | .start = SPORT3_TCR1, | |
773 | .end = SPORT3_MRCS3+4, | |
774 | .flags = IORESOURCE_MEM, | |
775 | }, | |
776 | { | |
777 | .start = IRQ_SPORT3_RX, | |
778 | .end = IRQ_SPORT3_RX+1, | |
779 | .flags = IORESOURCE_IRQ, | |
780 | }, | |
781 | { | |
782 | .start = IRQ_SPORT3_ERROR, | |
783 | .end = IRQ_SPORT3_ERROR, | |
784 | .flags = IORESOURCE_IRQ, | |
785 | }, | |
786 | }; | |
787 | ||
a8b19886 | 788 | static unsigned short bfin_sport3_peripherals[] = { |
df5de261 SZ |
789 | P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, |
790 | P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 | |
791 | }; | |
792 | ||
793 | static struct platform_device bfin_sport3_uart_device = { | |
794 | .name = "bfin-sport-uart", | |
795 | .id = 3, | |
796 | .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources), | |
797 | .resource = bfin_sport3_uart_resources, | |
798 | .dev = { | |
799 | .platform_data = &bfin_sport3_peripherals, /* Passed to driver */ | |
800 | }, | |
801 | }; | |
802 | #endif | |
803 | #endif | |
804 | ||
706a01b1 | 805 | #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) |
4c131c8c AW |
806 | |
807 | static unsigned short bfin_can0_peripherals[] = { | |
706a01b1 BS |
808 | P_CAN0_RX, P_CAN0_TX, 0 |
809 | }; | |
810 | ||
4c131c8c | 811 | static struct resource bfin_can0_resources[] = { |
706a01b1 BS |
812 | { |
813 | .start = 0xFFC02A00, | |
814 | .end = 0xFFC02FFF, | |
815 | .flags = IORESOURCE_MEM, | |
816 | }, | |
817 | { | |
818 | .start = IRQ_CAN0_RX, | |
819 | .end = IRQ_CAN0_RX, | |
820 | .flags = IORESOURCE_IRQ, | |
821 | }, | |
822 | { | |
823 | .start = IRQ_CAN0_TX, | |
824 | .end = IRQ_CAN0_TX, | |
825 | .flags = IORESOURCE_IRQ, | |
826 | }, | |
827 | { | |
828 | .start = IRQ_CAN0_ERROR, | |
829 | .end = IRQ_CAN0_ERROR, | |
830 | .flags = IORESOURCE_IRQ, | |
831 | }, | |
832 | }; | |
833 | ||
4c131c8c | 834 | static struct platform_device bfin_can0_device = { |
706a01b1 | 835 | .name = "bfin_can", |
4c131c8c AW |
836 | .id = 0, |
837 | .num_resources = ARRAY_SIZE(bfin_can0_resources), | |
838 | .resource = bfin_can0_resources, | |
706a01b1 | 839 | .dev = { |
4c131c8c | 840 | .platform_data = &bfin_can0_peripherals, /* Passed to driver */ |
706a01b1 BS |
841 | }, |
842 | }; | |
4c131c8c AW |
843 | |
844 | static unsigned short bfin_can1_peripherals[] = { | |
845 | P_CAN1_RX, P_CAN1_TX, 0 | |
846 | }; | |
847 | ||
848 | static struct resource bfin_can1_resources[] = { | |
849 | { | |
850 | .start = 0xFFC03200, | |
851 | .end = 0xFFC037FF, | |
852 | .flags = IORESOURCE_MEM, | |
853 | }, | |
854 | { | |
855 | .start = IRQ_CAN1_RX, | |
856 | .end = IRQ_CAN1_RX, | |
857 | .flags = IORESOURCE_IRQ, | |
858 | }, | |
859 | { | |
860 | .start = IRQ_CAN1_TX, | |
861 | .end = IRQ_CAN1_TX, | |
862 | .flags = IORESOURCE_IRQ, | |
863 | }, | |
864 | { | |
865 | .start = IRQ_CAN1_ERROR, | |
866 | .end = IRQ_CAN1_ERROR, | |
867 | .flags = IORESOURCE_IRQ, | |
868 | }, | |
869 | }; | |
870 | ||
871 | static struct platform_device bfin_can1_device = { | |
872 | .name = "bfin_can", | |
873 | .id = 1, | |
874 | .num_resources = ARRAY_SIZE(bfin_can1_resources), | |
875 | .resource = bfin_can1_resources, | |
876 | .dev = { | |
877 | .platform_data = &bfin_can1_peripherals, /* Passed to driver */ | |
878 | }, | |
879 | }; | |
880 | ||
706a01b1 BS |
881 | #endif |
882 | ||
c6c4d7bb BW |
883 | #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) |
884 | static struct resource bfin_atapi_resources[] = { | |
885 | { | |
886 | .start = 0xFFC03800, | |
887 | .end = 0xFFC0386F, | |
888 | .flags = IORESOURCE_MEM, | |
889 | }, | |
890 | { | |
891 | .start = IRQ_ATAPI_ERR, | |
892 | .end = IRQ_ATAPI_ERR, | |
893 | .flags = IORESOURCE_IRQ, | |
894 | }, | |
895 | }; | |
896 | ||
897 | static struct platform_device bfin_atapi_device = { | |
898 | .name = "pata-bf54x", | |
899 | .id = -1, | |
900 | .num_resources = ARRAY_SIZE(bfin_atapi_resources), | |
901 | .resource = bfin_atapi_resources, | |
902 | }; | |
903 | #endif | |
904 | ||
905 | #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) | |
906 | static struct mtd_partition partition_info[] = { | |
907 | { | |
73775b89 | 908 | .name = "bootloader(nand)", |
c6c4d7bb | 909 | .offset = 0, |
73775b89 MF |
910 | .size = 0x80000, |
911 | }, { | |
912 | .name = "linux kernel(nand)", | |
913 | .offset = MTDPART_OFS_APPEND, | |
f4585a08 | 914 | .size = 4 * 1024 * 1024, |
c6c4d7bb BW |
915 | }, |
916 | { | |
aa582977 | 917 | .name = "file system(nand)", |
edf05641 MF |
918 | .offset = MTDPART_OFS_APPEND, |
919 | .size = MTDPART_SIZ_FULL, | |
c6c4d7bb BW |
920 | }, |
921 | }; | |
922 | ||
923 | static struct bf5xx_nand_platform bf5xx_nand_platform = { | |
c6c4d7bb BW |
924 | .data_width = NFC_NWIDTH_8, |
925 | .partitions = partition_info, | |
926 | .nr_partitions = ARRAY_SIZE(partition_info), | |
927 | .rd_dly = 3, | |
928 | .wr_dly = 3, | |
929 | }; | |
930 | ||
931 | static struct resource bf5xx_nand_resources[] = { | |
932 | { | |
933 | .start = 0xFFC03B00, | |
934 | .end = 0xFFC03B4F, | |
935 | .flags = IORESOURCE_MEM, | |
936 | }, | |
937 | { | |
938 | .start = CH_NFC, | |
939 | .end = CH_NFC, | |
940 | .flags = IORESOURCE_IRQ, | |
941 | }, | |
942 | }; | |
943 | ||
944 | static struct platform_device bf5xx_nand_device = { | |
945 | .name = "bf5xx-nand", | |
946 | .id = 0, | |
947 | .num_resources = ARRAY_SIZE(bf5xx_nand_resources), | |
948 | .resource = bf5xx_nand_resources, | |
949 | .dev = { | |
950 | .platform_data = &bf5xx_nand_platform, | |
951 | }, | |
952 | }; | |
953 | #endif | |
954 | ||
3d7e6cf8 | 955 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) |
501674a5 CC |
956 | |
957 | static struct bfin_sd_host bfin_sdh_data = { | |
958 | .dma_chan = CH_SDH, | |
959 | .irq_int0 = IRQ_SDH_MASK0, | |
960 | .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0}, | |
961 | }; | |
962 | ||
c6c4d7bb BW |
963 | static struct platform_device bf54x_sdh_device = { |
964 | .name = "bfin-sdh", | |
965 | .id = 0, | |
501674a5 CC |
966 | .dev = { |
967 | .platform_data = &bfin_sdh_data, | |
968 | }, | |
c6c4d7bb BW |
969 | }; |
970 | #endif | |
971 | ||
793dc27b | 972 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
de8c43f2 MF |
973 | static struct mtd_partition ezkit_partitions[] = { |
974 | { | |
aa582977 | 975 | .name = "bootloader(nor)", |
73775b89 | 976 | .size = 0x80000, |
de8c43f2 MF |
977 | .offset = 0, |
978 | }, { | |
aa582977 | 979 | .name = "linux kernel(nor)", |
664d0403 | 980 | .size = 0x400000, |
de8c43f2 MF |
981 | .offset = MTDPART_OFS_APPEND, |
982 | }, { | |
aa582977 | 983 | .name = "file system(nor)", |
56072047 MF |
984 | .size = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4, |
985 | .offset = MTDPART_OFS_APPEND, | |
986 | }, { | |
987 | .name = "config(nor)", | |
988 | .size = 0x8000 * 3, | |
989 | .offset = MTDPART_OFS_APPEND, | |
990 | }, { | |
991 | .name = "u-boot env(nor)", | |
992 | .size = 0x8000, | |
de8c43f2 MF |
993 | .offset = MTDPART_OFS_APPEND, |
994 | } | |
995 | }; | |
996 | ||
997 | static struct physmap_flash_data ezkit_flash_data = { | |
998 | .width = 2, | |
999 | .parts = ezkit_partitions, | |
1000 | .nr_parts = ARRAY_SIZE(ezkit_partitions), | |
1001 | }; | |
1002 | ||
1003 | static struct resource ezkit_flash_resource = { | |
1004 | .start = 0x20000000, | |
664d0403 | 1005 | .end = 0x21ffffff, |
de8c43f2 MF |
1006 | .flags = IORESOURCE_MEM, |
1007 | }; | |
1008 | ||
1009 | static struct platform_device ezkit_flash_device = { | |
1010 | .name = "physmap-flash", | |
1011 | .id = 0, | |
1012 | .dev = { | |
1013 | .platform_data = &ezkit_flash_data, | |
1014 | }, | |
1015 | .num_resources = 1, | |
1016 | .resource = &ezkit_flash_resource, | |
1017 | }; | |
793dc27b | 1018 | #endif |
de8c43f2 | 1019 | |
c6c4d7bb BW |
1020 | #if defined(CONFIG_MTD_M25P80) \ |
1021 | || defined(CONFIG_MTD_M25P80_MODULE) | |
1022 | /* SPI flash chip (m25p16) */ | |
1023 | static struct mtd_partition bfin_spi_flash_partitions[] = { | |
1024 | { | |
aa582977 | 1025 | .name = "bootloader(spi)", |
73775b89 | 1026 | .size = 0x00080000, |
c6c4d7bb BW |
1027 | .offset = 0, |
1028 | .mask_flags = MTD_CAP_ROM | |
1029 | }, { | |
aa582977 | 1030 | .name = "linux kernel(spi)", |
edf05641 MF |
1031 | .size = MTDPART_SIZ_FULL, |
1032 | .offset = MTDPART_OFS_APPEND, | |
c6c4d7bb BW |
1033 | } |
1034 | }; | |
1035 | ||
1036 | static struct flash_platform_data bfin_spi_flash_data = { | |
1037 | .name = "m25p80", | |
1038 | .parts = bfin_spi_flash_partitions, | |
1039 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | |
1040 | .type = "m25p16", | |
1041 | }; | |
1042 | ||
1043 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | |
1044 | .enable_dma = 0, /* use dma transfer with this chip*/ | |
37fa2421 BS |
1045 | }; |
1046 | #endif | |
1047 | ||
c6c4d7bb | 1048 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
c6c4d7bb BW |
1049 | static const struct ad7877_platform_data bfin_ad7877_ts_info = { |
1050 | .model = 7877, | |
1051 | .vref_delay_usecs = 50, /* internal, no capacitor */ | |
1052 | .x_plate_ohms = 419, | |
1053 | .y_plate_ohms = 486, | |
1054 | .pressure_max = 1000, | |
1055 | .pressure_min = 0, | |
1056 | .stopacq_polarity = 1, | |
1057 | .first_conversion_delay = 3, | |
1058 | .acquisition_time = 1, | |
1059 | .averaging = 1, | |
1060 | .pen_down_acc_interval = 1, | |
1061 | }; | |
1062 | #endif | |
1063 | ||
54e4ff4d SZ |
1064 | #ifdef CONFIG_PINCTRL_ADI2 |
1065 | ||
1066 | # define ADI_PINT_DEVNAME "adi-gpio-pint" | |
1067 | # define ADI_GPIO_DEVNAME "adi-gpio" | |
1068 | # define ADI_PINCTRL_DEVNAME "pinctrl-adi2" | |
1069 | ||
1070 | static struct platform_device bfin_pinctrl_device = { | |
1071 | .name = ADI_PINCTRL_DEVNAME, | |
1072 | .id = 0, | |
1073 | }; | |
1074 | ||
1075 | static struct resource bfin_pint0_resources[] = { | |
1076 | { | |
1077 | .start = PINT0_MASK_SET, | |
1078 | .end = PINT0_LATCH + 3, | |
1079 | .flags = IORESOURCE_MEM, | |
1080 | }, | |
1081 | { | |
1082 | .start = IRQ_PINT0, | |
1083 | .end = IRQ_PINT0, | |
1084 | .flags = IORESOURCE_IRQ, | |
1085 | }, | |
1086 | }; | |
1087 | ||
1088 | static struct platform_device bfin_pint0_device = { | |
1089 | .name = ADI_PINT_DEVNAME, | |
1090 | .id = 0, | |
1091 | .num_resources = ARRAY_SIZE(bfin_pint0_resources), | |
1092 | .resource = bfin_pint0_resources, | |
1093 | }; | |
1094 | ||
1095 | static struct resource bfin_pint1_resources[] = { | |
1096 | { | |
1097 | .start = PINT1_MASK_SET, | |
1098 | .end = PINT1_LATCH + 3, | |
1099 | .flags = IORESOURCE_MEM, | |
1100 | }, | |
1101 | { | |
1102 | .start = IRQ_PINT1, | |
1103 | .end = IRQ_PINT1, | |
1104 | .flags = IORESOURCE_IRQ, | |
1105 | }, | |
1106 | }; | |
1107 | ||
1108 | static struct platform_device bfin_pint1_device = { | |
1109 | .name = ADI_PINT_DEVNAME, | |
1110 | .id = 1, | |
1111 | .num_resources = ARRAY_SIZE(bfin_pint1_resources), | |
1112 | .resource = bfin_pint1_resources, | |
1113 | }; | |
1114 | ||
1115 | static struct resource bfin_pint2_resources[] = { | |
1116 | { | |
1117 | .start = PINT2_MASK_SET, | |
1118 | .end = PINT2_LATCH + 3, | |
1119 | .flags = IORESOURCE_MEM, | |
1120 | }, | |
1121 | { | |
1122 | .start = IRQ_PINT2, | |
1123 | .end = IRQ_PINT2, | |
1124 | .flags = IORESOURCE_IRQ, | |
1125 | }, | |
1126 | }; | |
1127 | ||
1128 | static struct platform_device bfin_pint2_device = { | |
1129 | .name = ADI_PINT_DEVNAME, | |
1130 | .id = 2, | |
1131 | .num_resources = ARRAY_SIZE(bfin_pint2_resources), | |
1132 | .resource = bfin_pint2_resources, | |
1133 | }; | |
1134 | ||
1135 | static struct resource bfin_pint3_resources[] = { | |
1136 | { | |
1137 | .start = PINT3_MASK_SET, | |
1138 | .end = PINT3_LATCH + 3, | |
1139 | .flags = IORESOURCE_MEM, | |
1140 | }, | |
1141 | { | |
1142 | .start = IRQ_PINT3, | |
1143 | .end = IRQ_PINT3, | |
1144 | .flags = IORESOURCE_IRQ, | |
1145 | }, | |
1146 | }; | |
1147 | ||
1148 | static struct platform_device bfin_pint3_device = { | |
1149 | .name = ADI_PINT_DEVNAME, | |
1150 | .id = 3, | |
1151 | .num_resources = ARRAY_SIZE(bfin_pint3_resources), | |
1152 | .resource = bfin_pint3_resources, | |
1153 | }; | |
1154 | ||
1155 | static struct resource bfin_gpa_resources[] = { | |
1156 | { | |
1157 | .start = PORTA_FER, | |
1158 | .end = PORTA_MUX + 3, | |
1159 | .flags = IORESOURCE_MEM, | |
1160 | }, | |
1161 | { /* optional */ | |
1162 | .start = IRQ_PA0, | |
1163 | .end = IRQ_PA0, | |
1164 | .flags = IORESOURCE_IRQ, | |
1165 | }, | |
1166 | }; | |
1167 | ||
1168 | static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = { | |
1169 | .port_gpio_base = GPIO_PA0, /* Optional */ | |
1170 | .port_pin_base = GPIO_PA0, | |
1171 | .port_width = GPIO_BANKSIZE, | |
1172 | .pint_id = 0, /* PINT0 */ | |
1173 | .pint_assign = true, /* PINT upper 16 bit */ | |
1174 | .pint_map = 0, /* mapping mask in PINT */ | |
1175 | }; | |
1176 | ||
1177 | static struct platform_device bfin_gpa_device = { | |
1178 | .name = ADI_GPIO_DEVNAME, | |
1179 | .id = 0, | |
1180 | .num_resources = ARRAY_SIZE(bfin_gpa_resources), | |
1181 | .resource = bfin_gpa_resources, | |
1182 | .dev = { | |
1183 | .platform_data = &bfin_gpa_pdata, /* Passed to driver */ | |
1184 | }, | |
1185 | }; | |
1186 | ||
1187 | static struct resource bfin_gpb_resources[] = { | |
1188 | { | |
1189 | .start = PORTB_FER, | |
1190 | .end = PORTB_MUX + 3, | |
1191 | .flags = IORESOURCE_MEM, | |
1192 | }, | |
1193 | { | |
1194 | .start = IRQ_PB0, | |
1195 | .end = IRQ_PB0, | |
1196 | .flags = IORESOURCE_IRQ, | |
1197 | }, | |
1198 | }; | |
1199 | ||
1200 | static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = { | |
1201 | .port_gpio_base = GPIO_PB0, | |
1202 | .port_pin_base = GPIO_PB0, | |
1203 | .port_width = 15, | |
1204 | .pint_id = 0, | |
1205 | .pint_assign = true, | |
1206 | .pint_map = 1, | |
1207 | }; | |
1208 | ||
1209 | static struct platform_device bfin_gpb_device = { | |
1210 | .name = ADI_GPIO_DEVNAME, | |
1211 | .id = 1, | |
1212 | .num_resources = ARRAY_SIZE(bfin_gpb_resources), | |
1213 | .resource = bfin_gpb_resources, | |
1214 | .dev = { | |
1215 | .platform_data = &bfin_gpb_pdata, /* Passed to driver */ | |
1216 | }, | |
1217 | }; | |
1218 | ||
1219 | static struct resource bfin_gpc_resources[] = { | |
1220 | { | |
1221 | .start = PORTC_FER, | |
1222 | .end = PORTC_MUX + 3, | |
1223 | .flags = IORESOURCE_MEM, | |
1224 | }, | |
1225 | { | |
1226 | .start = IRQ_PC0, | |
1227 | .end = IRQ_PC0, | |
1228 | .flags = IORESOURCE_IRQ, | |
1229 | }, | |
1230 | }; | |
1231 | ||
1232 | static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = { | |
1233 | .port_gpio_base = GPIO_PC0, | |
1234 | .port_pin_base = GPIO_PC0, | |
1235 | .port_width = 14, | |
1236 | .pint_id = 2, | |
1237 | .pint_assign = true, | |
1238 | .pint_map = 0, | |
1239 | }; | |
1240 | ||
1241 | static struct platform_device bfin_gpc_device = { | |
1242 | .name = ADI_GPIO_DEVNAME, | |
1243 | .id = 2, | |
1244 | .num_resources = ARRAY_SIZE(bfin_gpc_resources), | |
1245 | .resource = bfin_gpc_resources, | |
1246 | .dev = { | |
1247 | .platform_data = &bfin_gpc_pdata, /* Passed to driver */ | |
1248 | }, | |
1249 | }; | |
1250 | ||
1251 | static struct resource bfin_gpd_resources[] = { | |
1252 | { | |
1253 | .start = PORTD_FER, | |
1254 | .end = PORTD_MUX + 3, | |
1255 | .flags = IORESOURCE_MEM, | |
1256 | }, | |
1257 | { | |
1258 | .start = IRQ_PD0, | |
1259 | .end = IRQ_PD0, | |
1260 | .flags = IORESOURCE_IRQ, | |
1261 | }, | |
1262 | }; | |
1263 | ||
1264 | static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = { | |
1265 | .port_gpio_base = GPIO_PD0, | |
1266 | .port_pin_base = GPIO_PD0, | |
1267 | .port_width = GPIO_BANKSIZE, | |
1268 | .pint_id = 2, | |
1269 | .pint_assign = false, | |
1270 | .pint_map = 1, | |
1271 | }; | |
1272 | ||
1273 | static struct platform_device bfin_gpd_device = { | |
1274 | .name = ADI_GPIO_DEVNAME, | |
1275 | .id = 3, | |
1276 | .num_resources = ARRAY_SIZE(bfin_gpd_resources), | |
1277 | .resource = bfin_gpd_resources, | |
1278 | .dev = { | |
1279 | .platform_data = &bfin_gpd_pdata, /* Passed to driver */ | |
1280 | }, | |
1281 | }; | |
1282 | ||
1283 | static struct resource bfin_gpe_resources[] = { | |
1284 | { | |
1285 | .start = PORTE_FER, | |
1286 | .end = PORTE_MUX + 3, | |
1287 | .flags = IORESOURCE_MEM, | |
1288 | }, | |
1289 | { | |
1290 | .start = IRQ_PE0, | |
1291 | .end = IRQ_PE0, | |
1292 | .flags = IORESOURCE_IRQ, | |
1293 | }, | |
1294 | }; | |
1295 | ||
1296 | static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = { | |
1297 | .port_gpio_base = GPIO_PE0, | |
1298 | .port_pin_base = GPIO_PE0, | |
1299 | .port_width = GPIO_BANKSIZE, | |
1300 | .pint_id = 3, | |
1301 | .pint_assign = true, | |
1302 | .pint_map = 2, | |
1303 | }; | |
1304 | ||
1305 | static struct platform_device bfin_gpe_device = { | |
1306 | .name = ADI_GPIO_DEVNAME, | |
1307 | .id = 4, | |
1308 | .num_resources = ARRAY_SIZE(bfin_gpe_resources), | |
1309 | .resource = bfin_gpe_resources, | |
1310 | .dev = { | |
1311 | .platform_data = &bfin_gpe_pdata, /* Passed to driver */ | |
1312 | }, | |
1313 | }; | |
1314 | ||
1315 | static struct resource bfin_gpf_resources[] = { | |
1316 | { | |
1317 | .start = PORTF_FER, | |
1318 | .end = PORTF_MUX + 3, | |
1319 | .flags = IORESOURCE_MEM, | |
1320 | }, | |
1321 | { | |
1322 | .start = IRQ_PF0, | |
1323 | .end = IRQ_PF0, | |
1324 | .flags = IORESOURCE_IRQ, | |
1325 | }, | |
1326 | }; | |
1327 | ||
1328 | static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = { | |
1329 | .port_gpio_base = GPIO_PF0, | |
1330 | .port_pin_base = GPIO_PF0, | |
1331 | .port_width = GPIO_BANKSIZE, | |
1332 | .pint_id = 3, | |
1333 | .pint_assign = false, | |
1334 | .pint_map = 3, | |
1335 | }; | |
1336 | ||
1337 | static struct platform_device bfin_gpf_device = { | |
1338 | .name = ADI_GPIO_DEVNAME, | |
1339 | .id = 5, | |
1340 | .num_resources = ARRAY_SIZE(bfin_gpf_resources), | |
1341 | .resource = bfin_gpf_resources, | |
1342 | .dev = { | |
1343 | .platform_data = &bfin_gpf_pdata, /* Passed to driver */ | |
1344 | }, | |
1345 | }; | |
1346 | ||
1347 | static struct resource bfin_gpg_resources[] = { | |
1348 | { | |
1349 | .start = PORTG_FER, | |
1350 | .end = PORTG_MUX + 3, | |
1351 | .flags = IORESOURCE_MEM, | |
1352 | }, | |
1353 | { | |
1354 | .start = IRQ_PG0, | |
1355 | .end = IRQ_PG0, | |
1356 | .flags = IORESOURCE_IRQ, | |
1357 | }, | |
1358 | }; | |
1359 | ||
1360 | static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = { | |
1361 | .port_gpio_base = GPIO_PG0, | |
1362 | .port_pin_base = GPIO_PG0, | |
1363 | .port_width = GPIO_BANKSIZE, | |
1364 | .pint_id = -1, | |
1365 | }; | |
1366 | ||
1367 | static struct platform_device bfin_gpg_device = { | |
1368 | .name = ADI_GPIO_DEVNAME, | |
1369 | .id = 6, | |
1370 | .num_resources = ARRAY_SIZE(bfin_gpg_resources), | |
1371 | .resource = bfin_gpg_resources, | |
1372 | .dev = { | |
1373 | .platform_data = &bfin_gpg_pdata, /* Passed to driver */ | |
1374 | }, | |
1375 | }; | |
1376 | ||
1377 | static struct resource bfin_gph_resources[] = { | |
1378 | { | |
1379 | .start = PORTH_FER, | |
1380 | .end = PORTH_MUX + 3, | |
1381 | .flags = IORESOURCE_MEM, | |
1382 | }, | |
1383 | { | |
1384 | .start = IRQ_PH0, | |
1385 | .end = IRQ_PH0, | |
1386 | .flags = IORESOURCE_IRQ, | |
1387 | }, | |
1388 | }; | |
1389 | ||
1390 | static struct adi_pinctrl_gpio_platform_data bfin_gph_pdata = { | |
1391 | .port_gpio_base = GPIO_PH0, | |
1392 | .port_pin_base = GPIO_PH0, | |
1393 | .port_width = 14, | |
1394 | .pint_id = -1, | |
1395 | }; | |
1396 | ||
1397 | static struct platform_device bfin_gph_device = { | |
1398 | .name = ADI_GPIO_DEVNAME, | |
1399 | .id = 7, | |
1400 | .num_resources = ARRAY_SIZE(bfin_gph_resources), | |
1401 | .resource = bfin_gph_resources, | |
1402 | .dev = { | |
1403 | .platform_data = &bfin_gph_pdata, /* Passed to driver */ | |
1404 | }, | |
1405 | }; | |
1406 | ||
1407 | static struct resource bfin_gpi_resources[] = { | |
1408 | { | |
1409 | .start = PORTI_FER, | |
1410 | .end = PORTI_MUX + 3, | |
1411 | .flags = IORESOURCE_MEM, | |
1412 | }, | |
1413 | { | |
1414 | .start = IRQ_PI0, | |
1415 | .end = IRQ_PI0, | |
1416 | .flags = IORESOURCE_IRQ, | |
1417 | }, | |
1418 | }; | |
1419 | ||
1420 | static struct adi_pinctrl_gpio_platform_data bfin_gpi_pdata = { | |
1421 | .port_gpio_base = GPIO_PI0, | |
1422 | .port_pin_base = GPIO_PI0, | |
1423 | .port_width = GPIO_BANKSIZE, | |
1424 | .pint_id = -1, | |
1425 | }; | |
1426 | ||
1427 | static struct platform_device bfin_gpi_device = { | |
1428 | .name = ADI_GPIO_DEVNAME, | |
1429 | .id = 8, | |
1430 | .num_resources = ARRAY_SIZE(bfin_gpi_resources), | |
1431 | .resource = bfin_gpi_resources, | |
1432 | .dev = { | |
1433 | .platform_data = &bfin_gpi_pdata, /* Passed to driver */ | |
1434 | }, | |
1435 | }; | |
1436 | ||
1437 | static struct resource bfin_gpj_resources[] = { | |
1438 | { | |
1439 | .start = PORTJ_FER, | |
1440 | .end = PORTJ_MUX + 3, | |
1441 | .flags = IORESOURCE_MEM, | |
1442 | }, | |
1443 | { | |
1444 | .start = IRQ_PJ0, | |
1445 | .end = IRQ_PJ0, | |
1446 | .flags = IORESOURCE_IRQ, | |
1447 | }, | |
1448 | }; | |
1449 | ||
1450 | static struct adi_pinctrl_gpio_platform_data bfin_gpj_pdata = { | |
1451 | .port_gpio_base = GPIO_PJ0, | |
1452 | .port_pin_base = GPIO_PJ0, | |
1453 | .port_width = 14, | |
1454 | .pint_id = -1, | |
1455 | }; | |
1456 | ||
1457 | static struct platform_device bfin_gpj_device = { | |
1458 | .name = ADI_GPIO_DEVNAME, | |
1459 | .id = 9, | |
1460 | .num_resources = ARRAY_SIZE(bfin_gpj_resources), | |
1461 | .resource = bfin_gpj_resources, | |
1462 | .dev = { | |
1463 | .platform_data = &bfin_gpj_pdata, /* Passed to driver */ | |
1464 | }, | |
1465 | }; | |
1466 | ||
1467 | #endif | |
1468 | ||
5bda2723 | 1469 | static struct spi_board_info bfin_spi_board_info[] __initdata = { |
c6c4d7bb BW |
1470 | #if defined(CONFIG_MTD_M25P80) \ |
1471 | || defined(CONFIG_MTD_M25P80_MODULE) | |
1472 | { | |
1473 | /* the modalias must be the same as spi device driver name */ | |
1474 | .modalias = "m25p80", /* Name of spi_driver for this device */ | |
1475 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | |
1476 | .bus_num = 0, /* Framework bus number */ | |
54e4ff4d | 1477 | .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1*/ |
c6c4d7bb BW |
1478 | .platform_data = &bfin_spi_flash_data, |
1479 | .controller_data = &spi_flash_chip_info, | |
1480 | .mode = SPI_MODE_3, | |
1481 | }, | |
1482 | #endif | |
7ba80063 BS |
1483 | #if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ |
1484 | || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) | |
37fa2421 | 1485 | { |
7ba80063 | 1486 | .modalias = "ad183x", |
37fa2421 BS |
1487 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
1488 | .bus_num = 1, | |
54e4ff4d | 1489 | .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */ |
37fa2421 BS |
1490 | }, |
1491 | #endif | |
c6c4d7bb | 1492 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) |
ffc4d8bc MH |
1493 | { |
1494 | .modalias = "ad7877", | |
1495 | .platform_data = &bfin_ad7877_ts_info, | |
1496 | .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */ | |
1497 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | |
1498 | .bus_num = 0, | |
54e4ff4d | 1499 | .chip_select = MAX_CTRL_CS + GPIO_PE5, /* SPI_SSEL2 */ |
ffc4d8bc | 1500 | }, |
c6c4d7bb | 1501 | #endif |
6e668936 MH |
1502 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) |
1503 | { | |
1504 | .modalias = "spidev", | |
1505 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | |
1506 | .bus_num = 0, | |
54e4ff4d | 1507 | .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1 */ |
6e668936 MH |
1508 | }, |
1509 | #endif | |
ffc4d8bc MH |
1510 | #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) |
1511 | { | |
1512 | .modalias = "adxl34x", | |
1513 | .platform_data = &adxl34x_info, | |
1514 | .irq = IRQ_PC5, | |
1515 | .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ | |
1516 | .bus_num = 1, | |
54e4ff4d | 1517 | .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */ |
ffc4d8bc MH |
1518 | .mode = SPI_MODE_3, |
1519 | }, | |
1520 | #endif | |
c6c4d7bb | 1521 | }; |
7d157fb0 | 1522 | #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE) |
c6c4d7bb BW |
1523 | /* SPI (0) */ |
1524 | static struct resource bfin_spi0_resource[] = { | |
1525 | [0] = { | |
1526 | .start = SPI0_REGBASE, | |
1527 | .end = SPI0_REGBASE + 0xFF, | |
1528 | .flags = IORESOURCE_MEM, | |
1529 | }, | |
1530 | [1] = { | |
1531 | .start = CH_SPI0, | |
1532 | .end = CH_SPI0, | |
53122693 YL |
1533 | .flags = IORESOURCE_DMA, |
1534 | }, | |
1535 | [2] = { | |
1536 | .start = IRQ_SPI0, | |
1537 | .end = IRQ_SPI0, | |
c6c4d7bb BW |
1538 | .flags = IORESOURCE_IRQ, |
1539 | } | |
1540 | }; | |
1541 | ||
1542 | /* SPI (1) */ | |
1543 | static struct resource bfin_spi1_resource[] = { | |
1544 | [0] = { | |
1545 | .start = SPI1_REGBASE, | |
1546 | .end = SPI1_REGBASE + 0xFF, | |
1547 | .flags = IORESOURCE_MEM, | |
1548 | }, | |
1549 | [1] = { | |
1550 | .start = CH_SPI1, | |
1551 | .end = CH_SPI1, | |
53122693 YL |
1552 | .flags = IORESOURCE_DMA, |
1553 | }, | |
1554 | [2] = { | |
1555 | .start = IRQ_SPI1, | |
1556 | .end = IRQ_SPI1, | |
c6c4d7bb BW |
1557 | .flags = IORESOURCE_IRQ, |
1558 | } | |
1559 | }; | |
1560 | ||
1561 | /* SPI controller data */ | |
5d448dd5 | 1562 | static struct bfin5xx_spi_master bf54x_spi_master_info0 = { |
54e4ff4d | 1563 | .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, |
c6c4d7bb | 1564 | .enable_dma = 1, /* master has the ability to do dma transfer */ |
5d448dd5 | 1565 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, |
c6c4d7bb BW |
1566 | }; |
1567 | ||
1568 | static struct platform_device bf54x_spi_master0 = { | |
1569 | .name = "bfin-spi", | |
1570 | .id = 0, /* Bus number */ | |
1571 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | |
1572 | .resource = bfin_spi0_resource, | |
1573 | .dev = { | |
5d448dd5 | 1574 | .platform_data = &bf54x_spi_master_info0, /* Passed to driver */ |
c6c4d7bb BW |
1575 | }, |
1576 | }; | |
1577 | ||
5d448dd5 | 1578 | static struct bfin5xx_spi_master bf54x_spi_master_info1 = { |
54e4ff4d | 1579 | .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, |
5d448dd5 BW |
1580 | .enable_dma = 1, /* master has the ability to do dma transfer */ |
1581 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, | |
1582 | }; | |
1583 | ||
c6c4d7bb BW |
1584 | static struct platform_device bf54x_spi_master1 = { |
1585 | .name = "bfin-spi", | |
1586 | .id = 1, /* Bus number */ | |
1587 | .num_resources = ARRAY_SIZE(bfin_spi1_resource), | |
1588 | .resource = bfin_spi1_resource, | |
1589 | .dev = { | |
5d448dd5 | 1590 | .platform_data = &bf54x_spi_master_info1, /* Passed to driver */ |
c6c4d7bb BW |
1591 | }, |
1592 | }; | |
1593 | #endif /* spi master and devices */ | |
1594 | ||
df864c30 SJ |
1595 | #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \ |
1596 | || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE) | |
1597 | #include <linux/videodev2.h> | |
1598 | #include <media/blackfin/bfin_capture.h> | |
1599 | #include <media/blackfin/ppi.h> | |
1600 | ||
1601 | static const unsigned short ppi_req[] = { | |
1602 | P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, | |
1603 | P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, | |
1604 | P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, | |
1605 | 0, | |
1606 | }; | |
1607 | ||
1608 | static const struct ppi_info ppi_info = { | |
1609 | .type = PPI_TYPE_EPPI, | |
1610 | .dma_ch = CH_EPPI1, | |
1611 | .irq_err = IRQ_EPPI1_ERROR, | |
1612 | .base = (void __iomem *)EPPI1_STATUS, | |
1613 | .pin_req = ppi_req, | |
1614 | }; | |
1615 | ||
1616 | #if defined(CONFIG_VIDEO_VS6624) \ | |
1617 | || defined(CONFIG_VIDEO_VS6624_MODULE) | |
1618 | static struct v4l2_input vs6624_inputs[] = { | |
1619 | { | |
1620 | .index = 0, | |
1621 | .name = "Camera", | |
1622 | .type = V4L2_INPUT_TYPE_CAMERA, | |
1623 | .std = V4L2_STD_UNKNOWN, | |
1624 | }, | |
1625 | }; | |
1626 | ||
1627 | static struct bcap_route vs6624_routes[] = { | |
1628 | { | |
1629 | .input = 0, | |
1630 | .output = 0, | |
1631 | }, | |
1632 | }; | |
1633 | ||
1634 | static const unsigned vs6624_ce_pin = GPIO_PG6; | |
1635 | ||
1636 | static struct bfin_capture_config bfin_capture_data = { | |
1637 | .card_name = "BF548", | |
1638 | .inputs = vs6624_inputs, | |
1639 | .num_inputs = ARRAY_SIZE(vs6624_inputs), | |
1640 | .routes = vs6624_routes, | |
1641 | .i2c_adapter_id = 0, | |
1642 | .board_info = { | |
1643 | .type = "vs6624", | |
1644 | .addr = 0x10, | |
1645 | .platform_data = (void *)&vs6624_ce_pin, | |
1646 | }, | |
1647 | .ppi_info = &ppi_info, | |
1648 | .ppi_control = (POLC | PACKEN | DLEN_8 | XFR_TYPE | 0x20), | |
4e937ac1 SJ |
1649 | .int_mask = 0xFFFFFFFF, /* disable error interrupt on eppi */ |
1650 | .blank_clocks = 8, /* 8 clocks as SAV and EAV */ | |
df864c30 SJ |
1651 | }; |
1652 | #endif | |
1653 | ||
1654 | static struct platform_device bfin_capture_device = { | |
1655 | .name = "bfin_capture", | |
1656 | .dev = { | |
1657 | .platform_data = &bfin_capture_data, | |
1658 | }, | |
1659 | }; | |
1660 | #endif | |
1661 | ||
c6c4d7bb | 1662 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
cf93feb3 SZ |
1663 | static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; |
1664 | ||
c6c4d7bb BW |
1665 | static struct resource bfin_twi0_resource[] = { |
1666 | [0] = { | |
1667 | .start = TWI0_REGBASE, | |
1668 | .end = TWI0_REGBASE + 0xFF, | |
1669 | .flags = IORESOURCE_MEM, | |
1670 | }, | |
1671 | [1] = { | |
1672 | .start = IRQ_TWI0, | |
1673 | .end = IRQ_TWI0, | |
1674 | .flags = IORESOURCE_IRQ, | |
1675 | }, | |
1676 | }; | |
1677 | ||
1678 | static struct platform_device i2c_bfin_twi0_device = { | |
1679 | .name = "i2c-bfin-twi", | |
1680 | .id = 0, | |
1681 | .num_resources = ARRAY_SIZE(bfin_twi0_resource), | |
1682 | .resource = bfin_twi0_resource, | |
cf93feb3 SZ |
1683 | .dev = { |
1684 | .platform_data = &bfin_twi0_pins, | |
1685 | }, | |
c6c4d7bb BW |
1686 | }; |
1687 | ||
7160e950 | 1688 | #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ |
cf93feb3 SZ |
1689 | static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0}; |
1690 | ||
c6c4d7bb BW |
1691 | static struct resource bfin_twi1_resource[] = { |
1692 | [0] = { | |
1693 | .start = TWI1_REGBASE, | |
1694 | .end = TWI1_REGBASE + 0xFF, | |
1695 | .flags = IORESOURCE_MEM, | |
1696 | }, | |
1697 | [1] = { | |
1698 | .start = IRQ_TWI1, | |
1699 | .end = IRQ_TWI1, | |
1700 | .flags = IORESOURCE_IRQ, | |
1701 | }, | |
1702 | }; | |
1703 | ||
1704 | static struct platform_device i2c_bfin_twi1_device = { | |
1705 | .name = "i2c-bfin-twi", | |
1706 | .id = 1, | |
1707 | .num_resources = ARRAY_SIZE(bfin_twi1_resource), | |
1708 | .resource = bfin_twi1_resource, | |
cf93feb3 SZ |
1709 | .dev = { |
1710 | .platform_data = &bfin_twi1_pins, | |
1711 | }, | |
c6c4d7bb BW |
1712 | }; |
1713 | #endif | |
7160e950 | 1714 | #endif |
c6c4d7bb | 1715 | |
81d9c7f2 | 1716 | static struct i2c_board_info __initdata bfin_i2c_board_info0[] = { |
eeec0a13 SZ |
1717 | #if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE) |
1718 | { | |
1719 | I2C_BOARD_INFO("ssm2602", 0x1b), | |
1720 | }, | |
1721 | #endif | |
81d9c7f2 BW |
1722 | }; |
1723 | ||
1724 | #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ | |
1725 | static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { | |
ebd58333 | 1726 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) |
81d9c7f2 BW |
1727 | { |
1728 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | |
81d9c7f2 BW |
1729 | }, |
1730 | #endif | |
204844eb | 1731 | #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE) |
81d9c7f2 BW |
1732 | { |
1733 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), | |
81d9c7f2 BW |
1734 | .irq = 212, |
1735 | }, | |
1736 | #endif | |
ffc4d8bc MH |
1737 | #if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE) |
1738 | { | |
1739 | I2C_BOARD_INFO("adxl34x", 0x53), | |
1740 | .irq = IRQ_PC5, | |
1741 | .platform_data = (void *)&adxl34x_info, | |
1742 | }, | |
1743 | #endif | |
39d3c1ca | 1744 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) |
1745 | { | |
1746 | I2C_BOARD_INFO("ad5252", 0x2f), | |
1747 | }, | |
1748 | #endif | |
81d9c7f2 BW |
1749 | }; |
1750 | #endif | |
81d9c7f2 | 1751 | |
2463ef22 MH |
1752 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) |
1753 | #include <linux/gpio_keys.h> | |
1754 | ||
1755 | static struct gpio_keys_button bfin_gpio_keys_table[] = { | |
1756 | {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"}, | |
1757 | {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"}, | |
1758 | {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"}, | |
1759 | {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"}, | |
1760 | }; | |
1761 | ||
1762 | static struct gpio_keys_platform_data bfin_gpio_keys_data = { | |
1763 | .buttons = bfin_gpio_keys_table, | |
1764 | .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), | |
1765 | }; | |
1766 | ||
1767 | static struct platform_device bfin_device_gpiokeys = { | |
1768 | .name = "gpio-keys", | |
1769 | .dev = { | |
1770 | .platform_data = &bfin_gpio_keys_data, | |
1771 | }, | |
1772 | }; | |
1773 | #endif | |
1774 | ||
14b03204 MH |
1775 | static const unsigned int cclk_vlev_datasheet[] = |
1776 | { | |
1777 | /* | |
1778 | * Internal VLEV BF54XSBBC1533 | |
1779 | ****temporarily using these values until data sheet is updated | |
1780 | */ | |
1781 | VRPAIR(VLEV_085, 150000000), | |
1782 | VRPAIR(VLEV_090, 250000000), | |
1783 | VRPAIR(VLEV_110, 276000000), | |
1784 | VRPAIR(VLEV_115, 301000000), | |
1785 | VRPAIR(VLEV_120, 525000000), | |
1786 | VRPAIR(VLEV_125, 550000000), | |
1787 | VRPAIR(VLEV_130, 600000000), | |
1788 | }; | |
1789 | ||
1790 | static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { | |
1791 | .tuple_tab = cclk_vlev_datasheet, | |
1792 | .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), | |
1793 | .vr_settling_time = 25 /* us */, | |
1794 | }; | |
1795 | ||
1796 | static struct platform_device bfin_dpmc = { | |
1797 | .name = "bfin dpmc", | |
1798 | .dev = { | |
1799 | .platform_data = &bfin_dmpc_vreg_data, | |
1800 | }, | |
1801 | }; | |
1802 | ||
6f53dbbb | 1803 | #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \ |
6f53dbbb SJ |
1804 | defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) |
1805 | ||
1806 | #define SPORT_REQ(x) \ | |
1807 | [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \ | |
1808 | P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0} | |
1809 | ||
1810 | static const u16 bfin_snd_pin[][7] = { | |
1811 | SPORT_REQ(0), | |
1812 | SPORT_REQ(1), | |
eeec0a13 SZ |
1813 | SPORT_REQ(2), |
1814 | SPORT_REQ(3), | |
6f53dbbb SJ |
1815 | }; |
1816 | ||
1817 | static struct bfin_snd_platform_data bfin_snd_data[] = { | |
1818 | { | |
1819 | .pin_req = &bfin_snd_pin[0][0], | |
1820 | }, | |
1821 | { | |
1822 | .pin_req = &bfin_snd_pin[1][0], | |
1823 | }, | |
eeec0a13 SZ |
1824 | { |
1825 | .pin_req = &bfin_snd_pin[2][0], | |
1826 | }, | |
1827 | { | |
1828 | .pin_req = &bfin_snd_pin[3][0], | |
1829 | }, | |
6f53dbbb SJ |
1830 | }; |
1831 | ||
1832 | #define BFIN_SND_RES(x) \ | |
1833 | [x] = { \ | |
1834 | { \ | |
1835 | .start = SPORT##x##_TCR1, \ | |
1836 | .end = SPORT##x##_TCR1, \ | |
1837 | .flags = IORESOURCE_MEM \ | |
1838 | }, \ | |
1839 | { \ | |
1840 | .start = CH_SPORT##x##_RX, \ | |
1841 | .end = CH_SPORT##x##_RX, \ | |
1842 | .flags = IORESOURCE_DMA, \ | |
1843 | }, \ | |
1844 | { \ | |
1845 | .start = CH_SPORT##x##_TX, \ | |
1846 | .end = CH_SPORT##x##_TX, \ | |
1847 | .flags = IORESOURCE_DMA, \ | |
1848 | }, \ | |
1849 | { \ | |
1850 | .start = IRQ_SPORT##x##_ERROR, \ | |
1851 | .end = IRQ_SPORT##x##_ERROR, \ | |
1852 | .flags = IORESOURCE_IRQ, \ | |
1853 | } \ | |
1854 | } | |
1855 | ||
1856 | static struct resource bfin_snd_resources[][4] = { | |
1857 | BFIN_SND_RES(0), | |
1858 | BFIN_SND_RES(1), | |
eeec0a13 SZ |
1859 | BFIN_SND_RES(2), |
1860 | BFIN_SND_RES(3), | |
6f53dbbb | 1861 | }; |
eeec0a13 | 1862 | #endif |
6f53dbbb | 1863 | |
eeec0a13 SZ |
1864 | #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) |
1865 | static struct platform_device bfin_i2s_pcm = { | |
1866 | .name = "bfin-i2s-pcm-audio", | |
1867 | .id = -1, | |
1868 | }; | |
1869 | #endif | |
1870 | ||
eeec0a13 SZ |
1871 | #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) |
1872 | static struct platform_device bfin_ac97_pcm = { | |
1873 | .name = "bfin-ac97-pcm-audio", | |
6f53dbbb SJ |
1874 | .id = -1, |
1875 | }; | |
1876 | #endif | |
1877 | ||
1878 | #if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE) | |
1879 | static struct platform_device bfin_ad73311_codec_device = { | |
1880 | .name = "ad73311", | |
1881 | .id = -1, | |
1882 | }; | |
1883 | #endif | |
1884 | ||
1885 | #if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE) | |
1886 | static struct platform_device bfin_ad1980_codec_device = { | |
1887 | .name = "ad1980", | |
1888 | .id = -1, | |
1889 | }; | |
1890 | #endif | |
1891 | ||
1892 | #if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE) | |
439b4867 BS |
1893 | static struct platform_device bfin_i2s = { |
1894 | .name = "bfin-i2s", | |
1895 | .id = CONFIG_SND_BF5XX_SPORT_NUM, | |
6f53dbbb SJ |
1896 | .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), |
1897 | .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], | |
1898 | .dev = { | |
1899 | .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], | |
1900 | }, | |
439b4867 BS |
1901 | }; |
1902 | #endif | |
1903 | ||
6f53dbbb | 1904 | #if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE) |
439b4867 BS |
1905 | static struct platform_device bfin_ac97 = { |
1906 | .name = "bfin-ac97", | |
1907 | .id = CONFIG_SND_BF5XX_SPORT_NUM, | |
6f53dbbb SJ |
1908 | .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), |
1909 | .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], | |
1910 | .dev = { | |
1911 | .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], | |
1912 | }, | |
439b4867 BS |
1913 | }; |
1914 | #endif | |
1915 | ||
24a07a12 | 1916 | static struct platform_device *ezkit_devices[] __initdata = { |
14b03204 MH |
1917 | |
1918 | &bfin_dpmc, | |
54e4ff4d SZ |
1919 | #if defined(CONFIG_PINCTRL_ADI2) |
1920 | &bfin_pinctrl_device, | |
1921 | &bfin_pint0_device, | |
1922 | &bfin_pint1_device, | |
1923 | &bfin_pint2_device, | |
1924 | &bfin_pint3_device, | |
1925 | &bfin_gpa_device, | |
1926 | &bfin_gpb_device, | |
1927 | &bfin_gpc_device, | |
1928 | &bfin_gpd_device, | |
1929 | &bfin_gpe_device, | |
1930 | &bfin_gpf_device, | |
1931 | &bfin_gpg_device, | |
1932 | &bfin_gph_device, | |
1933 | &bfin_gpi_device, | |
1934 | &bfin_gpj_device, | |
1935 | #endif | |
14b03204 | 1936 | |
24a07a12 RH |
1937 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
1938 | &rtc_device, | |
1939 | #endif | |
1940 | ||
1941 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
6bd1fbea SZ |
1942 | #ifdef CONFIG_SERIAL_BFIN_UART0 |
1943 | &bfin_uart0_device, | |
1944 | #endif | |
1945 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
1946 | &bfin_uart1_device, | |
1947 | #endif | |
1948 | #ifdef CONFIG_SERIAL_BFIN_UART2 | |
1949 | &bfin_uart2_device, | |
1950 | #endif | |
1951 | #ifdef CONFIG_SERIAL_BFIN_UART3 | |
1952 | &bfin_uart3_device, | |
1953 | #endif | |
24a07a12 | 1954 | #endif |
c6c4d7bb | 1955 | |
5be36d22 | 1956 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
42bd8bcb GY |
1957 | #ifdef CONFIG_BFIN_SIR0 |
1958 | &bfin_sir0_device, | |
1959 | #endif | |
1960 | #ifdef CONFIG_BFIN_SIR1 | |
1961 | &bfin_sir1_device, | |
1962 | #endif | |
1963 | #ifdef CONFIG_BFIN_SIR2 | |
1964 | &bfin_sir2_device, | |
1965 | #endif | |
1966 | #ifdef CONFIG_BFIN_SIR3 | |
1967 | &bfin_sir3_device, | |
1968 | #endif | |
5be36d22 GY |
1969 | #endif |
1970 | ||
c6c4d7bb BW |
1971 | #if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE) |
1972 | &bf54x_lq043_device, | |
1973 | #endif | |
1974 | ||
1975 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | |
1976 | &smsc911x_device, | |
1977 | #endif | |
1978 | ||
c6c4d7bb BW |
1979 | #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) |
1980 | &musb_device, | |
1981 | #endif | |
1982 | ||
3f375690 MH |
1983 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) |
1984 | &bfin_isp1760_device, | |
1985 | #endif | |
1986 | ||
df5de261 SZ |
1987 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) |
1988 | #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART | |
1989 | &bfin_sport0_uart_device, | |
1990 | #endif | |
1991 | #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART | |
1992 | &bfin_sport1_uart_device, | |
1993 | #endif | |
1994 | #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART | |
1995 | &bfin_sport2_uart_device, | |
1996 | #endif | |
1997 | #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART | |
1998 | &bfin_sport3_uart_device, | |
1999 | #endif | |
2000 | #endif | |
2001 | ||
706a01b1 | 2002 | #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) |
4c131c8c AW |
2003 | &bfin_can0_device, |
2004 | &bfin_can1_device, | |
706a01b1 BS |
2005 | #endif |
2006 | ||
c6c4d7bb BW |
2007 | #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) |
2008 | &bfin_atapi_device, | |
2009 | #endif | |
2010 | ||
2011 | #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE) | |
2012 | &bf5xx_nand_device, | |
2013 | #endif | |
2014 | ||
3d7e6cf8 | 2015 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) |
c6c4d7bb BW |
2016 | &bf54x_sdh_device, |
2017 | #endif | |
2018 | ||
7d157fb0 | 2019 | #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE) |
c6c4d7bb | 2020 | &bf54x_spi_master0, |
d4b1d273 | 2021 | &bf54x_spi_master1, |
c6c4d7bb | 2022 | #endif |
df864c30 SJ |
2023 | #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \ |
2024 | || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE) | |
2025 | &bfin_capture_device, | |
2026 | #endif | |
c6c4d7bb BW |
2027 | |
2028 | #if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE) | |
2029 | &bf54x_kpad_device, | |
2030 | #endif | |
2031 | ||
adfc0467 | 2032 | #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) |
aca5e4aa MH |
2033 | &bfin_rotary_device, |
2034 | #endif | |
2035 | ||
c6c4d7bb BW |
2036 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) |
2037 | &i2c_bfin_twi0_device, | |
7160e950 | 2038 | #if !defined(CONFIG_BF542) |
c6c4d7bb BW |
2039 | &i2c_bfin_twi1_device, |
2040 | #endif | |
7160e950 | 2041 | #endif |
2463ef22 MH |
2042 | |
2043 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | |
2044 | &bfin_device_gpiokeys, | |
2045 | #endif | |
cad2ab65 | 2046 | |
793dc27b | 2047 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
de8c43f2 | 2048 | &ezkit_flash_device, |
793dc27b | 2049 | #endif |
439b4867 | 2050 | |
eeec0a13 SZ |
2051 | #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) |
2052 | &bfin_i2s_pcm, | |
2053 | #endif | |
15502e0c | 2054 | |
eeec0a13 SZ |
2055 | #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) |
2056 | &bfin_ac97_pcm, | |
6f53dbbb SJ |
2057 | #endif |
2058 | ||
2059 | #if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE) | |
2060 | &bfin_ad1980_codec_device, | |
2061 | #endif | |
2062 | ||
439b4867 BS |
2063 | #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) |
2064 | &bfin_i2s, | |
2065 | #endif | |
2066 | ||
439b4867 BS |
2067 | #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) |
2068 | &bfin_ac97, | |
2069 | #endif | |
24a07a12 RH |
2070 | }; |
2071 | ||
54e4ff4d SZ |
2072 | /* Pin control settings */ |
2073 | static struct pinctrl_map __initdata bfin_pinmux_map[] = { | |
2074 | /* per-device maps */ | |
2075 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"), | |
2076 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"), | |
2077 | #ifdef CONFIG_BFIN_UART1_CTSRTS | |
2078 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"), | |
2079 | #endif | |
2080 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.2", "pinctrl-adi2.0", NULL, "uart2"), | |
2081 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3"), | |
2082 | #ifdef CONFIG_BFIN_UART3_CTSRTS | |
2083 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3_ctsrts"), | |
2084 | #endif | |
2085 | PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"), | |
2086 | PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"), | |
2087 | PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.2", "pinctrl-adi2.0", NULL, "uart2"), | |
2088 | PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.3", "pinctrl-adi2.0", NULL, "uart3"), | |
2089 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"), | |
2090 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.0", "pinctrl-adi2.0", NULL, "spi0"), | |
2091 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.1", "pinctrl-adi2.0", NULL, "spi1"), | |
2092 | PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"), | |
2093 | #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ | |
2094 | PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"), | |
2095 | #endif | |
2096 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"), | |
2097 | PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"), | |
2098 | PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.1", "pinctrl-adi2.0", NULL, "can1"), | |
2099 | PIN_MAP_MUX_GROUP_DEFAULT("bf54x-lq043", "pinctrl-adi2.0", NULL, "ppi0_24b"), | |
2100 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"), | |
2101 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"), | |
2102 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.0", "pinctrl-adi2.0", NULL, "sport0"), | |
2103 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"), | |
2104 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"), | |
2105 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.1", "pinctrl-adi2.0", NULL, "sport1"), | |
2106 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"), | |
2107 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"), | |
2108 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.2", "pinctrl-adi2.0", NULL, "sport2"), | |
2109 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.3", "pinctrl-adi2.0", NULL, "sport3"), | |
2110 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.3", "pinctrl-adi2.0", NULL, "sport3"), | |
2111 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.3", "pinctrl-adi2.0", NULL, "sport3"), | |
2112 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.0", "pinctrl-adi2.0", NULL, "sport0"), | |
2113 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.1", "pinctrl-adi2.0", NULL, "sport1"), | |
2114 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.2", "pinctrl-adi2.0", NULL, "sport2"), | |
2115 | PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.3", "pinctrl-adi2.0", NULL, "sport3"), | |
2116 | PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi"), | |
2117 | #ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT | |
2118 | PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi_alter"), | |
2119 | #endif | |
2120 | PIN_MAP_MUX_GROUP_DEFAULT("bf5xx-nand.0", "pinctrl-adi2.0", NULL, "nfc0"), | |
2121 | PIN_MAP_MUX_GROUP_DEFAULT("bf54x-keys", "pinctrl-adi2.0", NULL, "keys_4x4"), | |
2122 | }; | |
2123 | ||
a01d7a76 | 2124 | static int __init ezkit_init(void) |
24a07a12 | 2125 | { |
b85d858b | 2126 | printk(KERN_INFO "%s(): registering device resources\n", __func__); |
81d9c7f2 | 2127 | |
54e4ff4d SZ |
2128 | /* Initialize pinmuxing */ |
2129 | pinctrl_register_mappings(bfin_pinmux_map, | |
2130 | ARRAY_SIZE(bfin_pinmux_map)); | |
2131 | ||
81d9c7f2 BW |
2132 | i2c_register_board_info(0, bfin_i2c_board_info0, |
2133 | ARRAY_SIZE(bfin_i2c_board_info0)); | |
2134 | #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ | |
2135 | i2c_register_board_info(1, bfin_i2c_board_info1, | |
2136 | ARRAY_SIZE(bfin_i2c_board_info1)); | |
81d9c7f2 BW |
2137 | #endif |
2138 | ||
24a07a12 | 2139 | platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); |
c6c4d7bb | 2140 | |
5bda2723 | 2141 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); |
c6c4d7bb | 2142 | |
24a07a12 RH |
2143 | return 0; |
2144 | } | |
2145 | ||
a01d7a76 | 2146 | arch_initcall(ezkit_init); |
c13ce9fd SZ |
2147 | |
2148 | static struct platform_device *ezkit_early_devices[] __initdata = { | |
2149 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) | |
2150 | #ifdef CONFIG_SERIAL_BFIN_UART0 | |
2151 | &bfin_uart0_device, | |
2152 | #endif | |
2153 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
2154 | &bfin_uart1_device, | |
2155 | #endif | |
2156 | #ifdef CONFIG_SERIAL_BFIN_UART2 | |
2157 | &bfin_uart2_device, | |
2158 | #endif | |
2159 | #ifdef CONFIG_SERIAL_BFIN_UART3 | |
2160 | &bfin_uart3_device, | |
2161 | #endif | |
2162 | #endif | |
2163 | ||
2164 | #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) | |
2165 | #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART | |
2166 | &bfin_sport0_uart_device, | |
2167 | #endif | |
2168 | #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART | |
2169 | &bfin_sport1_uart_device, | |
2170 | #endif | |
2171 | #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART | |
2172 | &bfin_sport2_uart_device, | |
2173 | #endif | |
2174 | #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART | |
2175 | &bfin_sport3_uart_device, | |
2176 | #endif | |
2177 | #endif | |
2178 | }; | |
2179 | ||
2180 | void __init native_machine_early_platform_add_devices(void) | |
2181 | { | |
2182 | printk(KERN_INFO "register early platform devices\n"); | |
2183 | early_platform_add_devices(ezkit_early_devices, | |
2184 | ARRAY_SIZE(ezkit_early_devices)); | |
2185 | } |