Commit | Line | Data |
---|---|---|
24a07a12 | 1 | /* |
96f1050d | 2 | * the simple DMA Implementation for Blackfin |
24a07a12 | 3 | * |
96f1050d | 4 | * Copyright 2007-2009 Analog Devices Inc. |
24a07a12 | 5 | * |
96f1050d | 6 | * Licensed under the GPL-2 or later. |
24a07a12 RH |
7 | */ |
8 | ||
7aa475cf MF |
9 | #include <linux/module.h> |
10 | ||
24a07a12 RH |
11 | #include <asm/blackfin.h> |
12 | #include <asm/dma.h> | |
13 | ||
5e3bcf30 | 14 | struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = { |
24a07a12 RH |
15 | (struct dma_register *) DMA0_NEXT_DESC_PTR, |
16 | (struct dma_register *) DMA1_NEXT_DESC_PTR, | |
17 | (struct dma_register *) DMA2_NEXT_DESC_PTR, | |
18 | (struct dma_register *) DMA3_NEXT_DESC_PTR, | |
19 | (struct dma_register *) DMA4_NEXT_DESC_PTR, | |
20 | (struct dma_register *) DMA5_NEXT_DESC_PTR, | |
21 | (struct dma_register *) DMA6_NEXT_DESC_PTR, | |
22 | (struct dma_register *) DMA7_NEXT_DESC_PTR, | |
23 | (struct dma_register *) DMA8_NEXT_DESC_PTR, | |
24 | (struct dma_register *) DMA9_NEXT_DESC_PTR, | |
25 | (struct dma_register *) DMA10_NEXT_DESC_PTR, | |
26 | (struct dma_register *) DMA11_NEXT_DESC_PTR, | |
27 | (struct dma_register *) DMA12_NEXT_DESC_PTR, | |
28 | (struct dma_register *) DMA13_NEXT_DESC_PTR, | |
29 | (struct dma_register *) DMA14_NEXT_DESC_PTR, | |
30 | (struct dma_register *) DMA15_NEXT_DESC_PTR, | |
31 | (struct dma_register *) DMA16_NEXT_DESC_PTR, | |
32 | (struct dma_register *) DMA17_NEXT_DESC_PTR, | |
33 | (struct dma_register *) DMA18_NEXT_DESC_PTR, | |
34 | (struct dma_register *) DMA19_NEXT_DESC_PTR, | |
35 | (struct dma_register *) DMA20_NEXT_DESC_PTR, | |
36 | (struct dma_register *) DMA21_NEXT_DESC_PTR, | |
37 | (struct dma_register *) DMA22_NEXT_DESC_PTR, | |
38 | (struct dma_register *) DMA23_NEXT_DESC_PTR, | |
39 | (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, | |
40 | (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, | |
41 | (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, | |
42 | (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, | |
43 | (struct dma_register *) MDMA_D2_NEXT_DESC_PTR, | |
44 | (struct dma_register *) MDMA_S2_NEXT_DESC_PTR, | |
45 | (struct dma_register *) MDMA_D3_NEXT_DESC_PTR, | |
46 | (struct dma_register *) MDMA_S3_NEXT_DESC_PTR, | |
47 | }; | |
77955664 | 48 | EXPORT_SYMBOL(dma_io_base_addr); |
24a07a12 RH |
49 | |
50 | int channel2irq(unsigned int channel) | |
51 | { | |
52 | int ret_irq = -1; | |
53 | ||
54 | switch (channel) { | |
55 | case CH_SPORT0_RX: | |
56 | ret_irq = IRQ_SPORT0_RX; | |
57 | break; | |
58 | case CH_SPORT0_TX: | |
59 | ret_irq = IRQ_SPORT0_TX; | |
60 | break; | |
61 | case CH_SPORT1_RX: | |
62 | ret_irq = IRQ_SPORT1_RX; | |
63 | break; | |
64 | case CH_SPORT1_TX: | |
65 | ret_irq = IRQ_SPORT1_TX; | |
a71159b9 | 66 | break; |
24a07a12 RH |
67 | case CH_SPI0: |
68 | ret_irq = IRQ_SPI0; | |
69 | break; | |
70 | case CH_SPI1: | |
71 | ret_irq = IRQ_SPI1; | |
72 | break; | |
73 | case CH_UART0_RX: | |
a2f78cfc | 74 | ret_irq = IRQ_UART0_RX; |
24a07a12 RH |
75 | break; |
76 | case CH_UART0_TX: | |
a2f78cfc | 77 | ret_irq = IRQ_UART0_TX; |
24a07a12 RH |
78 | break; |
79 | case CH_UART1_RX: | |
a2f78cfc | 80 | ret_irq = IRQ_UART1_RX; |
24a07a12 RH |
81 | break; |
82 | case CH_UART1_TX: | |
a2f78cfc | 83 | ret_irq = IRQ_UART1_TX; |
24a07a12 RH |
84 | break; |
85 | case CH_EPPI0: | |
86 | ret_irq = IRQ_EPPI0; | |
87 | break; | |
88 | case CH_EPPI1: | |
89 | ret_irq = IRQ_EPPI1; | |
90 | break; | |
91 | case CH_EPPI2: | |
92 | ret_irq = IRQ_EPPI2; | |
93 | break; | |
94 | case CH_PIXC_IMAGE: | |
95 | ret_irq = IRQ_PIXC_IN0; | |
96 | break; | |
97 | case CH_PIXC_OVERLAY: | |
98 | ret_irq = IRQ_PIXC_IN1; | |
99 | break; | |
100 | case CH_PIXC_OUTPUT: | |
101 | ret_irq = IRQ_PIXC_OUT; | |
102 | break; | |
103 | case CH_SPORT2_RX: | |
104 | ret_irq = IRQ_SPORT2_RX; | |
105 | break; | |
106 | case CH_SPORT2_TX: | |
107 | ret_irq = IRQ_SPORT2_TX; | |
108 | break; | |
109 | case CH_SPORT3_RX: | |
110 | ret_irq = IRQ_SPORT3_RX; | |
111 | break; | |
112 | case CH_SPORT3_TX: | |
113 | ret_irq = IRQ_SPORT3_TX; | |
114 | break; | |
115 | case CH_SDH: | |
116 | ret_irq = IRQ_SDH; | |
117 | break; | |
118 | case CH_SPI2: | |
119 | ret_irq = IRQ_SPI2; | |
120 | break; | |
121 | case CH_MEM_STREAM0_SRC: | |
122 | case CH_MEM_STREAM0_DEST: | |
123 | ret_irq = IRQ_MDMAS0; | |
124 | break; | |
125 | case CH_MEM_STREAM1_SRC: | |
126 | case CH_MEM_STREAM1_DEST: | |
127 | ret_irq = IRQ_MDMAS1; | |
128 | break; | |
129 | case CH_MEM_STREAM2_SRC: | |
130 | case CH_MEM_STREAM2_DEST: | |
131 | ret_irq = IRQ_MDMAS2; | |
132 | break; | |
133 | case CH_MEM_STREAM3_SRC: | |
134 | case CH_MEM_STREAM3_DEST: | |
135 | ret_irq = IRQ_MDMAS3; | |
136 | break; | |
137 | } | |
138 | return ret_irq; | |
139 | } |