projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4f25eb85 MF |
1 | if (BF561) |
| 2 | ||
| 3 | source "arch/blackfin/mach-bf561/boards/Kconfig" | |
| 1394f032 BW |
4 | |
| 5 | menu "BF561 Specific Configuration" | |
| 6 | ||
| c51b4488 | 7 | if (!SMP) |
| 1394f032 | 8 | |
| c51b4488 | 9 | comment "Core B Support" |
| 1394f032 BW |
10 | |
| 11 | config BF561_COREB | |
| c8f36dc3 | 12 | bool "Enable Core B loader" |
| 1394f032 BW |
13 | default y |
| 14 | ||
| c51b4488 | 15 | endif |
| 1394f032 BW |
16 | |
| 17 | comment "Interrupt Priority Assignment" | |
| 18 | ||
| 19 | menu "Priority" | |
| 20 | ||
| 21 | config IRQ_PLL_WAKEUP | |
| 22 | int "PLL Wakeup Interrupt" | |
| 23 | default 7 | |
| 24 | config IRQ_DMA1_ERROR | |
| 25 | int "DMA1 Error (generic)" | |
| 26 | default 7 | |
| 27 | config IRQ_DMA2_ERROR | |
| 28 | int "DMA2 Error (generic)" | |
| 29 | default 7 | |
| 30 | config IRQ_IMDMA_ERROR | |
| 31 | int "IMDMA Error (generic)" | |
| 32 | default 7 | |
| 33 | config IRQ_PPI0_ERROR | |
| 34 | int "PPI0 Error Interrupt" | |
| 35 | default 7 | |
| 36 | config IRQ_PPI1_ERROR | |
| 37 | int "PPI1 Error Interrupt" | |
| 38 | default 7 | |
| 39 | config IRQ_SPORT0_ERROR | |
| 40 | int "SPORT0 Error Interrupt" | |
| 41 | default 7 | |
| 42 | config IRQ_SPORT1_ERROR | |
| 43 | int "SPORT1 Error Interrupt" | |
| 44 | default 7 | |
| 45 | config IRQ_SPI_ERROR | |
| 46 | int "SPI Error Interrupt" | |
| 47 | default 7 | |
| 48 | config IRQ_UART_ERROR | |
| 49 | int "UART Error Interrupt" | |
| 50 | default 7 | |
| 51 | config IRQ_RESERVED_ERROR | |
| 52 | int "Reserved Interrupt" | |
| 53 | default 7 | |
| 54 | config IRQ_DMA1_0 | |
| 55 | int "DMA1 0 Interrupt(PPI1)" | |
| 56 | default 8 | |
| 57 | config IRQ_DMA1_1 | |
| 58 | int "DMA1 1 Interrupt(PPI2)" | |
| 59 | default 8 | |
| 60 | config IRQ_DMA1_2 | |
| 61 | int "DMA1 2 Interrupt" | |
| 62 | default 8 | |
| 63 | config IRQ_DMA1_3 | |
| 64 | int "DMA1 3 Interrupt" | |
| 65 | default 8 | |
| 66 | config IRQ_DMA1_4 | |
| 67 | int "DMA1 4 Interrupt" | |
| 68 | default 8 | |
| 69 | config IRQ_DMA1_5 | |
| 70 | int "DMA1 5 Interrupt" | |
| 71 | default 8 | |
| 72 | config IRQ_DMA1_6 | |
| 73 | int "DMA1 6 Interrupt" | |
| 74 | default 8 | |
| 75 | config IRQ_DMA1_7 | |
| 76 | int "DMA1 7 Interrupt" | |
| 77 | default 8 | |
| 78 | config IRQ_DMA1_8 | |
| 79 | int "DMA1 8 Interrupt" | |
| 80 | default 8 | |
| 81 | config IRQ_DMA1_9 | |
| 82 | int "DMA1 9 Interrupt" | |
| 83 | default 8 | |
| 84 | config IRQ_DMA1_10 | |
| 85 | int "DMA1 10 Interrupt" | |
| 86 | default 8 | |
| 87 | config IRQ_DMA1_11 | |
| 88 | int "DMA1 11 Interrupt" | |
| 89 | default 8 | |
| 90 | config IRQ_DMA2_0 | |
| 91 | int "DMA2 0 (SPORT0 RX)" | |
| 92 | default 9 | |
| 93 | config IRQ_DMA2_1 | |
| 94 | int "DMA2 1 (SPORT0 TX)" | |
| 95 | default 9 | |
| 96 | config IRQ_DMA2_2 | |
| 97 | int "DMA2 2 (SPORT1 RX)" | |
| 98 | default 9 | |
| 99 | config IRQ_DMA2_3 | |
| 100 | int "DMA2 3 (SPORT2 TX)" | |
| 101 | default 9 | |
| 102 | config IRQ_DMA2_4 | |
| 103 | int "DMA2 4 (SPI)" | |
| 104 | default 9 | |
| 105 | config IRQ_DMA2_5 | |
| 106 | int "DMA2 5 (UART RX)" | |
| 107 | default 9 | |
| 108 | config IRQ_DMA2_6 | |
| 109 | int "DMA2 6 (UART TX)" | |
| 110 | default 9 | |
| 111 | config IRQ_DMA2_7 | |
| 112 | int "DMA2 7 Interrupt" | |
| 113 | default 9 | |
| 114 | config IRQ_DMA2_8 | |
| 115 | int "DMA2 8 Interrupt" | |
| 116 | default 9 | |
| 117 | config IRQ_DMA2_9 | |
| 118 | int "DMA2 9 Interrupt" | |
| 119 | default 9 | |
| 120 | config IRQ_DMA2_10 | |
| 121 | int "DMA2 10 Interrupt" | |
| 122 | default 9 | |
| 123 | config IRQ_DMA2_11 | |
| 124 | int "DMA2 11 Interrupt" | |
| 125 | default 9 | |
| 126 | config IRQ_TIMER0 | |
| 127 | int "TIMER 0 Interrupt" | |
| 1fa9be72 | 128 | default 7 if TICKSOURCE_GPTMR0 |
| 6a01f230 | 129 | default 8 |
| 1394f032 BW |
130 | config IRQ_TIMER1 |
| 131 | int "TIMER 1 Interrupt" | |
| 132 | default 10 | |
| 133 | config IRQ_TIMER2 | |
| 134 | int "TIMER 2 Interrupt" | |
| 135 | default 10 | |
| 136 | config IRQ_TIMER3 | |
| 137 | int "TIMER 3 Interrupt" | |
| 138 | default 10 | |
| 139 | config IRQ_TIMER4 | |
| 140 | int "TIMER 4 Interrupt" | |
| 141 | default 10 | |
| 142 | config IRQ_TIMER5 | |
| 143 | int "TIMER 5 Interrupt" | |
| 144 | default 10 | |
| 145 | config IRQ_TIMER6 | |
| 146 | int "TIMER 6 Interrupt" | |
| 147 | default 10 | |
| 148 | config IRQ_TIMER7 | |
| 149 | int "TIMER 7 Interrupt" | |
| 150 | default 10 | |
| 151 | config IRQ_TIMER8 | |
| 152 | int "TIMER 8 Interrupt" | |
| 153 | default 10 | |
| 154 | config IRQ_TIMER9 | |
| 155 | int "TIMER 9 Interrupt" | |
| 156 | default 10 | |
| 157 | config IRQ_TIMER10 | |
| 158 | int "TIMER 10 Interrupt" | |
| 159 | default 10 | |
| 160 | config IRQ_TIMER11 | |
| 161 | int "TIMER 11 Interrupt" | |
| 162 | default 10 | |
| 163 | config IRQ_PROG0_INTA | |
| 164 | int "Programmable Flags0 A (8)" | |
| 165 | default 11 | |
| 166 | config IRQ_PROG0_INTB | |
| 167 | int "Programmable Flags0 B (8)" | |
| 168 | default 11 | |
| 169 | config IRQ_PROG1_INTA | |
| 170 | int "Programmable Flags1 A (8)" | |
| 171 | default 11 | |
| 172 | config IRQ_PROG1_INTB | |
| 173 | int "Programmable Flags1 B (8)" | |
| 174 | default 11 | |
| 175 | config IRQ_PROG2_INTA | |
| 176 | int "Programmable Flags2 A (8)" | |
| 177 | default 11 | |
| 178 | config IRQ_PROG2_INTB | |
| 179 | int "Programmable Flags2 B (8)" | |
| 180 | default 11 | |
| 181 | config IRQ_DMA1_WRRD0 | |
| 182 | int "MDMA1 0 write/read INT" | |
| 183 | default 8 | |
| 184 | config IRQ_DMA1_WRRD1 | |
| 185 | int "MDMA1 1 write/read INT" | |
| 186 | default 8 | |
| 187 | config IRQ_DMA2_WRRD0 | |
| 188 | int "MDMA2 0 write/read INT" | |
| 189 | default 9 | |
| 190 | config IRQ_DMA2_WRRD1 | |
| 191 | int "MDMA2 1 write/read INT" | |
| 192 | default 9 | |
| 193 | config IRQ_IMDMA_WRRD0 | |
| 194 | int "IMDMA 0 write/read INT" | |
| 195 | default 12 | |
| 196 | config IRQ_IMDMA_WRRD1 | |
| 197 | int "IMDMA 1 write/read INT" | |
| 198 | default 12 | |
| 199 | config IRQ_WDTIMER | |
| 200 | int "Watch Dog Timer" | |
| 201 | default 13 | |
| 202 | ||
| 203 | help | |
| 204 | Enter the priority numbers between 7-13 ONLY. Others are Reserved. | |
| 205 | This applies to all the above. It is not recommended to assign the | |
| 206 | highest priority number 7 to UART or any other device. | |
| 207 | ||
| 208 | endmenu | |
| 209 | ||
| 210 | endmenu | |
| 211 | ||
| 212 | endif |