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blackfin: adi gpio driver and pinctrl driver support
[deliverable/linux.git] / arch / blackfin / mach-bf609 / boards / ezkit.c
CommitLineData
22a82628
SZ		 1/*
2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
16#include <linux/irq.h>
17#include <linux/i2c.h>
18#include <linux/interrupt.h>
19#include <linux/usb/musb.h>
54e4ff4d
SZ		 20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinconf-generic.h>
22#include <linux/platform_data/pinctrl-adi2.h>
5e50175b 23#include <asm/bfin_spi3.h>
22a82628
SZ		 24#include <asm/dma.h>
25#include <asm/gpio.h>
26#include <asm/nand.h>
27#include <asm/dpmc.h>
28#include <asm/portmux.h>
29#include <asm/bfin_sdh.h>
30#include <linux/input.h>
31#include <linux/spi/ad7877.h>
32
33/*
34 * Name the Board for the /proc/cpuinfo
35 */
36const char bfin_board_name[] = "ADI BF609-EZKIT";
37
38/*
39 * Driver needs to know address, irq and flag pin.
40 */
41
42#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
43#include <linux/usb/isp1760.h>
44static struct resource bfin_isp1760_resources[] = {
45 [0] = {
46 .start = 0x2C0C0000,
47 .end = 0x2C0C0000 + 0xfffff,
48 .flags = IORESOURCE_MEM,
49 },
50 [1] = {
51 .start = IRQ_PG7,
52 .end = IRQ_PG7,
53 .flags = IORESOURCE_IRQ,
54 },
55};
56
57static struct isp1760_platform_data isp1760_priv = {
58 .is_isp1761 = 0,
59 .bus_width_16 = 1,
60 .port1_otg = 0,
61 .analog_oc = 0,
62 .dack_polarity_high = 0,
63 .dreq_polarity_high = 0,
64};
65
66static struct platform_device bfin_isp1760_device = {
67 .name = "isp1760",
68 .id = 0,
69 .dev = {
70 .platform_data = &isp1760_priv,
71 },
72 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
73 .resource = bfin_isp1760_resources,
74};
75#endif
76
77#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
78#include <asm/bfin_rotary.h>
79
80static struct bfin_rotary_platform_data bfin_rotary_data = {
81 /*.rotary_up_key = KEY_UP,*/
82 /*.rotary_down_key = KEY_DOWN,*/
83 .rotary_rel_code = REL_WHEEL,
84 .rotary_button_key = KEY_ENTER,
85 .debounce = 10, /* 0..17 */
86 .mode = ROT_QUAD_ENC | ROT_DEBE,
87};
88
89static struct resource bfin_rotary_resources[] = {
90 {
91 .start = IRQ_CNT,
92 .end = IRQ_CNT,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device bfin_rotary_device = {
98 .name = "bfin-rotary",
99 .id = -1,
100 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
101 .resource = bfin_rotary_resources,
102 .dev = {
103 .platform_data = &bfin_rotary_data,
104 },
105};
106#endif
107
108#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
109#include <linux/stmmac.h>
1d899fd6 110#include <linux/phy.h>
22a82628
SZ		 111
112static struct stmmac_mdio_bus_data phy_private_data = {
22a82628
SZ		 113 .phy_mask = 1,
114};
115
1d899fd6
SZ		 116static struct stmmac_dma_cfg eth_dma_cfg = {
117 .pbl = 2,
118};
119
120int stmmac_ptp_clk_init(struct platform_device *pdev)
121{
122 bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
123 return 0;
124}
125
22a82628 126static struct plat_stmmacenet_data eth_private_data = {
1d899fd6 127 .has_gmac = 1,
22a82628
SZ		 128 .bus_id = 0,
129 .enh_desc = 1,
130 .phy_addr = 1,
131 .mdio_bus_data = &phy_private_data,
1d899fd6
SZ		 132 .dma_cfg = &eth_dma_cfg,
133 .force_thresh_dma_mode = 1,
134 .interface = PHY_INTERFACE_MODE_RMII,
135 .init = stmmac_ptp_clk_init,
22a82628
SZ		 136};
137
138static struct platform_device bfin_eth_device = {
139 .name = "stmmaceth",
140 .id = 0,
141 .num_resources = 2,
142 .resource = (struct resource[]) {
143 {
144 .start = EMAC0_MACCFG,
145 .end = EMAC0_MACCFG + 0x1274,
146 .flags = IORESOURCE_MEM,
147 },
148 {
149 .name = "macirq",
150 .start = IRQ_EMAC0_STAT,
151 .end = IRQ_EMAC0_STAT,
152 .flags = IORESOURCE_IRQ,
153 },
154 },
155 .dev = {
6e1953e1 156 .power.can_wakeup = 1,
22a82628
SZ		 157 .platform_data = &eth_private_data,
158 }
159};
160#endif
161
162#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
163#include <linux/input/adxl34x.h>
164static const struct adxl34x_platform_data adxl34x_info = {
165 .x_axis_offset = 0,
166 .y_axis_offset = 0,
167 .z_axis_offset = 0,
168 .tap_threshold = 0x31,
169 .tap_duration = 0x10,
170 .tap_latency = 0x60,
171 .tap_window = 0xF0,
172 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
173 .act_axis_control = 0xFF,
174 .activity_threshold = 5,
175 .inactivity_threshold = 3,
176 .inactivity_time = 4,
177 .free_fall_threshold = 0x7,
178 .free_fall_time = 0x20,
179 .data_rate = 0x8,
180 .data_range = ADXL_FULL_RES,
181
182 .ev_type = EV_ABS,
183 .ev_code_x = ABS_X, /* EV_REL */
184 .ev_code_y = ABS_Y, /* EV_REL */
185 .ev_code_z = ABS_Z, /* EV_REL */
186
187 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
188
189/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
190/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
191 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
192 .fifo_mode = ADXL_FIFO_STREAM,
193 .orientation_enable = ADXL_EN_ORIENTATION_3D,
194 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
195 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
196 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
197 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
198};
199#endif
200
201#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
202static struct platform_device rtc_device = {
203 .name = "rtc-bfin",
204 .id = -1,
205};
206#endif
207
208#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
209#ifdef CONFIG_SERIAL_BFIN_UART0
210static struct resource bfin_uart0_resources[] = {
211 {
212 .start = UART0_REVID,
213 .end = UART0_RXDIV+4,
214 .flags = IORESOURCE_MEM,
215 },
216 {
217 .start = IRQ_UART0_TX,
218 .end = IRQ_UART0_TX,
219 .flags = IORESOURCE_IRQ,
220 },
221 {
222 .start = IRQ_UART0_RX,
223 .end = IRQ_UART0_RX,
224 .flags = IORESOURCE_IRQ,
225 },
226 {
227 .start = IRQ_UART0_STAT,
228 .end = IRQ_UART0_STAT,
229 .flags = IORESOURCE_IRQ,
230 },
231 {
232 .start = CH_UART0_TX,
233 .end = CH_UART0_TX,
234 .flags = IORESOURCE_DMA,
235 },
236 {
237 .start = CH_UART0_RX,
238 .end = CH_UART0_RX,
239 .flags = IORESOURCE_DMA,
240 },
241#ifdef CONFIG_BFIN_UART0_CTSRTS
242 { /* CTS pin -- 0 means not supported */
243 .start = GPIO_PD10,
244 .end = GPIO_PD10,
245 .flags = IORESOURCE_IO,
246 },
247 { /* RTS pin -- 0 means not supported */
248 .start = GPIO_PD9,
249 .end = GPIO_PD9,
250 .flags = IORESOURCE_IO,
251 },
252#endif
253};
254
255static unsigned short bfin_uart0_peripherals[] = {
256 P_UART0_TX, P_UART0_RX,
257#ifdef CONFIG_BFIN_UART0_CTSRTS
258 P_UART0_RTS, P_UART0_CTS,
259#endif
260 0
261};
262
263static struct platform_device bfin_uart0_device = {
264 .name = "bfin-uart",
265 .id = 0,
266 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
267 .resource = bfin_uart0_resources,
268 .dev = {
269 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
270 },
271};
272#endif
273#ifdef CONFIG_SERIAL_BFIN_UART1
274static struct resource bfin_uart1_resources[] = {
275 {
276 .start = UART1_REVID,
277 .end = UART1_RXDIV+4,
278 .flags = IORESOURCE_MEM,
279 },
280 {
281 .start = IRQ_UART1_TX,
282 .end = IRQ_UART1_TX,
283 .flags = IORESOURCE_IRQ,
284 },
285 {
286 .start = IRQ_UART1_RX,
287 .end = IRQ_UART1_RX,
288 .flags = IORESOURCE_IRQ,
289 },
290 {
291 .start = IRQ_UART1_STAT,
292 .end = IRQ_UART1_STAT,
293 .flags = IORESOURCE_IRQ,
294 },
295 {
296 .start = CH_UART1_TX,
297 .end = CH_UART1_TX,
298 .flags = IORESOURCE_DMA,
299 },
300 {
301 .start = CH_UART1_RX,
302 .end = CH_UART1_RX,
303 .flags = IORESOURCE_DMA,
304 },
305#ifdef CONFIG_BFIN_UART1_CTSRTS
306 { /* CTS pin -- 0 means not supported */
307 .start = GPIO_PG13,
308 .end = GPIO_PG13,
309 .flags = IORESOURCE_IO,
310 },
311 { /* RTS pin -- 0 means not supported */
312 .start = GPIO_PG10,
313 .end = GPIO_PG10,
314 .flags = IORESOURCE_IO,
315 },
316#endif
317};
318
319static unsigned short bfin_uart1_peripherals[] = {
320 P_UART1_TX, P_UART1_RX,
321#ifdef CONFIG_BFIN_UART1_CTSRTS
322 P_UART1_RTS, P_UART1_CTS,
323#endif
324 0
325};
326
327static struct platform_device bfin_uart1_device = {
328 .name = "bfin-uart",
329 .id = 1,
330 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
331 .resource = bfin_uart1_resources,
332 .dev = {
333 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
334 },
335};
336#endif
337#endif
338
339#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
340#ifdef CONFIG_BFIN_SIR0
341static struct resource bfin_sir0_resources[] = {
342 {
343 .start = 0xFFC00400,
344 .end = 0xFFC004FF,
345 .flags = IORESOURCE_MEM,
346 },
347 {
348 .start = IRQ_UART0_TX,
349 .end = IRQ_UART0_TX+1,
350 .flags = IORESOURCE_IRQ,
351 },
352 {
353 .start = CH_UART0_TX,
354 .end = CH_UART0_TX+1,
355 .flags = IORESOURCE_DMA,
356 },
357};
358static struct platform_device bfin_sir0_device = {
359 .name = "bfin_sir",
360 .id = 0,
361 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
362 .resource = bfin_sir0_resources,
363};
364#endif
365#ifdef CONFIG_BFIN_SIR1
366static struct resource bfin_sir1_resources[] = {
367 {
368 .start = 0xFFC02000,
369 .end = 0xFFC020FF,
370 .flags = IORESOURCE_MEM,
371 },
372 {
373 .start = IRQ_UART1_TX,
374 .end = IRQ_UART1_TX+1,
375 .flags = IORESOURCE_IRQ,
376 },
377 {
378 .start = CH_UART1_TX,
379 .end = CH_UART1_TX+1,
380 .flags = IORESOURCE_DMA,
381 },
382};
383static struct platform_device bfin_sir1_device = {
384 .name = "bfin_sir",
385 .id = 1,
386 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
387 .resource = bfin_sir1_resources,
388};
389#endif
390#endif
391
392#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
393static struct resource musb_resources[] = {
394 [0] = {
395 .start = 0xFFCC1000,
396 .end = 0xFFCC1398,
397 .flags = IORESOURCE_MEM,
398 },
399 [1] = { /* general IRQ */
400 .start = IRQ_USB_STAT,
401 .end = IRQ_USB_STAT,
402 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
403 .name = "mc"
404 },
405 [2] = { /* DMA IRQ */
406 .start = IRQ_USB_DMA,
407 .end = IRQ_USB_DMA,
408 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
409 .name = "dma"
410 },
411};
412
413static struct musb_hdrc_config musb_config = {
414 .multipoint = 1,
415 .dyn_fifo = 0,
416 .dma = 1,
417 .num_eps = 16,
418 .dma_channels = 8,
419 .clkin = 48, /* musb CLKIN in MHZ */
420};
421
422static struct musb_hdrc_platform_data musb_plat = {
423#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
424 .mode = MUSB_OTG,
425#elif defined(CONFIG_USB_MUSB_HDRC)
426 .mode = MUSB_HOST,
427#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
428 .mode = MUSB_PERIPHERAL,
429#endif
430 .config = &musb_config,
431};
432
433static u64 musb_dmamask = ~(u32)0;
434
435static struct platform_device musb_device = {
436 .name = "musb-blackfin",
437 .id = 0,
438 .dev = {
439 .dma_mask = &musb_dmamask,
440 .coherent_dma_mask = 0xffffffff,
441 .platform_data = &musb_plat,
442 },
443 .num_resources = ARRAY_SIZE(musb_resources),
444 .resource = musb_resources,
445};
446#endif
447
448#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
449#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
450static struct resource bfin_sport0_uart_resources[] = {
451 {
452 .start = SPORT0_TCR1,
453 .end = SPORT0_MRCS3+4,
454 .flags = IORESOURCE_MEM,
455 },
456 {
457 .start = IRQ_SPORT0_RX,
458 .end = IRQ_SPORT0_RX+1,
459 .flags = IORESOURCE_IRQ,
460 },
461 {
462 .start = IRQ_SPORT0_ERROR,
463 .end = IRQ_SPORT0_ERROR,
464 .flags = IORESOURCE_IRQ,
465 },
466};
467
468static unsigned short bfin_sport0_peripherals[] = {
469 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
470 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
471};
472
473static struct platform_device bfin_sport0_uart_device = {
474 .name = "bfin-sport-uart",
475 .id = 0,
476 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
477 .resource = bfin_sport0_uart_resources,
478 .dev = {
479 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
480 },
481};
482#endif
483#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
484static struct resource bfin_sport1_uart_resources[] = {
485 {
486 .start = SPORT1_TCR1,
487 .end = SPORT1_MRCS3+4,
488 .flags = IORESOURCE_MEM,
489 },
490 {
491 .start = IRQ_SPORT1_RX,
492 .end = IRQ_SPORT1_RX+1,
493 .flags = IORESOURCE_IRQ,
494 },
495 {
496 .start = IRQ_SPORT1_ERROR,
497 .end = IRQ_SPORT1_ERROR,
498 .flags = IORESOURCE_IRQ,
499 },
500};
501
502static unsigned short bfin_sport1_peripherals[] = {
503 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
504 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
505};
506
507static struct platform_device bfin_sport1_uart_device = {
508 .name = "bfin-sport-uart",
509 .id = 1,
510 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
511 .resource = bfin_sport1_uart_resources,
512 .dev = {
513 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
514 },
515};
516#endif
517#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
518static struct resource bfin_sport2_uart_resources[] = {
519 {
520 .start = SPORT2_TCR1,
521 .end = SPORT2_MRCS3+4,
522 .flags = IORESOURCE_MEM,
523 },
524 {
525 .start = IRQ_SPORT2_RX,
526 .end = IRQ_SPORT2_RX+1,
527 .flags = IORESOURCE_IRQ,
528 },
529 {
530 .start = IRQ_SPORT2_ERROR,
531 .end = IRQ_SPORT2_ERROR,
532 .flags = IORESOURCE_IRQ,
533 },
534};
535
536static unsigned short bfin_sport2_peripherals[] = {
537 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
538 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
539};
540
541static struct platform_device bfin_sport2_uart_device = {
542 .name = "bfin-sport-uart",
543 .id = 2,
544 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
545 .resource = bfin_sport2_uart_resources,
546 .dev = {
547 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
548 },
549};
550#endif
551#endif
552
553#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
554
555static unsigned short bfin_can0_peripherals[] = {
556 P_CAN0_RX, P_CAN0_TX, 0
557};
558
559static struct resource bfin_can0_resources[] = {
560 {
561 .start = 0xFFC00A00,
562 .end = 0xFFC00FFF,
563 .flags = IORESOURCE_MEM,
564 },
565 {
566 .start = IRQ_CAN0_RX,
567 .end = IRQ_CAN0_RX,
568 .flags = IORESOURCE_IRQ,
569 },
570 {
571 .start = IRQ_CAN0_TX,
572 .end = IRQ_CAN0_TX,
573 .flags = IORESOURCE_IRQ,
574 },
575 {
576 .start = IRQ_CAN0_STAT,
577 .end = IRQ_CAN0_STAT,
578 .flags = IORESOURCE_IRQ,
579 },
580};
581
582static struct platform_device bfin_can0_device = {
583 .name = "bfin_can",
584 .id = 0,
585 .num_resources = ARRAY_SIZE(bfin_can0_resources),
586 .resource = bfin_can0_resources,
587 .dev = {
588 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
589 },
590};
591
592#endif
593
594#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
595static struct mtd_partition partition_info[] = {
596 {
597 .name = "bootloader(nand)",
598 .offset = 0,
599 .size = 0x80000,
600 }, {
601 .name = "linux kernel(nand)",
602 .offset = MTDPART_OFS_APPEND,
603 .size = 4 * 1024 * 1024,
604 },
605 {
606 .name = "file system(nand)",
607 .offset = MTDPART_OFS_APPEND,
608 .size = MTDPART_SIZ_FULL,
609 },
610};
611
612static struct bf5xx_nand_platform bfin_nand_platform = {
613 .data_width = NFC_NWIDTH_8,
614 .partitions = partition_info,
615 .nr_partitions = ARRAY_SIZE(partition_info),
616 .rd_dly = 3,
617 .wr_dly = 3,
618};
619
620static struct resource bfin_nand_resources[] = {
621 {
622 .start = 0xFFC03B00,
623 .end = 0xFFC03B4F,
624 .flags = IORESOURCE_MEM,
625 },
626 {
627 .start = CH_NFC,
628 .end = CH_NFC,
629 .flags = IORESOURCE_IRQ,
630 },
631};
632
633static struct platform_device bfin_nand_device = {
634 .name = "bfin-nand",
635 .id = 0,
636 .num_resources = ARRAY_SIZE(bfin_nand_resources),
637 .resource = bfin_nand_resources,
638 .dev = {
639 .platform_data = &bfin_nand_platform,
640 },
641};
642#endif
643
644#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
645
646static struct bfin_sd_host bfin_sdh_data = {
647 .dma_chan = CH_RSI,
648 .irq_int0 = IRQ_RSI_INT0,
649 .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
650};
651
652static struct platform_device bfin_sdh_device = {
653 .name = "bfin-sdh",
654 .id = 0,
655 .dev = {
656 .platform_data = &bfin_sdh_data,
657 },
658};
659#endif
660
1c400939 661#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
22a82628
SZ		 662static struct mtd_partition ezkit_partitions[] = {
663 {
664 .name = "bootloader(nor)",
665 .size = 0x80000,
666 .offset = 0,
667 }, {
668 .name = "linux kernel(nor)",
669 .size = 0x400000,
670 .offset = MTDPART_OFS_APPEND,
671 }, {
672 .name = "file system(nor)",
673 .size = 0x1000000 - 0x80000 - 0x400000,
674 .offset = MTDPART_OFS_APPEND,
675 },
676};
677
54e4ff4d 678int bf609_nor_flash_init(struct platform_device *pdev)
22a82628
SZ		 679{
680#define CONFIG_SMC_GCTL_VAL 0x00000010
681 const unsigned short pins[] = {
682 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
683 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
684 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
685 };
686
687 peripheral_request_list(pins, "smc0");
688
689 bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
1c400939 690 bfin_write32(SMC_B0CTL, 0x01002011);
22a82628
SZ		 691 bfin_write32(SMC_B0TIM, 0x08170977);
692 bfin_write32(SMC_B0ETIM, 0x00092231);
693 return 0;
694}
695
0220874a
SM		 696void bf609_nor_flash_exit(struct platform_device *dev)
697{
698 const unsigned short pins[] = {
699 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
700 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
701 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
702 };
703
704 peripheral_free_list(pins);
705
706 bfin_write32(SMC_GCTL, 0);
0220874a
SM		 707}
708
22a82628
SZ		 709static struct physmap_flash_data ezkit_flash_data = {
710 .width = 2,
711 .parts = ezkit_partitions,
0220874a
SM		 712 .init = bf609_nor_flash_init,
713 .exit = bf609_nor_flash_exit,
22a82628 714 .nr_parts = ARRAY_SIZE(ezkit_partitions),
3fa8c4b0
BL		 715#ifdef CONFIG_ROMKERNEL
716 .probe_type = "map_rom",
717#endif
22a82628
SZ		 718};
719
720static struct resource ezkit_flash_resource = {
721 .start = 0xb0000000,
722 .end = 0xb0ffffff,
723 .flags = IORESOURCE_MEM,
724};
725
726static struct platform_device ezkit_flash_device = {
1c400939 727 .name = "physmap-flash",
22a82628
SZ		 728 .id = 0,
729 .dev = {
730 .platform_data = &ezkit_flash_data,
731 },
732 .num_resources = 1,
733 .resource = &ezkit_flash_resource,
734};
735#endif
736
737#if defined(CONFIG_MTD_M25P80) \
738 || defined(CONFIG_MTD_M25P80_MODULE)
739/* SPI flash chip (w25q32) */
740static struct mtd_partition bfin_spi_flash_partitions[] = {
741 {
742 .name = "bootloader(spi)",
743 .size = 0x00080000,
744 .offset = 0,
745 .mask_flags = MTD_CAP_ROM
746 }, {
747 .name = "linux kernel(spi)",
748 .size = 0x00180000,
749 .offset = MTDPART_OFS_APPEND,
750 }, {
751 .name = "file system(spi)",
752 .size = MTDPART_SIZ_FULL,
753 .offset = MTDPART_OFS_APPEND,
754 }
755};
756
757static struct flash_platform_data bfin_spi_flash_data = {
758 .name = "m25p80",
759 .parts = bfin_spi_flash_partitions,
760 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
761 .type = "w25q32",
762};
763
5e50175b 764static struct bfin_spi3_chip spi_flash_chip_info = {
22a82628
SZ		 765 .enable_dma = true, /* use dma transfer with this chip*/
766};
767#endif
768
769#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
5e50175b 770static struct bfin_spi3_chip spidev_chip_info = {
22a82628
SZ		 771 .enable_dma = true,
772};
773#endif
774
2984b52b 775#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
22a82628
SZ		 776static struct platform_device bfin_i2s_pcm = {
777 .name = "bfin-i2s-pcm-audio",
778 .id = -1,
779};
780#endif
781
782#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
783 defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
784#include <asm/bfin_sport3.h>
785static struct resource bfin_snd_resources[] = {
786 {
787 .start = SPORT0_CTL_A,
788 .end = SPORT0_CTL_A,
789 .flags = IORESOURCE_MEM,
790 },
791 {
792 .start = SPORT0_CTL_B,
793 .end = SPORT0_CTL_B,
794 .flags = IORESOURCE_MEM,
795 },
796 {
797 .start = CH_SPORT0_TX,
798 .end = CH_SPORT0_TX,
799 .flags = IORESOURCE_DMA,
800 },
801 {
802 .start = CH_SPORT0_RX,
803 .end = CH_SPORT0_RX,
804 .flags = IORESOURCE_DMA,
805 },
806 {
807 .start = IRQ_SPORT0_TX_STAT,
808 .end = IRQ_SPORT0_TX_STAT,
809 .flags = IORESOURCE_IRQ,
810 },
811 {
812 .start = IRQ_SPORT0_RX_STAT,
813 .end = IRQ_SPORT0_RX_STAT,
814 .flags = IORESOURCE_IRQ,
815 },
816};
817
818static const unsigned short bfin_snd_pin[] = {
819 P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
820 P_SPORT0_BFS, P_SPORT0_BD0, 0,
821};
822
823static struct bfin_snd_platform_data bfin_snd_data = {
824 .pin_req = bfin_snd_pin,
825};
826
827static struct platform_device bfin_i2s = {
828 .name = "bfin-i2s",
829 .num_resources = ARRAY_SIZE(bfin_snd_resources),
830 .resource = bfin_snd_resources,
831 .dev = {
832 .platform_data = &bfin_snd_data,
833 },
834};
835#endif
836
63f49dce
SJ		 837#if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
838 || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
839static const char * const ad1836_link[] = {
34f40955 840 "bfin-i2s.0",
63f49dce
SJ		 841 "spi0.76",
842};
843static struct platform_device bfin_ad1836_machine = {
844 .name = "bfin-snd-ad1836",
845 .id = -1,
846 .dev = {
847 .platform_data = (void *)ad1836_link,
848 },
849};
850#endif
851
22a82628
SZ		 852#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
853 defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
854static struct platform_device adau1761_device = {
855 .name = "bfin-eval-adau1x61",
856};
857#endif
858
859#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
860#include <sound/adau17x1.h>
861static struct adau1761_platform_data adau1761_info = {
862 .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
863 .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
864};
865#endif
866
867#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
868 || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
869#include <linux/videodev2.h>
870#include <media/blackfin/bfin_capture.h>
871#include <media/blackfin/ppi.h>
872
873static const unsigned short ppi_req[] = {
874 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
875 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
338881a5
SJ		 876 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
877 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
00afdbbf 878#if !defined(CONFIG_VIDEO_VS6624) && !defined(CONFIG_VIDEO_VS6624_MODULE)
338881a5
SJ		 879 P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
880 P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
00afdbbf 881#endif
22a82628
SZ		 882 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
883 0,
884};
885
886static const struct ppi_info ppi_info = {
887 .type = PPI_TYPE_EPPI3,
888 .dma_ch = CH_EPPI0_CH0,
889 .irq_err = IRQ_EPPI0_STAT,
890 .base = (void __iomem *)EPPI0_STAT,
891 .pin_req = ppi_req,
892};
893
894#if defined(CONFIG_VIDEO_VS6624) \
895 || defined(CONFIG_VIDEO_VS6624_MODULE)
896static struct v4l2_input vs6624_inputs[] = {
897 {
898 .index = 0,
899 .name = "Camera",
900 .type = V4L2_INPUT_TYPE_CAMERA,
901 .std = V4L2_STD_UNKNOWN,
902 },
903};
904
905static struct bcap_route vs6624_routes[] = {
906 {
907 .input = 0,
908 .output = 0,
909 },
910};
911
00afdbbf 912static const unsigned vs6624_ce_pin = GPIO_PE4;
22a82628
SZ		 913
914static struct bfin_capture_config bfin_capture_data = {
915 .card_name = "BF609",
916 .inputs = vs6624_inputs,
917 .num_inputs = ARRAY_SIZE(vs6624_inputs),
918 .routes = vs6624_routes,
919 .i2c_adapter_id = 0,
920 .board_info = {
921 .type = "vs6624",
922 .addr = 0x10,
923 .platform_data = (void *)&vs6624_ce_pin,
924 },
925 .ppi_info = &ppi_info,
926 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
927 | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
ac5bb893 928 .blank_pixels = 4,
22a82628
SZ		 929};
930#endif
931
338881a5
SJ		 932#if defined(CONFIG_VIDEO_ADV7842) \
933 || defined(CONFIG_VIDEO_ADV7842_MODULE)
934#include <media/adv7842.h>
935
936static struct v4l2_input adv7842_inputs[] = {
937 {
938 .index = 0,
939 .name = "Composite",
940 .type = V4L2_INPUT_TYPE_CAMERA,
941 .std = V4L2_STD_ALL,
688da5e8 942 .capabilities = V4L2_IN_CAP_STD,
338881a5
SJ		 943 },
944 {
945 .index = 1,
946 .name = "S-Video",
947 .type = V4L2_INPUT_TYPE_CAMERA,
948 .std = V4L2_STD_ALL,
688da5e8 949 .capabilities = V4L2_IN_CAP_STD,
338881a5
SJ		 950 },
951 {
952 .index = 2,
953 .name = "Component",
954 .type = V4L2_INPUT_TYPE_CAMERA,
a8451ed2 955 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
338881a5
SJ		 956 },
957 {
958 .index = 3,
959 .name = "VGA",
960 .type = V4L2_INPUT_TYPE_CAMERA,
a8451ed2 961 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
338881a5
SJ		 962 },
963 {
964 .index = 4,
965 .name = "HDMI",
966 .type = V4L2_INPUT_TYPE_CAMERA,
a8451ed2 967 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
338881a5
SJ		 968 },
969};
970
971static struct bcap_route adv7842_routes[] = {
972 {
973 .input = 3,
b5c00ae7 974 .output = 0,
688da5e8
SJ		 975 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
976 | EPPI_CTL_ACTIVE656),
338881a5
SJ		 977 },
978 {
979 .input = 4,
b5c00ae7 980 .output = 0,
338881a5
SJ		 981 },
982 {
983 .input = 2,
b5c00ae7 984 .output = 0,
338881a5
SJ		 985 },
986 {
987 .input = 1,
b5c00ae7 988 .output = 0,
338881a5
SJ		 989 },
990 {
991 .input = 0,
688da5e8
SJ		 992 .output = 1,
993 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
994 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
995 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
b5c00ae7
SJ		 996 },
997};
998
999static struct adv7842_output_format adv7842_opf[] = {
1000 {
1001 .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
1002 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
1003 .op_656_range = 1,
1004 .blank_data = 1,
1005 .insert_av_codes = 1,
338881a5 1006 },
688da5e8
SJ		 1007 {
1008 .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
1009 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
1010 .op_656_range = 1,
1011 .blank_data = 1,
1012 },
338881a5
SJ		 1013};
1014
1015static struct adv7842_platform_data adv7842_data = {
b5c00ae7
SJ		 1016 .opf = adv7842_opf,
1017 .num_opf = ARRAY_SIZE(adv7842_opf),
338881a5 1018 .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
338881a5
SJ		 1019 .prim_mode = ADV7842_PRIM_MODE_SDP,
1020 .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
1021 .inp_color_space = ADV7842_INP_COLOR_SPACE_AUTO,
e942d619
SJ		 1022 .i2c_sdp_io = 0x40,
1023 .i2c_sdp = 0x41,
1024 .i2c_cp = 0x42,
1025 .i2c_vdp = 0x43,
1026 .i2c_afe = 0x44,
1027 .i2c_hdmi = 0x45,
1028 .i2c_repeater = 0x46,
1029 .i2c_edid = 0x47,
1030 .i2c_infoframe = 0x48,
1031 .i2c_cec = 0x49,
1032 .i2c_avlink = 0x4a,
b5c00ae7 1033 .i2c_ex = 0x26,
338881a5
SJ		 1034};
1035
1036static struct bfin_capture_config bfin_capture_data = {
1037 .card_name = "BF609",
1038 .inputs = adv7842_inputs,
1039 .num_inputs = ARRAY_SIZE(adv7842_inputs),
1040 .routes = adv7842_routes,
1041 .i2c_adapter_id = 0,
1042 .board_info = {
1043 .type = "adv7842",
1044 .addr = 0x20,
1045 .platform_data = (void *)&adv7842_data,
1046 },
1047 .ppi_info = &ppi_info,
1048 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
1049 | EPPI_CTL_ACTIVE656),
1050};
1051#endif
1052
22a82628
SZ		 1053static struct platform_device bfin_capture_device = {
1054 .name = "bfin_capture",
1055 .dev = {
1056 .platform_data = &bfin_capture_data,
1057 },
1058};
1059#endif
1060
e942d619
SJ		 1061#if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
1062 || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
1063#include <linux/videodev2.h>
1064#include <media/blackfin/bfin_display.h>
1065#include <media/blackfin/ppi.h>
1066
1067static const unsigned short ppi_req_disp[] = {
1068 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
1069 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
1070 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
1071 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
1072 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
1073 0,
1074};
1075
1076static const struct ppi_info ppi_info = {
1077 .type = PPI_TYPE_EPPI3,
1078 .dma_ch = CH_EPPI0_CH0,
1079 .irq_err = IRQ_EPPI0_STAT,
1080 .base = (void __iomem *)EPPI0_STAT,
1081 .pin_req = ppi_req_disp,
1082};
1083
1084#if defined(CONFIG_VIDEO_ADV7511) \
1085 || defined(CONFIG_VIDEO_ADV7511_MODULE)
1086#include <media/adv7511.h>
1087
1088static struct v4l2_output adv7511_outputs[] = {
1089 {
1090 .index = 0,
1091 .name = "HDMI",
1092 .type = V4L2_INPUT_TYPE_CAMERA,
a8451ed2 1093 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
e942d619
SJ		 1094 },
1095};
1096
1097static struct disp_route adv7511_routes[] = {
1098 {
1099 .output = 0,
1100 },
1101};
1102
1103static struct adv7511_platform_data adv7511_data = {
1104 .edid_addr = 0x7e,
1105 .i2c_ex = 0x25,
1106};
1107
1108static struct bfin_display_config bfin_display_data = {
1109 .card_name = "BF609",
1110 .outputs = adv7511_outputs,
1111 .num_outputs = ARRAY_SIZE(adv7511_outputs),
1112 .routes = adv7511_routes,
1113 .i2c_adapter_id = 0,
1114 .board_info = {
1115 .type = "adv7511",
1116 .addr = 0x39,
1117 .platform_data = (void *)&adv7511_data,
1118 },
1119 .ppi_info = &ppi_info,
1120 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
1121 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
1122 | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
1123 | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1124};
1125#endif
1126
4940c53d
SJ		 1127#if IS_ENABLED(CONFIG_VIDEO_ADV7343)
1128#include <media/adv7343.h>
1129
1130static struct v4l2_output adv7343_outputs[] = {
1131 {
1132 .index = 0,
1133 .name = "Composite",
1134 .type = V4L2_OUTPUT_TYPE_ANALOG,
1135 .std = V4L2_STD_ALL,
1136 .capabilities = V4L2_OUT_CAP_STD,
1137 },
e5786092
SJ		 1138 {
1139 .index = 1,
1140 .name = "S-Video",
1141 .type = V4L2_OUTPUT_TYPE_ANALOG,
1142 .std = V4L2_STD_ALL,
1143 .capabilities = V4L2_OUT_CAP_STD,
1144 },
1145 {
1146 .index = 2,
1147 .name = "Component",
1148 .type = V4L2_OUTPUT_TYPE_ANALOG,
1149 .std = V4L2_STD_ALL,
1150 .capabilities = V4L2_OUT_CAP_STD,
1151 },
1152
4940c53d
SJ		 1153};
1154
1155static struct disp_route adv7343_routes[] = {
1156 {
e5786092
SJ		 1157 .output = ADV7343_COMPOSITE_ID,
1158 },
1159 {
1160 .output = ADV7343_SVIDEO_ID,
1161 },
1162 {
1163 .output = ADV7343_COMPONENT_ID,
4940c53d
SJ		 1164 },
1165};
1166
1167static struct adv7343_platform_data adv7343_data = {
1168 .mode_config = {
1169 .sleep_mode = false,
1170 .pll_control = false,
1171 .dac_1 = true,
1172 .dac_2 = true,
1173 .dac_3 = true,
1174 .dac_4 = true,
1175 .dac_5 = true,
1176 .dac_6 = true,
1177 },
1178 .sd_config = {
1179 .sd_dac_out1 = false,
1180 .sd_dac_out2 = false,
1181 },
1182};
1183
1184static struct bfin_display_config bfin_display_data = {
1185 .card_name = "BF609",
1186 .outputs = adv7343_outputs,
1187 .num_outputs = ARRAY_SIZE(adv7343_outputs),
1188 .routes = adv7343_routes,
1189 .i2c_adapter_id = 0,
1190 .board_info = {
1191 .type = "adv7343",
1192 .addr = 0x2b,
1193 .platform_data = (void *)&adv7343_data,
1194 },
1195 .ppi_info = &ppi_info_disp,
1196 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
1197 | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
1198 | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1199};
1200#endif
1201
e942d619
SJ		 1202static struct platform_device bfin_display_device = {
1203 .name = "bfin_display",
1204 .dev = {
1205 .platform_data = &bfin_display_data,
1206 },
1207};
1208#endif
1209
22a82628
SZ		 1210#if defined(CONFIG_BFIN_CRC)
1211#define BFIN_CRC_NAME "bfin-crc"
1212
1213static struct resource bfin_crc0_resources[] = {
1214 {
1215 .start = REG_CRC0_CTL,
1216 .end = REG_CRC0_REVID+4,
1217 .flags = IORESOURCE_MEM,
1218 },
1219 {
1220 .start = IRQ_CRC0_DCNTEXP,
1221 .end = IRQ_CRC0_DCNTEXP,
1222 .flags = IORESOURCE_IRQ,
1223 },
1224 {
1225 .start = CH_MEM_STREAM0_SRC_CRC0,
1226 .end = CH_MEM_STREAM0_SRC_CRC0,
1227 .flags = IORESOURCE_DMA,
1228 },
1229 {
1230 .start = CH_MEM_STREAM0_DEST_CRC0,
1231 .end = CH_MEM_STREAM0_DEST_CRC0,
1232 .flags = IORESOURCE_DMA,
1233 },
1234};
1235
1236static struct platform_device bfin_crc0_device = {
1237 .name = BFIN_CRC_NAME,
1238 .id = 0,
1239 .num_resources = ARRAY_SIZE(bfin_crc0_resources),
1240 .resource = bfin_crc0_resources,
1241};
1242
1243static struct resource bfin_crc1_resources[] = {
1244 {
1245 .start = REG_CRC1_CTL,
1246 .end = REG_CRC1_REVID+4,
1247 .flags = IORESOURCE_MEM,
1248 },
1249 {
1250 .start = IRQ_CRC1_DCNTEXP,
1251 .end = IRQ_CRC1_DCNTEXP,
1252 .flags = IORESOURCE_IRQ,
1253 },
1254 {
1255 .start = CH_MEM_STREAM1_SRC_CRC1,
1256 .end = CH_MEM_STREAM1_SRC_CRC1,
1257 .flags = IORESOURCE_DMA,
1258 },
1259 {
1260 .start = CH_MEM_STREAM1_DEST_CRC1,
1261 .end = CH_MEM_STREAM1_DEST_CRC1,
1262 .flags = IORESOURCE_DMA,
1263 },
1264};
1265
1266static struct platform_device bfin_crc1_device = {
1267 .name = BFIN_CRC_NAME,
1268 .id = 1,
1269 .num_resources = ARRAY_SIZE(bfin_crc1_resources),
1270 .resource = bfin_crc1_resources,
1271};
1272#endif
1273
c21e783b
SZ		 1274#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1275#define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
1276#define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
1277
1278static struct resource bfin_crypto_crc_resources[] = {
1279 {
1280 .start = REG_CRC0_CTL,
1281 .end = REG_CRC0_REVID+4,
1282 .flags = IORESOURCE_MEM,
1283 },
1284 {
1285 .start = IRQ_CRC0_DCNTEXP,
1286 .end = IRQ_CRC0_DCNTEXP,
1287 .flags = IORESOURCE_IRQ,
1288 },
1289 {
1290 .start = CH_MEM_STREAM0_SRC_CRC0,
1291 .end = CH_MEM_STREAM0_SRC_CRC0,
1292 .flags = IORESOURCE_DMA,
1293 },
c21e783b
SZ		 1294};
1295
1296static struct platform_device bfin_crypto_crc_device = {
1297 .name = BFIN_CRYPTO_CRC_NAME,
1298 .id = 0,
1299 .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
1300 .resource = bfin_crypto_crc_resources,
1301 .dev = {
1302 .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
1303 },
1304};
1305#endif
1306
22a82628
SZ		 1307#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1308static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1309 .model = 7877,
1310 .vref_delay_usecs = 50, /* internal, no capacitor */
1311 .x_plate_ohms = 419,
1312 .y_plate_ohms = 486,
1313 .pressure_max = 1000,
1314 .pressure_min = 0,
1315 .stopacq_polarity = 1,
1316 .first_conversion_delay = 3,
1317 .acquisition_time = 1,
1318 .averaging = 1,
1319 .pen_down_acc_interval = 1,
1320};
1321#endif
1322
54e4ff4d
SZ		 1323#ifdef CONFIG_PINCTRL_ADI2
1324
1325# define ADI_PINT_DEVNAME "adi-gpio-pint"
1326# define ADI_GPIO_DEVNAME "adi-gpio"
1327# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1328
1329static struct platform_device bfin_pinctrl_device = {
1330 .name = ADI_PINCTRL_DEVNAME,
1331 .id = 0,
1332};
1333
1334#ifdef CONFIG_PINCTRL_ADI2
1335
1336# define ADI_PINT_DEVNAME "adi-gpio-pint"
1337# define ADI_GPIO_DEVNAME "adi-gpio"
1338# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1339
1340static struct platform_device bfin_pinctrl_device = {
1341 .name = ADI_PINCTRL_DEVNAME,
1342 .id = 0,
1343};
1344
1345static struct resource bfin_pint0_resources[] = {
1346 {
1347 .start = PINT0_MASK_SET,
1348 .end = PINT0_LATCH + 3,
1349 .flags = IORESOURCE_MEM,
1350 },
1351 {
1352 .start = IRQ_PINT0,
1353 .end = IRQ_PINT0,
1354 .flags = IORESOURCE_IRQ,
1355 },
1356};
1357
1358static struct platform_device bfin_pint0_device = {
1359 .name = ADI_PINT_DEVNAME,
1360 .id = 0,
1361 .num_resources = ARRAY_SIZE(bfin_pint0_resources),
1362 .resource = bfin_pint0_resources,
1363};
1364
1365static struct resource bfin_pint1_resources[] = {
1366 {
1367 .start = PINT1_MASK_SET,
1368 .end = PINT1_LATCH + 3,
1369 .flags = IORESOURCE_MEM,
1370 },
1371 {
1372 .start = IRQ_PINT1,
1373 .end = IRQ_PINT1,
1374 .flags = IORESOURCE_IRQ,
1375 },
1376};
1377
1378static struct platform_device bfin_pint1_device = {
1379 .name = ADI_PINT_DEVNAME,
1380 .id = 1,
1381 .num_resources = ARRAY_SIZE(bfin_pint1_resources),
1382 .resource = bfin_pint1_resources,
1383};
1384
1385static struct resource bfin_pint2_resources[] = {
1386 {
1387 .start = PINT2_MASK_SET,
1388 .end = PINT2_LATCH + 3,
1389 .flags = IORESOURCE_MEM,
1390 },
1391 {
1392 .start = IRQ_PINT2,
1393 .end = IRQ_PINT2,
1394 .flags = IORESOURCE_IRQ,
1395 },
1396};
1397
1398static struct platform_device bfin_pint2_device = {
1399 .name = ADI_PINT_DEVNAME,
1400 .id = 2,
1401 .num_resources = ARRAY_SIZE(bfin_pint2_resources),
1402 .resource = bfin_pint2_resources,
1403};
1404
1405static struct resource bfin_pint3_resources[] = {
1406 {
1407 .start = PINT3_MASK_SET,
1408 .end = PINT3_LATCH + 3,
1409 .flags = IORESOURCE_MEM,
1410 },
1411 {
1412 .start = IRQ_PINT3,
1413 .end = IRQ_PINT3,
1414 .flags = IORESOURCE_IRQ,
1415 },
1416};
1417
1418static struct platform_device bfin_pint3_device = {
1419 .name = ADI_PINT_DEVNAME,
1420 .id = 3,
1421 .num_resources = ARRAY_SIZE(bfin_pint3_resources),
1422 .resource = bfin_pint3_resources,
1423};
1424
1425static struct resource bfin_pint4_resources[] = {
1426 {
1427 .start = PINT4_MASK_SET,
1428 .end = PINT4_LATCH + 3,
1429 .flags = IORESOURCE_MEM,
1430 },
1431 {
1432 .start = IRQ_PINT4,
1433 .end = IRQ_PINT4,
1434 .flags = IORESOURCE_IRQ,
1435 },
1436};
1437
1438static struct platform_device bfin_pint4_device = {
1439 .name = ADI_PINT_DEVNAME,
1440 .id = 4,
1441 .num_resources = ARRAY_SIZE(bfin_pint4_resources),
1442 .resource = bfin_pint4_resources,
1443};
1444
1445static struct resource bfin_pint5_resources[] = {
1446 {
1447 .start = PINT5_MASK_SET,
1448 .end = PINT5_LATCH + 3,
1449 .flags = IORESOURCE_MEM,
1450 },
1451 {
1452 .start = IRQ_PINT5,
1453 .end = IRQ_PINT5,
1454 .flags = IORESOURCE_IRQ,
1455 },
1456};
1457
1458static struct platform_device bfin_pint5_device = {
1459 .name = ADI_PINT_DEVNAME,
1460 .id = 5,
1461 .num_resources = ARRAY_SIZE(bfin_pint5_resources),
1462 .resource = bfin_pint5_resources,
1463};
1464
1465static struct resource bfin_gpa_resources[] = {
1466 {
1467 .start = PORTA_FER,
1468 .end = PORTA_MUX + 3,
1469 .flags = IORESOURCE_MEM,
1470 },
1471 { /* optional */
1472 .start = IRQ_PA0,
1473 .end = IRQ_PA0,
1474 .flags = IORESOURCE_IRQ,
1475 },
1476};
1477
1478static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
1479 .port_pin_base = GPIO_PA0,
1480 .port_width = GPIO_BANKSIZE,
1481 .pint_id = 0, /* PINT0 */
1482 .pint_assign = true, /* PINT upper 16 bit */
1483 .pint_map = 0, /* mapping mask in PINT */
1484};
1485
1486static struct platform_device bfin_gpa_device = {
1487 .name = ADI_GPIO_DEVNAME,
1488 .id = 0,
1489 .num_resources = ARRAY_SIZE(bfin_gpa_resources),
1490 .resource = bfin_gpa_resources,
1491 .dev = {
1492 .platform_data = &bfin_gpa_pdata, /* Passed to driver */
1493 },
1494};
1495
1496static struct resource bfin_gpb_resources[] = {
1497 {
1498 .start = PORTB_FER,
1499 .end = PORTB_MUX + 3,
1500 .flags = IORESOURCE_MEM,
1501 },
1502 {
1503 .start = IRQ_PB0,
1504 .end = IRQ_PB0,
1505 .flags = IORESOURCE_IRQ,
1506 },
1507};
1508
1509static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
1510 .port_pin_base = GPIO_PB0,
1511 .port_width = GPIO_BANKSIZE,
1512 .pint_id = 0,
1513 .pint_assign = false,
1514 .pint_map = 1,
1515};
1516
1517static struct platform_device bfin_gpb_device = {
1518 .name = ADI_GPIO_DEVNAME,
1519 .id = 1,
1520 .num_resources = ARRAY_SIZE(bfin_gpb_resources),
1521 .resource = bfin_gpb_resources,
1522 .dev = {
1523 .platform_data = &bfin_gpb_pdata, /* Passed to driver */
1524 },
1525};
1526
1527static struct resource bfin_gpc_resources[] = {
1528 {
1529 .start = PORTC_FER,
1530 .end = PORTC_MUX + 3,
1531 .flags = IORESOURCE_MEM,
1532 },
1533 {
1534 .start = IRQ_PC0,
1535 .end = IRQ_PC0,
1536 .flags = IORESOURCE_IRQ,
1537 },
1538};
1539
1540static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
1541 .port_pin_base = GPIO_PC0,
1542 .port_width = GPIO_BANKSIZE,
1543 .pint_id = 1,
1544 .pint_assign = false,
1545 .pint_map = 1,
1546};
1547
1548static struct platform_device bfin_gpc_device = {
1549 .name = ADI_GPIO_DEVNAME,
1550 .id = 2,
1551 .num_resources = ARRAY_SIZE(bfin_gpc_resources),
1552 .resource = bfin_gpc_resources,
1553 .dev = {
1554 .platform_data = &bfin_gpc_pdata, /* Passed to driver */
1555 },
1556};
1557
1558static struct resource bfin_gpd_resources[] = {
1559 {
1560 .start = PORTD_FER,
1561 .end = PORTD_MUX + 3,
1562 .flags = IORESOURCE_MEM,
1563 },
1564 {
1565 .start = IRQ_PD0,
1566 .end = IRQ_PD0,
1567 .flags = IORESOURCE_IRQ,
1568 },
1569};
1570
1571static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
1572 .port_pin_base = GPIO_PD0,
1573 .port_width = GPIO_BANKSIZE,
1574 .pint_id = 2,
1575 .pint_assign = false,
1576 .pint_map = 1,
1577};
1578
1579static struct platform_device bfin_gpd_device = {
1580 .name = ADI_GPIO_DEVNAME,
1581 .id = 3,
1582 .num_resources = ARRAY_SIZE(bfin_gpd_resources),
1583 .resource = bfin_gpd_resources,
1584 .dev = {
1585 .platform_data = &bfin_gpd_pdata, /* Passed to driver */
1586 },
1587};
1588
1589static struct resource bfin_gpe_resources[] = {
1590 {
1591 .start = PORTE_FER,
1592 .end = PORTE_MUX + 3,
1593 .flags = IORESOURCE_MEM,
1594 },
1595 {
1596 .start = IRQ_PE0,
1597 .end = IRQ_PE0,
1598 .flags = IORESOURCE_IRQ,
1599 },
1600};
1601
1602static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
1603 .port_pin_base = GPIO_PE0,
1604 .port_width = GPIO_BANKSIZE,
1605 .pint_id = 3,
1606 .pint_assign = false,
1607 .pint_map = 1,
1608};
1609
1610static struct platform_device bfin_gpe_device = {
1611 .name = ADI_GPIO_DEVNAME,
1612 .id = 4,
1613 .num_resources = ARRAY_SIZE(bfin_gpe_resources),
1614 .resource = bfin_gpe_resources,
1615 .dev = {
1616 .platform_data = &bfin_gpe_pdata, /* Passed to driver */
1617 },
1618};
1619
1620static struct resource bfin_gpf_resources[] = {
1621 {
1622 .start = PORTF_FER,
1623 .end = PORTF_MUX + 3,
1624 .flags = IORESOURCE_MEM,
1625 },
1626 {
1627 .start = IRQ_PF0,
1628 .end = IRQ_PF0,
1629 .flags = IORESOURCE_IRQ,
1630 },
1631};
1632
1633static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
1634 .port_pin_base = GPIO_PF0,
1635 .port_width = GPIO_BANKSIZE,
1636 .pint_id = 4,
1637 .pint_assign = false,
1638 .pint_map = 1,
1639};
1640
1641static struct platform_device bfin_gpf_device = {
1642 .name = ADI_GPIO_DEVNAME,
1643 .id = 5,
1644 .num_resources = ARRAY_SIZE(bfin_gpf_resources),
1645 .resource = bfin_gpf_resources,
1646 .dev = {
1647 .platform_data = &bfin_gpf_pdata, /* Passed to driver */
1648 },
1649};
1650
1651static struct resource bfin_gpg_resources[] = {
1652 {
1653 .start = PORTG_FER,
1654 .end = PORTG_MUX + 3,
1655 .flags = IORESOURCE_MEM,
1656 },
1657 {
1658 .start = IRQ_PG0,
1659 .end = IRQ_PG0,
1660 .flags = IORESOURCE_IRQ,
1661 },
1662};
1663
1664static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
1665 .port_pin_base = GPIO_PG0,
1666 .port_width = GPIO_BANKSIZE,
1667 .pint_id = 5,
1668 .pint_assign = false,
1669 .pint_map = 1,
1670};
1671
1672static struct platform_device bfin_gpg_device = {
1673 .name = ADI_GPIO_DEVNAME,
1674 .id = 6,
1675 .num_resources = ARRAY_SIZE(bfin_gpg_resources),
1676 .resource = bfin_gpg_resources,
1677 .dev = {
1678 .platform_data = &bfin_gpg_pdata, /* Passed to driver */
1679 },
1680};
1681
1682#endif
1683
bbca5c6d
SM		 1684#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1685#include <linux/input.h>
1686#include <linux/gpio_keys.h>
1687
1688static struct gpio_keys_button bfin_gpio_keys_table[] = {
1689 {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
1690 {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
1691};
1692
1693static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1694 .buttons = bfin_gpio_keys_table,
1695 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1696};
1697
1698static struct platform_device bfin_device_gpiokeys = {
1699 .name = "gpio-keys",
1700 .dev = {
1701 .platform_data = &bfin_gpio_keys_data,
1702 },
1703};
1704#endif
1705
22a82628
SZ		 1706static struct spi_board_info bfin_spi_board_info[] __initdata = {
1707#if defined(CONFIG_MTD_M25P80) \
1708 || defined(CONFIG_MTD_M25P80_MODULE)
1709 {
1710 /* the modalias must be the same as spi device driver name */
1711 .modalias = "m25p80", /* Name of spi_driver for this device */
1712 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1713 .bus_num = 0, /* Framework bus number */
54e4ff4d 1714 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
22a82628
SZ		 1715 .platform_data = &bfin_spi_flash_data,
1716 .controller_data = &spi_flash_chip_info,
1717 .mode = SPI_MODE_3,
1718 },
1719#endif
1720#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1721 {
1722 .modalias = "ad7877",
1723 .platform_data = &bfin_ad7877_ts_info,
2cdd7008 1724 .irq = IRQ_PD9,
22a82628
SZ		 1725 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1726 .bus_num = 0,
54e4ff4d 1727 .chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
22a82628
SZ		 1728 },
1729#endif
1730#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1731 {
1732 .modalias = "spidev",
1733 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1734 .bus_num = 0,
54e4ff4d 1735 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
22a82628
SZ		 1736 .controller_data = &spidev_chip_info,
1737 },
1738#endif
1739#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1740 {
1741 .modalias = "adxl34x",
1742 .platform_data = &adxl34x_info,
1743 .irq = IRQ_PC5,
1744 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1745 .bus_num = 1,
1746 .chip_select = 2,
1747 .mode = SPI_MODE_3,
1748 },
1749#endif
1750};
5e50175b 1751#if IS_ENABLED(CONFIG_SPI_BFIN_V3)
22a82628
SZ		 1752/* SPI (0) */
1753static struct resource bfin_spi0_resource[] = {
1754 {
1755 .start = SPI0_REGBASE,
1756 .end = SPI0_REGBASE + 0xFF,
1757 .flags = IORESOURCE_MEM,
1758 },
1759 {
1760 .start = CH_SPI0_TX,
1761 .end = CH_SPI0_TX,
1762 .flags = IORESOURCE_DMA,
1763 },
1764 {
1765 .start = CH_SPI0_RX,
1766 .end = CH_SPI0_RX,
1767 .flags = IORESOURCE_DMA,
1768 },
1769};
1770
1771/* SPI (1) */
1772static struct resource bfin_spi1_resource[] = {
1773 {
1774 .start = SPI1_REGBASE,
1775 .end = SPI1_REGBASE + 0xFF,
1776 .flags = IORESOURCE_MEM,
1777 },
1778 {
1779 .start = CH_SPI1_TX,
1780 .end = CH_SPI1_TX,
1781 .flags = IORESOURCE_DMA,
1782 },
1783 {
1784 .start = CH_SPI1_RX,
1785 .end = CH_SPI1_RX,
1786 .flags = IORESOURCE_DMA,
1787 },
1788
1789};
1790
1791/* SPI controller data */
5e50175b 1792static struct bfin_spi3_master bf60x_spi_master_info0 = {
2cdd7008 1793 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
22a82628
SZ		 1794 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1795};
1796
1797static struct platform_device bf60x_spi_master0 = {
5e50175b 1798 .name = "bfin-spi3",
22a82628
SZ		 1799 .id = 0, /* Bus number */
1800 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1801 .resource = bfin_spi0_resource,
1802 .dev = {
1803 .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
1804 },
1805};
1806
5e50175b 1807static struct bfin_spi3_master bf60x_spi_master_info1 = {
2cdd7008 1808 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
22a82628
SZ		 1809 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1810};
1811
1812static struct platform_device bf60x_spi_master1 = {
5e50175b 1813 .name = "bfin-spi3",
22a82628
SZ		 1814 .id = 1, /* Bus number */
1815 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1816 .resource = bfin_spi1_resource,
1817 .dev = {
1818 .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
1819 },
1820};
1821#endif /* spi master and devices */
1822
1823#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
cf93feb3
SZ		 1824static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1825
22a82628
SZ		 1826static struct resource bfin_twi0_resource[] = {
1827 [0] = {
1828 .start = TWI0_CLKDIV,
1829 .end = TWI0_CLKDIV + 0xFF,
1830 .flags = IORESOURCE_MEM,
1831 },
1832 [1] = {
1833 .start = IRQ_TWI0,
1834 .end = IRQ_TWI0,
1835 .flags = IORESOURCE_IRQ,
1836 },
1837};
1838
1839static struct platform_device i2c_bfin_twi0_device = {
1840 .name = "i2c-bfin-twi",
1841 .id = 0,
1842 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1843 .resource = bfin_twi0_resource,
cf93feb3
SZ		 1844 .dev = {
1845 .platform_data = &bfin_twi0_pins,
1846 },
22a82628
SZ		 1847};
1848
cf93feb3
SZ		 1849static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1850
22a82628
SZ		 1851static struct resource bfin_twi1_resource[] = {
1852 [0] = {
1853 .start = TWI1_CLKDIV,
1854 .end = TWI1_CLKDIV + 0xFF,
1855 .flags = IORESOURCE_MEM,
1856 },
1857 [1] = {
1858 .start = IRQ_TWI1,
1859 .end = IRQ_TWI1,
1860 .flags = IORESOURCE_IRQ,
1861 },
1862};
1863
1864static struct platform_device i2c_bfin_twi1_device = {
1865 .name = "i2c-bfin-twi",
1866 .id = 1,
1867 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1868 .resource = bfin_twi1_resource,
cf93feb3
SZ		 1869 .dev = {
1870 .platform_data = &bfin_twi1_pins,
1871 },
22a82628
SZ		 1872};
1873#endif
1874
1875static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1876#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1877 {
1878 I2C_BOARD_INFO("adxl34x", 0x53),
1879 .irq = IRQ_PC5,
1880 .platform_data = (void *)&adxl34x_info,
1881 },
1882#endif
1883#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
1884 {
1885 I2C_BOARD_INFO("adau1761", 0x38),
1886 .platform_data = (void *)&adau1761_info
1887 },
1888#endif
335dd559
SJ		 1889#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
1890 {
1891 I2C_BOARD_INFO("ssm2602", 0x1b),
1892 },
1893#endif
22a82628
SZ		 1894};
1895
1896static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1897};
1898
1899static const unsigned int cclk_vlev_datasheet[] =
1900{
1901/*
1902 * Internal VLEV BF54XSBBC1533
1903 ****temporarily using these values until data sheet is updated
1904 */
1905 VRPAIR(VLEV_085, 150000000),
1906 VRPAIR(VLEV_090, 250000000),
1907 VRPAIR(VLEV_110, 276000000),
1908 VRPAIR(VLEV_115, 301000000),
1909 VRPAIR(VLEV_120, 525000000),
1910 VRPAIR(VLEV_125, 550000000),
1911 VRPAIR(VLEV_130, 600000000),
1912};
1913
1914static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1915 .tuple_tab = cclk_vlev_datasheet,
1916 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1917 .vr_settling_time = 25 /* us */,
1918};
1919
1920static struct platform_device bfin_dpmc = {
1921 .name = "bfin dpmc",
1922 .dev = {
1923 .platform_data = &bfin_dmpc_vreg_data,
1924 },
1925};
1926
1927static struct platform_device *ezkit_devices[] __initdata = {
1928
1929 &bfin_dpmc,
54e4ff4d
SZ		 1930#if defined(CONFIG_PINCTRL_ADI2)
1931 &bfin_pinctrl_device,
1932 &bfin_pint0_device,
1933 &bfin_pint1_device,
1934 &bfin_pint2_device,
1935 &bfin_pint3_device,
1936 &bfin_pint4_device,
1937 &bfin_pint5_device,
1938 &bfin_gpa_device,
1939 &bfin_gpb_device,
1940 &bfin_gpc_device,
1941 &bfin_gpd_device,
1942 &bfin_gpe_device,
1943 &bfin_gpf_device,
1944 &bfin_gpg_device,
1945#endif
22a82628
SZ		 1946
1947#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1948 &rtc_device,
1949#endif
1950
1951#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1952#ifdef CONFIG_SERIAL_BFIN_UART0
1953 &bfin_uart0_device,
1954#endif
1955#ifdef CONFIG_SERIAL_BFIN_UART1
1956 &bfin_uart1_device,
1957#endif
1958#endif
1959
1960#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
1961#ifdef CONFIG_BFIN_SIR0
1962 &bfin_sir0_device,
1963#endif
1964#ifdef CONFIG_BFIN_SIR1
1965 &bfin_sir1_device,
1966#endif
1967#endif
1968
1969#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1970 &bfin_eth_device,
1971#endif
1972
1973#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1974 &musb_device,
1975#endif
1976
1977#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1978 &bfin_isp1760_device,
1979#endif
1980
1981#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1982#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1983 &bfin_sport0_uart_device,
1984#endif
1985#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1986 &bfin_sport1_uart_device,
1987#endif
1988#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1989 &bfin_sport2_uart_device,
1990#endif
1991#endif
1992
1993#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1994 &bfin_can0_device,
1995#endif
1996
1997#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1998 &bfin_nand_device,
1999#endif
2000
2001#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
2002 &bfin_sdh_device,
2003#endif
2004
5e50175b 2005#if IS_ENABLED(CONFIG_SPI_BFIN_V3)
22a82628
SZ		 2006 &bf60x_spi_master0,
2007 &bf60x_spi_master1,
2008#endif
2009
2010#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
2011 &bfin_rotary_device,
2012#endif
2013
2014#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
2015 &i2c_bfin_twi0_device,
2016#if !defined(CONFIG_BF542)
2017 &i2c_bfin_twi1_device,
2018#endif
2019#endif
2020
2021#if defined(CONFIG_BFIN_CRC)
2022 &bfin_crc0_device,
2023 &bfin_crc1_device,
2024#endif
c21e783b
SZ		 2025#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
2026 &bfin_crypto_crc_device,
2027#endif
22a82628
SZ		 2028
2029#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
2030 &bfin_device_gpiokeys,
2031#endif
2032
1c400939 2033#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
22a82628
SZ		 2034 &ezkit_flash_device,
2035#endif
2984b52b 2036#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
22a82628
SZ		 2037 &bfin_i2s_pcm,
2038#endif
2039#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
2040 defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
2041 &bfin_i2s,
2042#endif
63f49dce
SJ		 2043#if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \
2044 defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
2045 &bfin_ad1836_machine,
2046#endif
22a82628
SZ		 2047#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
2048 defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
2049 &adau1761_device,
2050#endif
2051#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
2052 || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
2053 &bfin_capture_device,
2054#endif
e942d619
SJ		 2055#if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
2056 || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
2057 &bfin_display_device,
2058#endif
2059
22a82628
SZ		 2060};
2061
54e4ff4d
SZ		 2062/* Pin control settings */
2063static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2064 /* per-device maps */
2065 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
2066 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
2067 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
2068 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
2069 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
2070 PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
2071 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
2072 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
2073 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
2074 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
2075 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
2076 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
2077 PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
2078 PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2", "pinctrl-adi2.0", NULL, "ppi2_16b"),
2079 PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2080#if defined(CONFIG_VIDEO_MT9M114) || defined(CONFIG_VIDEO_MT9M114_MODULE)
2081 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_8b"),
2082#elif defined(CONFIG_VIDEO_VS6624) || defined(CONFIG_VIDEO_VS6624_MODULE)
2083 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2084#else
2085 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_24b"),
2086#endif
2087 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
2088 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
2089 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
2090 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
2091 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
2092 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
2093};
2094
2095/* Pin control settings */
2096static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2097 /* per-device maps */
2098 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
2099#ifdef CONFIG_BFIN_UART0_CTSRTS
2100 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0_ctsrts"),
2101#endif
2102 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
2103#ifdef CONFIG_BFIN_UART1_CTSRTS
2104 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"),
2105#endif
2106 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
2107 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
2108 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
2109 PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
2110 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
2111 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
2112 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
2113 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
2114 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
2115 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
2116 PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
2117 PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2", "pinctrl-adi2.0", NULL, "ppi2_16b"),
2118 PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", NULL, "ppi2_16b"),
2119#if defined(CONFIG_VIDEO_MT9M114) || defined(CONFIG_VIDEO_MT9M114_MODULE)
2120 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_8b"),
2121#elif defined(CONFIG_VIDEO_VS6624) || defined(CONFIG_VIDEO_VS6624_MODULE)
2122 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2123#else
2124 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_24b"),
2125#endif
2126 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
2127 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
2128 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
2129 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
2130 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
2131 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
2132};
2133
22a82628
SZ		 2134static int __init ezkit_init(void)
2135{
2136 printk(KERN_INFO "%s(): registering device resources\n", __func__);
2137
54e4ff4d
SZ		 2138 /* Initialize pinmuxing */
2139 pinctrl_register_mappings(bfin_pinmux_map,
2140 ARRAY_SIZE(bfin_pinmux_map));
2141
22a82628
SZ		 2142 i2c_register_board_info(0, bfin_i2c_board_info0,
2143 ARRAY_SIZE(bfin_i2c_board_info0));
2144 i2c_register_board_info(1, bfin_i2c_board_info1,
2145 ARRAY_SIZE(bfin_i2c_board_info1));
2146
22a82628
SZ		 2147 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
2148
2149 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
2150
2151 return 0;
2152}
2153
2154arch_initcall(ezkit_init);
2155
2156static struct platform_device *ezkit_early_devices[] __initdata = {
2157#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
2158#ifdef CONFIG_SERIAL_BFIN_UART0
2159 &bfin_uart0_device,
2160#endif
2161#ifdef CONFIG_SERIAL_BFIN_UART1
2162 &bfin_uart1_device,
2163#endif
2164#endif
2165
2166#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
2167#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2168 &bfin_sport0_uart_device,
2169#endif
2170#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
2171 &bfin_sport1_uart_device,
2172#endif
2173#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
2174 &bfin_sport2_uart_device,
2175#endif
2176#endif
2177};
2178
2179void __init native_machine_early_platform_add_devices(void)
2180{
2181 printk(KERN_INFO "register early platform devices\n");
2182 early_platform_add_devices(ezkit_early_devices,
2183 ARRAY_SIZE(ezkit_early_devices));
2184}
Linux kernel - Deliverables
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