[deliverable/linux.git] / arch / blackfin / mach-common / dpmc_modes.S

/*
 * Copyright 2004-2008 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/linkage.h>
#include <asm/blackfin.h>
#include <asm/mach/irq.h>


.section .l1.text

ENTRY(_sleep_mode)
	[--SP] = ( R7:0, P5:0 );
	[--SP] =  RETS;

	call _set_sic_iwr;

	R0 = 0xFFFF (Z);
	call _set_rtc_istat;

	P0.H = hi(PLL_CTL);
	P0.L = lo(PLL_CTL);
	R1 = W[P0](z);
	BITSET (R1, 3);
	W[P0] = R1.L;

	CLI R2;
	SSYNC;
	IDLE;
	STI R2;

	call _test_pll_locked;

	R0 = IWR_ENABLE(0);
	R1 = IWR_DISABLE_ALL;
	R2 = IWR_DISABLE_ALL;

	call _set_sic_iwr;

	P0.H = hi(PLL_CTL);
	P0.L = lo(PLL_CTL);
	R7 = w[p0](z);
	BITCLR (R7, 3);
	BITCLR (R7, 5);
	w[p0] = R7.L;
	IDLE;
	call _test_pll_locked;

	RETS = [SP++];
	( R7:0, P5:0 ) = [SP++];
	RTS;

ENTRY(_hibernate_mode)
	[--SP] = ( R7:0, P5:0 );
	[--SP] =  RETS;

	call _set_sic_iwr;

	R0 = 0xFFFF (Z);
	call _set_rtc_istat;

	P0.H = hi(VR_CTL);
	P0.L = lo(VR_CTL);
	R1 = W[P0](z);
	BITSET (R1, 8);
	BITCLR (R1, 0);
	BITCLR (R1, 1);
	W[P0] = R1.L;
	SSYNC;

	CLI R2;
	IDLE;

	/* Actually, adding anything may not be necessary...SDRAM contents
	 * are lost
	 */

ENTRY(_deep_sleep)
	[--SP] = ( R7:0, P5:0 );
	[--SP] =  RETS;

	CLI R4;

	R0 = IWR_ENABLE(0);
	R1 = IWR_DISABLE_ALL;
	R2 = IWR_DISABLE_ALL;

	call _set_sic_iwr;

	call _set_dram_srfs;

	/* Clear all the interrupts,bits sticky */
	R0 = 0xFFFF (Z);
	call _set_rtc_istat

	P0.H = hi(PLL_CTL);
	P0.L = lo(PLL_CTL);
	R0 = W[P0](z);
	BITSET (R0, 5);
	W[P0] = R0.L;

	call _test_pll_locked;

	SSYNC;
	IDLE;

	call _unset_dram_srfs;

	call _test_pll_locked;

	R0 = IWR_ENABLE(0);
	R1 = IWR_DISABLE_ALL;
	R2 = IWR_DISABLE_ALL;

	call _set_sic_iwr;

	P0.H = hi(PLL_CTL);
	P0.L = lo(PLL_CTL);
	R0 = w[p0](z);
	BITCLR (R0, 3);
	BITCLR (R0, 5);
	BITCLR (R0, 8);
	w[p0] = R0;
	IDLE;
	call _test_pll_locked;

	STI R4;

	RETS = [SP++];
	( R7:0, P5:0 ) = [SP++];
	RTS;

ENTRY(_sleep_deeper)
	[--SP] = ( R7:0, P5:0 );
	[--SP] =  RETS;

	CLI R4;

	P3 = R0;
	P4 = R1;
	P5 = R2;

	R0 = IWR_ENABLE(0);
	R1 = IWR_DISABLE_ALL;
	R2 = IWR_DISABLE_ALL;

	call _set_sic_iwr;
	call _set_dram_srfs;	/* Set SDRAM Self Refresh */

	/* Clear all the interrupts,bits sticky */
	R0 = 0xFFFF (Z);
	call _set_rtc_istat;
	P0.H = hi(PLL_DIV);
	P0.L = lo(PLL_DIV);
	R6 = W[P0](z);
	R0.L = 0xF;
	W[P0] = R0.l;		/* Set Max VCO to SCLK divider */

	P0.H = hi(PLL_CTL);
	P0.L = lo(PLL_CTL);
	R5 = W[P0](z);
	R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
	W[P0] = R0.l;		/* Set Min CLKIN to VCO multiplier */

	SSYNC;
	IDLE;

	call _test_pll_locked;

	P0.H = hi(VR_CTL);
	P0.L = lo(VR_CTL);
	R7 = W[P0](z);
	R1 = 0x6;
	R1 <<= 16;
	R2 = 0x0404(Z);
	R1 = R1|R2;

	R2 = DEPOSIT(R7, R1);
	W[P0] = R2;		/* Set Min Core Voltage */

	SSYNC;
	IDLE;

	call _test_pll_locked;

	R0 = P3;
	R1 = P4;
	R3 = P5;
	call _set_sic_iwr;	/* Set Awake from IDLE */

	P0.H = hi(PLL_CTL);
	P0.L = lo(PLL_CTL);
	R0 = W[P0](z);
	BITSET (R0, 3);
	W[P0] = R0.L;		/* Turn CCLK OFF */
	SSYNC;
	IDLE;

	call _test_pll_locked;

	R0 = IWR_ENABLE(0);
	R1 = IWR_DISABLE_ALL;
	R2 = IWR_DISABLE_ALL;

	call _set_sic_iwr;	/* Set Awake from IDLE PLL */

	P0.H = hi(VR_CTL);
	P0.L = lo(VR_CTL);
	W[P0]= R7;

	SSYNC;
	IDLE;

	call _test_pll_locked;

	P0.H = hi(PLL_DIV);
	P0.L = lo(PLL_DIV);
	W[P0]= R6;		/* Restore CCLK and SCLK divider */

	P0.H = hi(PLL_CTL);
	P0.L = lo(PLL_CTL);
	w[p0] = R5;		/* Restore VCO multiplier */
	IDLE;
	call _test_pll_locked;

	call _unset_dram_srfs;	/* SDRAM Self Refresh Off */

	STI R4;

	RETS = [SP++];
	( R7:0, P5:0 ) = [SP++];
	RTS;

ENTRY(_set_dram_srfs)
	/*  set the dram to self refresh mode */
#if defined(CONFIG_BF54x)
	P0.H = hi(EBIU_RSTCTL);
	P0.L = lo(EBIU_RSTCTL);
	R2 = [P0];
	R3.H = hi(SRREQ);
	R3.L = lo(SRREQ);
#else
	P0.H = hi(EBIU_SDGCTL);
	P0.L = lo(EBIU_SDGCTL);
	R2 = [P0];
	R3.H = hi(SRFS);
	R3.L = lo(SRFS);
#endif
	R2 = R2|R3;
	[P0] = R2;
	ssync;
#if defined(CONFIG_BF54x)
.LSRR_MODE:
	R2 = [P0];
	CC = BITTST(R2, 4);
	if !CC JUMP .LSRR_MODE;
#endif
	RTS;

ENTRY(_unset_dram_srfs)
	/*  set the dram out of self refresh mode */
#if defined(CONFIG_BF54x)
	P0.H = hi(EBIU_RSTCTL);
	P0.L = lo(EBIU_RSTCTL);
	R2 = [P0];
	R3.H = hi(SRREQ);
	R3.L = lo(SRREQ);
#else
	P0.H = hi(EBIU_SDGCTL);
	P0.L = lo(EBIU_SDGCTL);
	R2 = [P0];
	R3.H = hi(SRFS);
	R3.L = lo(SRFS);
#endif
	R3 = ~R3;
	R2 = R2&R3;
	[P0] = R2;
	ssync;
	RTS;

ENTRY(_set_sic_iwr)
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)
	P0.H = hi(SIC_IWR0);
	P0.L = lo(SIC_IWR0);
	P1.H = hi(SIC_IWR1);
	P1.L = lo(SIC_IWR1);
	[P1] = R1;
#if defined(CONFIG_BF54x)
	P1.H = hi(SIC_IWR2);
	P1.L = lo(SIC_IWR2);
	[P1] = R2;
#endif
#else
	P0.H = hi(SIC_IWR);
	P0.L = lo(SIC_IWR);
#endif
	[P0] = R0;

	SSYNC;
	RTS;

ENTRY(_set_rtc_istat)
#ifndef CONFIG_BF561
	P0.H = hi(RTC_ISTAT);
	P0.L = lo(RTC_ISTAT);
	w[P0] = R0.L;
	SSYNC;
#endif
	RTS;

ENTRY(_test_pll_locked)
	P0.H = hi(PLL_STAT);
	P0.L = lo(PLL_STAT);
1:
	R0 = W[P0] (Z);
	CC = BITTST(R0,5);
	IF !CC JUMP 1b;
	RTS;
Commit	Line	Data
1394f032	1	/*
14b03204	2	* Copyright 2004-2008 Analog Devices Inc.
1394f032	3	*
14b03204	4	* Licensed under the GPL-2 or later.
1394f032 BW	5	*/
	6
	7	#include <linux/linkage.h>
	8	#include <asm/blackfin.h>
	9	#include <asm/mach/irq.h>
	10
1394f032 BW	11
	12	.section .l1.text
	13
	14	ENTRY(_sleep_mode)
	15	[--SP] = ( R7:0, P5:0 );
	16	[--SP] = RETS;
	17
	18	call _set_sic_iwr;
	19
	20	R0 = 0xFFFF (Z);
4521ef42	21	call _set_rtc_istat;
1394f032 BW	22
	23	P0.H = hi(PLL_CTL);
	24	P0.L = lo(PLL_CTL);
	25	R1 = W[P0](z);
	26	BITSET (R1, 3);
	27	W[P0] = R1.L;
	28
	29	CLI R2;
	30	SSYNC;
	31	IDLE;
	32	STI R2;
	33
	34	call _test_pll_locked;
	35
	36	R0 = IWR_ENABLE(0);
cfefe3c6 MH	37	R1 = IWR_DISABLE_ALL;
	38	R2 = IWR_DISABLE_ALL;
	39
1394f032 BW	40	call _set_sic_iwr;
	41
	42	P0.H = hi(PLL_CTL);
	43	P0.L = lo(PLL_CTL);
	44	R7 = w[p0](z);
	45	BITCLR (R7, 3);
	46	BITCLR (R7, 5);
	47	w[p0] = R7.L;
	48	IDLE;
	49	call _test_pll_locked;
	50
	51	RETS = [SP++];
	52	( R7:0, P5:0 ) = [SP++];
	53	RTS;
	54
	55	ENTRY(_hibernate_mode)
	56	[--SP] = ( R7:0, P5:0 );
	57	[--SP] = RETS;
	58
	59	call _set_sic_iwr;
	60
	61	R0 = 0xFFFF (Z);
4521ef42	62	call _set_rtc_istat;
1394f032 BW	63
	64	P0.H = hi(VR_CTL);
	65	P0.L = lo(VR_CTL);
	66	R1 = W[P0](z);
	67	BITSET (R1, 8);
	68	BITCLR (R1, 0);
	69	BITCLR (R1, 1);
	70	W[P0] = R1.L;
	71	SSYNC;
	72
	73	CLI R2;
	74	IDLE;
	75
	76	/* Actually, adding anything may not be necessary...SDRAM contents
	77	* are lost
	78	*/
	79
	80	ENTRY(_deep_sleep)
	81	[--SP] = ( R7:0, P5:0 );
	82	[--SP] = RETS;
	83
	84	CLI R4;
	85
cfefe3c6 MH	86	R0 = IWR_ENABLE(0);
	87	R1 = IWR_DISABLE_ALL;
	88	R2 = IWR_DISABLE_ALL;
	89
1394f032 BW	90	call _set_sic_iwr;
1394f032 BW	91
fb5f0049	92	call _set_dram_srfs;
1394f032 BW	93
	94	/* Clear all the interrupts,bits sticky */
	95	R0 = 0xFFFF (Z);
	96	call _set_rtc_istat
	97
	98	P0.H = hi(PLL_CTL);
	99	P0.L = lo(PLL_CTL);
	100	R0 = W[P0](z);
	101	BITSET (R0, 5);
	102	W[P0] = R0.L;
	103
	104	call _test_pll_locked;
	105
	106	SSYNC;
	107	IDLE;
	108
fb5f0049	109	call _unset_dram_srfs;
1394f032 BW	110
	111	call _test_pll_locked;
	112
	113	R0 = IWR_ENABLE(0);
cfefe3c6 MH	114	R1 = IWR_DISABLE_ALL;
	115	R2 = IWR_DISABLE_ALL;
	116
1394f032 BW	117	call _set_sic_iwr;
	118
	119	P0.H = hi(PLL_CTL);
	120	P0.L = lo(PLL_CTL);
	121	R0 = w[p0](z);
	122	BITCLR (R0, 3);
	123	BITCLR (R0, 5);
	124	BITCLR (R0, 8);
	125	w[p0] = R0;
	126	IDLE;
	127	call _test_pll_locked;
	128
	129	STI R4;
	130
	131	RETS = [SP++];
	132	( R7:0, P5:0 ) = [SP++];
	133	RTS;
	134
	135	ENTRY(_sleep_deeper)
	136	[--SP] = ( R7:0, P5:0 );
	137	[--SP] = RETS;
	138
	139	CLI R4;
	140
	141	P3 = R0;
cfefe3c6 MH	142	P4 = R1;
	143	P5 = R2;
	144
1394f032	145	R0 = IWR_ENABLE(0);
cfefe3c6 MH	146	R1 = IWR_DISABLE_ALL;
	147	R2 = IWR_DISABLE_ALL;
	148
1394f032	149	call _set_sic_iwr;
4521ef42	150	call _set_dram_srfs; /* Set SDRAM Self Refresh */
1394f032 BW	151
	152	/* Clear all the interrupts,bits sticky */
	153	R0 = 0xFFFF (Z);
4521ef42	154	call _set_rtc_istat;
1394f032 BW	155	P0.H = hi(PLL_DIV);
	156	P0.L = lo(PLL_DIV);
	157	R6 = W[P0](z);
	158	R0.L = 0xF;
4521ef42	159	W[P0] = R0.l; /* Set Max VCO to SCLK divider */
1394f032 BW	160
	161	P0.H = hi(PLL_CTL);
	162	P0.L = lo(PLL_CTL);
	163	R5 = W[P0](z);
f16295e7	164	R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
4521ef42	165	W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
1394f032 BW	166
	167	SSYNC;
	168	IDLE;
	169
	170	call _test_pll_locked;
	171
	172	P0.H = hi(VR_CTL);
	173	P0.L = lo(VR_CTL);
	174	R7 = W[P0](z);
	175	R1 = 0x6;
	176	R1 <<= 16;
	177	R2 = 0x0404(Z);
	178	R1 = R1\|R2;
	179
	180	R2 = DEPOSIT(R7, R1);
4521ef42	181	W[P0] = R2; /* Set Min Core Voltage */
1394f032 BW	182
	183	SSYNC;
	184	IDLE;
	185
	186	call _test_pll_locked;
	187
4521ef42	188	R0 = P3;
cfefe3c6 MH	189	R1 = P4;
cfefe3c6 MH	190	R3 = P5;
4521ef42 MH	191	call _set_sic_iwr; /* Set Awake from IDLE */
4521ef42 MH	192
1394f032 BW	193	P0.H = hi(PLL_CTL);
	194	P0.L = lo(PLL_CTL);
	195	R0 = W[P0](z);
	196	BITSET (R0, 3);
4521ef42	197	W[P0] = R0.L; /* Turn CCLK OFF */
1394f032 BW	198	SSYNC;
	199	IDLE;
	200
	201	call _test_pll_locked;
	202
	203	R0 = IWR_ENABLE(0);
cfefe3c6 MH	204	R1 = IWR_DISABLE_ALL;
	205	R2 = IWR_DISABLE_ALL;
	206
4521ef42	207	call _set_sic_iwr; /* Set Awake from IDLE PLL */
1394f032 BW	208
	209	P0.H = hi(VR_CTL);
	210	P0.L = lo(VR_CTL);
	211	W[P0]= R7;
	212
	213	SSYNC;
	214	IDLE;
	215
	216	call _test_pll_locked;
	217
	218	P0.H = hi(PLL_DIV);
	219	P0.L = lo(PLL_DIV);
4521ef42	220	W[P0]= R6; /* Restore CCLK and SCLK divider */
1394f032 BW	221
	222	P0.H = hi(PLL_CTL);
	223	P0.L = lo(PLL_CTL);
4521ef42	224	w[p0] = R5; /* Restore VCO multiplier */
1394f032 BW	225	IDLE;
	226	call _test_pll_locked;
	227
4521ef42	228	call _unset_dram_srfs; /* SDRAM Self Refresh Off */
1394f032 BW	229
	230	STI R4;
	231
	232	RETS = [SP++];
	233	( R7:0, P5:0 ) = [SP++];
	234	RTS;
	235
fb5f0049 SZ	236	ENTRY(_set_dram_srfs)
	237	/* set the dram to self refresh mode */
	238	#if defined(CONFIG_BF54x)
	239	P0.H = hi(EBIU_RSTCTL);
	240	P0.L = lo(EBIU_RSTCTL);
	241	R2 = [P0];
	242	R3.H = hi(SRREQ);
	243	R3.L = lo(SRREQ);
	244	#else
1394f032 BW	245	P0.H = hi(EBIU_SDGCTL);
	246	P0.L = lo(EBIU_SDGCTL);
	247	R2 = [P0];
	248	R3.H = hi(SRFS);
	249	R3.L = lo(SRFS);
fb5f0049	250	#endif
1394f032 BW	251	R2 = R2\|R3;
	252	[P0] = R2;
	253	ssync;
fb5f0049 SZ	254	#if defined(CONFIG_BF54x)
	255	.LSRR_MODE:
	256	R2 = [P0];
	257	CC = BITTST(R2, 4);
	258	if !CC JUMP .LSRR_MODE;
	259	#endif
1394f032 BW	260	RTS;
1394f032 BW	261
fb5f0049 SZ	262	ENTRY(_unset_dram_srfs)
	263	/* set the dram out of self refresh mode */
	264	#if defined(CONFIG_BF54x)
	265	P0.H = hi(EBIU_RSTCTL);
	266	P0.L = lo(EBIU_RSTCTL);
	267	R2 = [P0];
	268	R3.H = hi(SRREQ);
	269	R3.L = lo(SRREQ);
	270	#else
1394f032 BW	271	P0.H = hi(EBIU_SDGCTL);
	272	P0.L = lo(EBIU_SDGCTL);
	273	R2 = [P0];
	274	R3.H = hi(SRFS);
	275	R3.L = lo(SRFS);
fb5f0049	276	#endif
1394f032 BW	277	R3 = ~R3;
	278	R2 = R2&R3;
	279	[P0] = R2;
	280	ssync;
	281	RTS;
	282
	283	ENTRY(_set_sic_iwr)
cfefe3c6	284	#if defined(CONFIG_BF54x) \|\| defined(CONFIG_BF52x) \|\| defined(CONFIG_BF561)
fb5f0049 SZ	285	P0.H = hi(SIC_IWR0);
fb5f0049 SZ	286	P0.L = lo(SIC_IWR0);
cfefe3c6 MH	287	P1.H = hi(SIC_IWR1);
	288	P1.L = lo(SIC_IWR1);
	289	[P1] = R1;
	290	#if defined(CONFIG_BF54x)
	291	P1.H = hi(SIC_IWR2);
	292	P1.L = lo(SIC_IWR2);
	293	[P1] = R2;
	294	#endif
fb5f0049	295	#else
1394f032 BW	296	P0.H = hi(SIC_IWR);
1394f032 BW	297	P0.L = lo(SIC_IWR);
fb5f0049	298	#endif
1394f032	299	[P0] = R0;
cfefe3c6	300
1394f032 BW	301	SSYNC;
	302	RTS;
	303
	304	ENTRY(_set_rtc_istat)
3927819d	305	#ifndef CONFIG_BF561
1394f032 BW	306	P0.H = hi(RTC_ISTAT);
	307	P0.L = lo(RTC_ISTAT);
	308	w[P0] = R0.L;
	309	SSYNC;
3927819d	310	#endif
1394f032 BW	311	RTS;
	312
	313	ENTRY(_test_pll_locked)
	314	P0.H = hi(PLL_STAT);
	315	P0.L = lo(PLL_STAT);
	316	1:
	317	R0 = W[P0] (Z);
	318	CC = BITTST(R0,5);
	319	IF !CC JUMP 1b;
	320	RTS;