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1394f032 | 1 | /* |
14b03204 | 2 | * Copyright 2004-2008 Analog Devices Inc. |
1394f032 | 3 | * |
14b03204 | 4 | * Licensed under the GPL-2 or later. |
1394f032 BW |
5 | */ |
6 | ||
7 | #include <linux/linkage.h> | |
8 | #include <asm/blackfin.h> | |
639f6571 | 9 | #include <mach/irq.h> |
1efc80b5 | 10 | #include <asm/dpmc.h> |
1394f032 BW |
11 | |
12 | .section .l1.text | |
13 | ||
14 | ENTRY(_sleep_mode) | |
15 | [--SP] = ( R7:0, P5:0 ); | |
16 | [--SP] = RETS; | |
17 | ||
18 | call _set_sic_iwr; | |
19 | ||
20 | R0 = 0xFFFF (Z); | |
4521ef42 | 21 | call _set_rtc_istat; |
1394f032 BW |
22 | |
23 | P0.H = hi(PLL_CTL); | |
24 | P0.L = lo(PLL_CTL); | |
25 | R1 = W[P0](z); | |
26 | BITSET (R1, 3); | |
27 | W[P0] = R1.L; | |
28 | ||
29 | CLI R2; | |
30 | SSYNC; | |
31 | IDLE; | |
32 | STI R2; | |
33 | ||
34 | call _test_pll_locked; | |
35 | ||
36 | R0 = IWR_ENABLE(0); | |
cfefe3c6 MH |
37 | R1 = IWR_DISABLE_ALL; |
38 | R2 = IWR_DISABLE_ALL; | |
39 | ||
1394f032 BW |
40 | call _set_sic_iwr; |
41 | ||
42 | P0.H = hi(PLL_CTL); | |
43 | P0.L = lo(PLL_CTL); | |
44 | R7 = w[p0](z); | |
45 | BITCLR (R7, 3); | |
46 | BITCLR (R7, 5); | |
47 | w[p0] = R7.L; | |
48 | IDLE; | |
49 | call _test_pll_locked; | |
50 | ||
51 | RETS = [SP++]; | |
52 | ( R7:0, P5:0 ) = [SP++]; | |
53 | RTS; | |
1a8caeeb | 54 | ENDPROC(_sleep_mode) |
1394f032 BW |
55 | |
56 | ENTRY(_hibernate_mode) | |
57 | [--SP] = ( R7:0, P5:0 ); | |
58 | [--SP] = RETS; | |
59 | ||
1efc80b5 MH |
60 | R3 = R0; |
61 | R0 = IWR_DISABLE_ALL; | |
62 | R1 = IWR_DISABLE_ALL; | |
63 | R2 = IWR_DISABLE_ALL; | |
1394f032 | 64 | call _set_sic_iwr; |
1efc80b5 MH |
65 | call _set_dram_srfs; |
66 | SSYNC; | |
1394f032 BW |
67 | |
68 | R0 = 0xFFFF (Z); | |
4521ef42 | 69 | call _set_rtc_istat; |
1394f032 BW |
70 | |
71 | P0.H = hi(VR_CTL); | |
72 | P0.L = lo(VR_CTL); | |
1394f032 | 73 | |
1efc80b5 | 74 | W[P0] = R3.L; |
1394f032 BW |
75 | CLI R2; |
76 | IDLE; | |
1efc80b5 MH |
77 | .Lforever: |
78 | jump .Lforever; | |
1a8caeeb | 79 | ENDPROC(_hibernate_mode) |
1394f032 | 80 | |
1394f032 BW |
81 | ENTRY(_sleep_deeper) |
82 | [--SP] = ( R7:0, P5:0 ); | |
83 | [--SP] = RETS; | |
84 | ||
85 | CLI R4; | |
86 | ||
87 | P3 = R0; | |
cfefe3c6 MH |
88 | P4 = R1; |
89 | P5 = R2; | |
90 | ||
1394f032 | 91 | R0 = IWR_ENABLE(0); |
cfefe3c6 MH |
92 | R1 = IWR_DISABLE_ALL; |
93 | R2 = IWR_DISABLE_ALL; | |
94 | ||
1394f032 | 95 | call _set_sic_iwr; |
4521ef42 | 96 | call _set_dram_srfs; /* Set SDRAM Self Refresh */ |
1394f032 BW |
97 | |
98 | /* Clear all the interrupts,bits sticky */ | |
99 | R0 = 0xFFFF (Z); | |
4521ef42 | 100 | call _set_rtc_istat; |
1394f032 BW |
101 | P0.H = hi(PLL_DIV); |
102 | P0.L = lo(PLL_DIV); | |
103 | R6 = W[P0](z); | |
104 | R0.L = 0xF; | |
4521ef42 | 105 | W[P0] = R0.l; /* Set Max VCO to SCLK divider */ |
1394f032 BW |
106 | |
107 | P0.H = hi(PLL_CTL); | |
108 | P0.L = lo(PLL_CTL); | |
109 | R5 = W[P0](z); | |
f16295e7 | 110 | R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9; |
4521ef42 | 111 | W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */ |
1394f032 BW |
112 | |
113 | SSYNC; | |
114 | IDLE; | |
115 | ||
116 | call _test_pll_locked; | |
117 | ||
118 | P0.H = hi(VR_CTL); | |
119 | P0.L = lo(VR_CTL); | |
120 | R7 = W[P0](z); | |
121 | R1 = 0x6; | |
122 | R1 <<= 16; | |
123 | R2 = 0x0404(Z); | |
124 | R1 = R1|R2; | |
125 | ||
126 | R2 = DEPOSIT(R7, R1); | |
4521ef42 | 127 | W[P0] = R2; /* Set Min Core Voltage */ |
1394f032 BW |
128 | |
129 | SSYNC; | |
130 | IDLE; | |
131 | ||
132 | call _test_pll_locked; | |
133 | ||
4521ef42 | 134 | R0 = P3; |
cfefe3c6 MH |
135 | R1 = P4; |
136 | R3 = P5; | |
4521ef42 MH |
137 | call _set_sic_iwr; /* Set Awake from IDLE */ |
138 | ||
1394f032 BW |
139 | P0.H = hi(PLL_CTL); |
140 | P0.L = lo(PLL_CTL); | |
141 | R0 = W[P0](z); | |
142 | BITSET (R0, 3); | |
4521ef42 | 143 | W[P0] = R0.L; /* Turn CCLK OFF */ |
1394f032 BW |
144 | SSYNC; |
145 | IDLE; | |
146 | ||
147 | call _test_pll_locked; | |
148 | ||
149 | R0 = IWR_ENABLE(0); | |
cfefe3c6 MH |
150 | R1 = IWR_DISABLE_ALL; |
151 | R2 = IWR_DISABLE_ALL; | |
152 | ||
4521ef42 | 153 | call _set_sic_iwr; /* Set Awake from IDLE PLL */ |
1394f032 BW |
154 | |
155 | P0.H = hi(VR_CTL); | |
156 | P0.L = lo(VR_CTL); | |
157 | W[P0]= R7; | |
158 | ||
159 | SSYNC; | |
160 | IDLE; | |
161 | ||
162 | call _test_pll_locked; | |
163 | ||
164 | P0.H = hi(PLL_DIV); | |
165 | P0.L = lo(PLL_DIV); | |
4521ef42 | 166 | W[P0]= R6; /* Restore CCLK and SCLK divider */ |
1394f032 BW |
167 | |
168 | P0.H = hi(PLL_CTL); | |
169 | P0.L = lo(PLL_CTL); | |
4521ef42 | 170 | w[p0] = R5; /* Restore VCO multiplier */ |
1394f032 BW |
171 | IDLE; |
172 | call _test_pll_locked; | |
173 | ||
4521ef42 | 174 | call _unset_dram_srfs; /* SDRAM Self Refresh Off */ |
1394f032 BW |
175 | |
176 | STI R4; | |
177 | ||
178 | RETS = [SP++]; | |
179 | ( R7:0, P5:0 ) = [SP++]; | |
180 | RTS; | |
1a8caeeb | 181 | ENDPROC(_sleep_deeper) |
1efc80b5 | 182 | |
fb5f0049 SZ |
183 | ENTRY(_set_dram_srfs) |
184 | /* set the dram to self refresh mode */ | |
1efc80b5 MH |
185 | SSYNC; |
186 | #if defined(EBIU_RSTCTL) /* DDR */ | |
fb5f0049 SZ |
187 | P0.H = hi(EBIU_RSTCTL); |
188 | P0.L = lo(EBIU_RSTCTL); | |
189 | R2 = [P0]; | |
1efc80b5 MH |
190 | BITSET(R2, 3); /* SRREQ enter self-refresh mode */ |
191 | [P0] = R2; | |
192 | SSYNC; | |
193 | 1: | |
194 | R2 = [P0]; | |
195 | CC = BITTST(R2, 4); | |
196 | if !CC JUMP 1b; | |
197 | #else /* SDRAM */ | |
1394f032 | 198 | P0.L = lo(EBIU_SDGCTL); |
1efc80b5 | 199 | P0.H = hi(EBIU_SDGCTL); |
1394f032 | 200 | R2 = [P0]; |
1efc80b5 | 201 | BITSET(R2, 24); /* SRFS enter self-refresh mode */ |
1394f032 | 202 | [P0] = R2; |
1efc80b5 MH |
203 | SSYNC; |
204 | ||
205 | P0.L = lo(EBIU_SDSTAT); | |
206 | P0.H = hi(EBIU_SDSTAT); | |
207 | 1: | |
208 | R2 = w[P0]; | |
209 | SSYNC; | |
210 | cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */ | |
211 | if !cc jump 1b; | |
212 | ||
213 | P0.L = lo(EBIU_SDGCTL); | |
214 | P0.H = hi(EBIU_SDGCTL); | |
fb5f0049 | 215 | R2 = [P0]; |
1efc80b5 MH |
216 | BITCLR(R2, 0); /* SCTLE disable CLKOUT */ |
217 | [P0] = R2; | |
fb5f0049 | 218 | #endif |
1394f032 | 219 | RTS; |
1a8caeeb | 220 | ENDPROC(_set_dram_srfs) |
1efc80b5 | 221 | |
fb5f0049 SZ |
222 | ENTRY(_unset_dram_srfs) |
223 | /* set the dram out of self refresh mode */ | |
1efc80b5 | 224 | #if defined(EBIU_RSTCTL) /* DDR */ |
fb5f0049 SZ |
225 | P0.H = hi(EBIU_RSTCTL); |
226 | P0.L = lo(EBIU_RSTCTL); | |
227 | R2 = [P0]; | |
1efc80b5 MH |
228 | BITCLR(R2, 3); /* clear SRREQ bit */ |
229 | [P0] = R2; | |
230 | #elif defined(EBIU_SDGCTL) /* SDRAM */ | |
231 | ||
232 | P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */ | |
1394f032 | 233 | P0.H = hi(EBIU_SDGCTL); |
1394f032 | 234 | R2 = [P0]; |
1efc80b5 MH |
235 | BITSET(R2, 0); /* SCTLE enable CLKOUT */ |
236 | [P0] = R2 | |
237 | SSYNC; | |
238 | ||
239 | P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */ | |
240 | P0.H = hi(EBIU_SDGCTL); | |
241 | R2 = [P0]; | |
242 | BITCLR(R2, 24); /* clear SRFS bit */ | |
243 | [P0] = R2 | |
fb5f0049 | 244 | #endif |
1efc80b5 | 245 | SSYNC; |
1394f032 | 246 | RTS; |
1a8caeeb | 247 | ENDPROC(_unset_dram_srfs) |
1394f032 BW |
248 | |
249 | ENTRY(_set_sic_iwr) | |
dc26aec2 MH |
250 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \ |
251 | defined(CONFIG_BF538) || defined(CONFIG_BF539) | |
fb5f0049 SZ |
252 | P0.H = hi(SIC_IWR0); |
253 | P0.L = lo(SIC_IWR0); | |
cfefe3c6 MH |
254 | P1.H = hi(SIC_IWR1); |
255 | P1.L = lo(SIC_IWR1); | |
256 | [P1] = R1; | |
257 | #if defined(CONFIG_BF54x) | |
258 | P1.H = hi(SIC_IWR2); | |
259 | P1.L = lo(SIC_IWR2); | |
260 | [P1] = R2; | |
261 | #endif | |
fb5f0049 | 262 | #else |
1394f032 BW |
263 | P0.H = hi(SIC_IWR); |
264 | P0.L = lo(SIC_IWR); | |
fb5f0049 | 265 | #endif |
1394f032 | 266 | [P0] = R0; |
cfefe3c6 | 267 | |
1394f032 BW |
268 | SSYNC; |
269 | RTS; | |
1a8caeeb | 270 | ENDPROC(_set_sic_iwr) |
1394f032 BW |
271 | |
272 | ENTRY(_set_rtc_istat) | |
3927819d | 273 | #ifndef CONFIG_BF561 |
1394f032 BW |
274 | P0.H = hi(RTC_ISTAT); |
275 | P0.L = lo(RTC_ISTAT); | |
276 | w[P0] = R0.L; | |
277 | SSYNC; | |
1efc80b5 MH |
278 | #elif (ANOMALY_05000371) |
279 | nop; | |
280 | nop; | |
281 | nop; | |
282 | nop; | |
3927819d | 283 | #endif |
1394f032 | 284 | RTS; |
1a8caeeb | 285 | ENDPROC(_set_rtc_istat) |
1394f032 BW |
286 | |
287 | ENTRY(_test_pll_locked) | |
288 | P0.H = hi(PLL_STAT); | |
289 | P0.L = lo(PLL_STAT); | |
290 | 1: | |
291 | R0 = W[P0] (Z); | |
292 | CC = BITTST(R0,5); | |
293 | IF !CC JUMP 1b; | |
294 | RTS; | |
1a8caeeb | 295 | ENDPROC(_test_pll_locked) |
1efc80b5 MH |
296 | |
297 | .section .text | |
298 | ||
1efc80b5 MH |
299 | ENTRY(_do_hibernate) |
300 | [--SP] = ( R7:0, P5:0 ); | |
301 | [--SP] = RETS; | |
302 | /* Save System MMRs */ | |
303 | R2 = R0; | |
304 | P0.H = hi(PLL_CTL); | |
305 | P0.L = lo(PLL_CTL); | |
306 | ||
307 | #ifdef SIC_IMASK0 | |
308 | PM_SYS_PUSH(SIC_IMASK0) | |
309 | #endif | |
310 | #ifdef SIC_IMASK1 | |
311 | PM_SYS_PUSH(SIC_IMASK1) | |
312 | #endif | |
313 | #ifdef SIC_IMASK2 | |
314 | PM_SYS_PUSH(SIC_IMASK2) | |
315 | #endif | |
316 | #ifdef SIC_IMASK | |
317 | PM_SYS_PUSH(SIC_IMASK) | |
318 | #endif | |
319 | #ifdef SICA_IMASK0 | |
320 | PM_SYS_PUSH(SICA_IMASK0) | |
321 | #endif | |
322 | #ifdef SICA_IMASK1 | |
323 | PM_SYS_PUSH(SICA_IMASK1) | |
324 | #endif | |
325 | #ifdef SIC_IAR2 | |
326 | PM_SYS_PUSH(SIC_IAR0) | |
327 | PM_SYS_PUSH(SIC_IAR1) | |
328 | PM_SYS_PUSH(SIC_IAR2) | |
329 | #endif | |
330 | #ifdef SIC_IAR3 | |
331 | PM_SYS_PUSH(SIC_IAR3) | |
332 | #endif | |
333 | #ifdef SIC_IAR4 | |
334 | PM_SYS_PUSH(SIC_IAR4) | |
335 | PM_SYS_PUSH(SIC_IAR5) | |
336 | PM_SYS_PUSH(SIC_IAR6) | |
337 | #endif | |
338 | #ifdef SIC_IAR7 | |
339 | PM_SYS_PUSH(SIC_IAR7) | |
340 | #endif | |
341 | #ifdef SIC_IAR8 | |
342 | PM_SYS_PUSH(SIC_IAR8) | |
343 | PM_SYS_PUSH(SIC_IAR9) | |
344 | PM_SYS_PUSH(SIC_IAR10) | |
345 | PM_SYS_PUSH(SIC_IAR11) | |
346 | #endif | |
347 | ||
348 | #ifdef SICA_IAR0 | |
349 | PM_SYS_PUSH(SICA_IAR0) | |
350 | PM_SYS_PUSH(SICA_IAR1) | |
351 | PM_SYS_PUSH(SICA_IAR2) | |
352 | PM_SYS_PUSH(SICA_IAR3) | |
353 | PM_SYS_PUSH(SICA_IAR4) | |
354 | PM_SYS_PUSH(SICA_IAR5) | |
355 | PM_SYS_PUSH(SICA_IAR6) | |
356 | PM_SYS_PUSH(SICA_IAR7) | |
357 | #endif | |
358 | ||
359 | #ifdef SIC_IWR | |
360 | PM_SYS_PUSH(SIC_IWR) | |
361 | #endif | |
362 | #ifdef SIC_IWR0 | |
363 | PM_SYS_PUSH(SIC_IWR0) | |
364 | #endif | |
365 | #ifdef SIC_IWR1 | |
366 | PM_SYS_PUSH(SIC_IWR1) | |
367 | #endif | |
368 | #ifdef SIC_IWR2 | |
369 | PM_SYS_PUSH(SIC_IWR2) | |
370 | #endif | |
371 | #ifdef SICA_IWR0 | |
372 | PM_SYS_PUSH(SICA_IWR0) | |
373 | #endif | |
374 | #ifdef SICA_IWR1 | |
375 | PM_SYS_PUSH(SICA_IWR1) | |
376 | #endif | |
377 | ||
378 | #ifdef PINT0_ASSIGN | |
379 | PM_SYS_PUSH(PINT0_ASSIGN) | |
380 | PM_SYS_PUSH(PINT1_ASSIGN) | |
381 | PM_SYS_PUSH(PINT2_ASSIGN) | |
382 | PM_SYS_PUSH(PINT3_ASSIGN) | |
383 | #endif | |
384 | ||
385 | PM_SYS_PUSH(EBIU_AMBCTL0) | |
386 | PM_SYS_PUSH(EBIU_AMBCTL1) | |
387 | PM_SYS_PUSH16(EBIU_AMGCTL) | |
388 | ||
389 | #ifdef EBIU_FCTL | |
390 | PM_SYS_PUSH(EBIU_MBSCTL) | |
391 | PM_SYS_PUSH(EBIU_MODE) | |
392 | PM_SYS_PUSH(EBIU_FCTL) | |
393 | #endif | |
394 | ||
395 | PM_SYS_PUSH16(SYSCR) | |
396 | ||
397 | /* Save Core MMRs */ | |
398 | P0.H = hi(SRAM_BASE_ADDRESS); | |
399 | P0.L = lo(SRAM_BASE_ADDRESS); | |
400 | ||
401 | PM_PUSH(DMEM_CONTROL) | |
402 | PM_PUSH(DCPLB_ADDR0) | |
403 | PM_PUSH(DCPLB_ADDR1) | |
404 | PM_PUSH(DCPLB_ADDR2) | |
405 | PM_PUSH(DCPLB_ADDR3) | |
406 | PM_PUSH(DCPLB_ADDR4) | |
407 | PM_PUSH(DCPLB_ADDR5) | |
408 | PM_PUSH(DCPLB_ADDR6) | |
409 | PM_PUSH(DCPLB_ADDR7) | |
410 | PM_PUSH(DCPLB_ADDR8) | |
411 | PM_PUSH(DCPLB_ADDR9) | |
412 | PM_PUSH(DCPLB_ADDR10) | |
413 | PM_PUSH(DCPLB_ADDR11) | |
414 | PM_PUSH(DCPLB_ADDR12) | |
415 | PM_PUSH(DCPLB_ADDR13) | |
416 | PM_PUSH(DCPLB_ADDR14) | |
417 | PM_PUSH(DCPLB_ADDR15) | |
418 | PM_PUSH(DCPLB_DATA0) | |
419 | PM_PUSH(DCPLB_DATA1) | |
420 | PM_PUSH(DCPLB_DATA2) | |
421 | PM_PUSH(DCPLB_DATA3) | |
422 | PM_PUSH(DCPLB_DATA4) | |
423 | PM_PUSH(DCPLB_DATA5) | |
424 | PM_PUSH(DCPLB_DATA6) | |
425 | PM_PUSH(DCPLB_DATA7) | |
426 | PM_PUSH(DCPLB_DATA8) | |
427 | PM_PUSH(DCPLB_DATA9) | |
428 | PM_PUSH(DCPLB_DATA10) | |
429 | PM_PUSH(DCPLB_DATA11) | |
430 | PM_PUSH(DCPLB_DATA12) | |
431 | PM_PUSH(DCPLB_DATA13) | |
432 | PM_PUSH(DCPLB_DATA14) | |
433 | PM_PUSH(DCPLB_DATA15) | |
434 | PM_PUSH(IMEM_CONTROL) | |
435 | PM_PUSH(ICPLB_ADDR0) | |
436 | PM_PUSH(ICPLB_ADDR1) | |
437 | PM_PUSH(ICPLB_ADDR2) | |
438 | PM_PUSH(ICPLB_ADDR3) | |
439 | PM_PUSH(ICPLB_ADDR4) | |
440 | PM_PUSH(ICPLB_ADDR5) | |
441 | PM_PUSH(ICPLB_ADDR6) | |
442 | PM_PUSH(ICPLB_ADDR7) | |
443 | PM_PUSH(ICPLB_ADDR8) | |
444 | PM_PUSH(ICPLB_ADDR9) | |
445 | PM_PUSH(ICPLB_ADDR10) | |
446 | PM_PUSH(ICPLB_ADDR11) | |
447 | PM_PUSH(ICPLB_ADDR12) | |
448 | PM_PUSH(ICPLB_ADDR13) | |
449 | PM_PUSH(ICPLB_ADDR14) | |
450 | PM_PUSH(ICPLB_ADDR15) | |
451 | PM_PUSH(ICPLB_DATA0) | |
452 | PM_PUSH(ICPLB_DATA1) | |
453 | PM_PUSH(ICPLB_DATA2) | |
454 | PM_PUSH(ICPLB_DATA3) | |
455 | PM_PUSH(ICPLB_DATA4) | |
456 | PM_PUSH(ICPLB_DATA5) | |
457 | PM_PUSH(ICPLB_DATA6) | |
458 | PM_PUSH(ICPLB_DATA7) | |
459 | PM_PUSH(ICPLB_DATA8) | |
460 | PM_PUSH(ICPLB_DATA9) | |
461 | PM_PUSH(ICPLB_DATA10) | |
462 | PM_PUSH(ICPLB_DATA11) | |
463 | PM_PUSH(ICPLB_DATA12) | |
464 | PM_PUSH(ICPLB_DATA13) | |
465 | PM_PUSH(ICPLB_DATA14) | |
466 | PM_PUSH(ICPLB_DATA15) | |
467 | PM_PUSH(EVT0) | |
468 | PM_PUSH(EVT1) | |
469 | PM_PUSH(EVT2) | |
470 | PM_PUSH(EVT3) | |
471 | PM_PUSH(EVT4) | |
472 | PM_PUSH(EVT5) | |
473 | PM_PUSH(EVT6) | |
474 | PM_PUSH(EVT7) | |
475 | PM_PUSH(EVT8) | |
476 | PM_PUSH(EVT9) | |
477 | PM_PUSH(EVT10) | |
478 | PM_PUSH(EVT11) | |
479 | PM_PUSH(EVT12) | |
480 | PM_PUSH(EVT13) | |
481 | PM_PUSH(EVT14) | |
482 | PM_PUSH(EVT15) | |
483 | PM_PUSH(IMASK) | |
484 | PM_PUSH(ILAT) | |
485 | PM_PUSH(IPRIO) | |
486 | PM_PUSH(TCNTL) | |
487 | PM_PUSH(TPERIOD) | |
488 | PM_PUSH(TSCALE) | |
489 | PM_PUSH(TCOUNT) | |
490 | PM_PUSH(TBUFCTL) | |
491 | ||
492 | /* Save Core Registers */ | |
493 | [--sp] = SYSCFG; | |
494 | [--sp] = ( R7:0, P5:0 ); | |
495 | [--sp] = fp; | |
496 | [--sp] = usp; | |
497 | ||
498 | [--sp] = i0; | |
499 | [--sp] = i1; | |
500 | [--sp] = i2; | |
501 | [--sp] = i3; | |
502 | ||
503 | [--sp] = m0; | |
504 | [--sp] = m1; | |
505 | [--sp] = m2; | |
506 | [--sp] = m3; | |
507 | ||
508 | [--sp] = l0; | |
509 | [--sp] = l1; | |
510 | [--sp] = l2; | |
511 | [--sp] = l3; | |
512 | ||
513 | [--sp] = b0; | |
514 | [--sp] = b1; | |
515 | [--sp] = b2; | |
516 | [--sp] = b3; | |
517 | [--sp] = a0.x; | |
518 | [--sp] = a0.w; | |
519 | [--sp] = a1.x; | |
520 | [--sp] = a1.w; | |
521 | ||
522 | [--sp] = LC0; | |
523 | [--sp] = LC1; | |
524 | [--sp] = LT0; | |
525 | [--sp] = LT1; | |
526 | [--sp] = LB0; | |
527 | [--sp] = LB1; | |
528 | ||
529 | [--sp] = ASTAT; | |
530 | [--sp] = CYCLES; | |
531 | [--sp] = CYCLES2; | |
532 | ||
533 | [--sp] = RETS; | |
534 | r0 = RETI; | |
535 | [--sp] = r0; | |
536 | [--sp] = RETX; | |
537 | [--sp] = RETN; | |
538 | [--sp] = RETE; | |
539 | [--sp] = SEQSTAT; | |
540 | ||
541 | /* Save Magic, return address and Stack Pointer */ | |
542 | P0.H = 0; | |
543 | P0.L = 0; | |
544 | R0.H = 0xDEAD; /* Hibernate Magic */ | |
545 | R0.L = 0xBEEF; | |
546 | [P0++] = R0; /* Store Hibernate Magic */ | |
1a8caeeb MF |
547 | R0.H = .Lpm_resume_here; |
548 | R0.L = .Lpm_resume_here; | |
1efc80b5 MH |
549 | [P0++] = R0; /* Save Return Address */ |
550 | [P0++] = SP; /* Save Stack Pointer */ | |
551 | P0.H = _hibernate_mode; | |
552 | P0.L = _hibernate_mode; | |
553 | R0 = R2; | |
554 | call (P0); /* Goodbye */ | |
555 | ||
1a8caeeb | 556 | .Lpm_resume_here: |
1efc80b5 MH |
557 | |
558 | /* Restore Core Registers */ | |
559 | SEQSTAT = [sp++]; | |
560 | RETE = [sp++]; | |
561 | RETN = [sp++]; | |
562 | RETX = [sp++]; | |
563 | r0 = [sp++]; | |
564 | RETI = r0; | |
565 | RETS = [sp++]; | |
566 | ||
567 | CYCLES2 = [sp++]; | |
568 | CYCLES = [sp++]; | |
569 | ASTAT = [sp++]; | |
570 | ||
571 | LB1 = [sp++]; | |
572 | LB0 = [sp++]; | |
573 | LT1 = [sp++]; | |
574 | LT0 = [sp++]; | |
575 | LC1 = [sp++]; | |
576 | LC0 = [sp++]; | |
577 | ||
578 | a1.w = [sp++]; | |
579 | a1.x = [sp++]; | |
580 | a0.w = [sp++]; | |
581 | a0.x = [sp++]; | |
582 | b3 = [sp++]; | |
583 | b2 = [sp++]; | |
584 | b1 = [sp++]; | |
585 | b0 = [sp++]; | |
586 | ||
587 | l3 = [sp++]; | |
588 | l2 = [sp++]; | |
589 | l1 = [sp++]; | |
590 | l0 = [sp++]; | |
591 | ||
592 | m3 = [sp++]; | |
593 | m2 = [sp++]; | |
594 | m1 = [sp++]; | |
595 | m0 = [sp++]; | |
596 | ||
597 | i3 = [sp++]; | |
598 | i2 = [sp++]; | |
599 | i1 = [sp++]; | |
600 | i0 = [sp++]; | |
601 | ||
602 | usp = [sp++]; | |
603 | fp = [sp++]; | |
604 | ||
605 | ( R7 : 0, P5 : 0) = [ SP ++ ]; | |
606 | SYSCFG = [sp++]; | |
607 | ||
608 | /* Restore Core MMRs */ | |
609 | ||
610 | PM_POP(TBUFCTL) | |
611 | PM_POP(TCOUNT) | |
612 | PM_POP(TSCALE) | |
613 | PM_POP(TPERIOD) | |
614 | PM_POP(TCNTL) | |
615 | PM_POP(IPRIO) | |
616 | PM_POP(ILAT) | |
617 | PM_POP(IMASK) | |
618 | PM_POP(EVT15) | |
619 | PM_POP(EVT14) | |
620 | PM_POP(EVT13) | |
621 | PM_POP(EVT12) | |
622 | PM_POP(EVT11) | |
623 | PM_POP(EVT10) | |
624 | PM_POP(EVT9) | |
625 | PM_POP(EVT8) | |
626 | PM_POP(EVT7) | |
627 | PM_POP(EVT6) | |
628 | PM_POP(EVT5) | |
629 | PM_POP(EVT4) | |
630 | PM_POP(EVT3) | |
631 | PM_POP(EVT2) | |
632 | PM_POP(EVT1) | |
633 | PM_POP(EVT0) | |
634 | PM_POP(ICPLB_DATA15) | |
635 | PM_POP(ICPLB_DATA14) | |
636 | PM_POP(ICPLB_DATA13) | |
637 | PM_POP(ICPLB_DATA12) | |
638 | PM_POP(ICPLB_DATA11) | |
639 | PM_POP(ICPLB_DATA10) | |
640 | PM_POP(ICPLB_DATA9) | |
641 | PM_POP(ICPLB_DATA8) | |
642 | PM_POP(ICPLB_DATA7) | |
643 | PM_POP(ICPLB_DATA6) | |
644 | PM_POP(ICPLB_DATA5) | |
645 | PM_POP(ICPLB_DATA4) | |
646 | PM_POP(ICPLB_DATA3) | |
647 | PM_POP(ICPLB_DATA2) | |
648 | PM_POP(ICPLB_DATA1) | |
649 | PM_POP(ICPLB_DATA0) | |
650 | PM_POP(ICPLB_ADDR15) | |
651 | PM_POP(ICPLB_ADDR14) | |
652 | PM_POP(ICPLB_ADDR13) | |
653 | PM_POP(ICPLB_ADDR12) | |
654 | PM_POP(ICPLB_ADDR11) | |
655 | PM_POP(ICPLB_ADDR10) | |
656 | PM_POP(ICPLB_ADDR9) | |
657 | PM_POP(ICPLB_ADDR8) | |
658 | PM_POP(ICPLB_ADDR7) | |
659 | PM_POP(ICPLB_ADDR6) | |
660 | PM_POP(ICPLB_ADDR5) | |
661 | PM_POP(ICPLB_ADDR4) | |
662 | PM_POP(ICPLB_ADDR3) | |
663 | PM_POP(ICPLB_ADDR2) | |
664 | PM_POP(ICPLB_ADDR1) | |
665 | PM_POP(ICPLB_ADDR0) | |
666 | PM_POP(IMEM_CONTROL) | |
667 | PM_POP(DCPLB_DATA15) | |
668 | PM_POP(DCPLB_DATA14) | |
669 | PM_POP(DCPLB_DATA13) | |
670 | PM_POP(DCPLB_DATA12) | |
671 | PM_POP(DCPLB_DATA11) | |
672 | PM_POP(DCPLB_DATA10) | |
673 | PM_POP(DCPLB_DATA9) | |
674 | PM_POP(DCPLB_DATA8) | |
675 | PM_POP(DCPLB_DATA7) | |
676 | PM_POP(DCPLB_DATA6) | |
677 | PM_POP(DCPLB_DATA5) | |
678 | PM_POP(DCPLB_DATA4) | |
679 | PM_POP(DCPLB_DATA3) | |
680 | PM_POP(DCPLB_DATA2) | |
681 | PM_POP(DCPLB_DATA1) | |
682 | PM_POP(DCPLB_DATA0) | |
683 | PM_POP(DCPLB_ADDR15) | |
684 | PM_POP(DCPLB_ADDR14) | |
685 | PM_POP(DCPLB_ADDR13) | |
686 | PM_POP(DCPLB_ADDR12) | |
687 | PM_POP(DCPLB_ADDR11) | |
688 | PM_POP(DCPLB_ADDR10) | |
689 | PM_POP(DCPLB_ADDR9) | |
690 | PM_POP(DCPLB_ADDR8) | |
691 | PM_POP(DCPLB_ADDR7) | |
692 | PM_POP(DCPLB_ADDR6) | |
693 | PM_POP(DCPLB_ADDR5) | |
694 | PM_POP(DCPLB_ADDR4) | |
695 | PM_POP(DCPLB_ADDR3) | |
696 | PM_POP(DCPLB_ADDR2) | |
697 | PM_POP(DCPLB_ADDR1) | |
698 | PM_POP(DCPLB_ADDR0) | |
699 | PM_POP(DMEM_CONTROL) | |
700 | ||
701 | /* Restore System MMRs */ | |
702 | ||
703 | P0.H = hi(PLL_CTL); | |
704 | P0.L = lo(PLL_CTL); | |
705 | PM_SYS_POP16(SYSCR) | |
706 | ||
707 | #ifdef EBIU_FCTL | |
708 | PM_SYS_POP(EBIU_FCTL) | |
709 | PM_SYS_POP(EBIU_MODE) | |
710 | PM_SYS_POP(EBIU_MBSCTL) | |
711 | #endif | |
712 | PM_SYS_POP16(EBIU_AMGCTL) | |
713 | PM_SYS_POP(EBIU_AMBCTL1) | |
714 | PM_SYS_POP(EBIU_AMBCTL0) | |
715 | ||
716 | #ifdef PINT0_ASSIGN | |
717 | PM_SYS_POP(PINT3_ASSIGN) | |
718 | PM_SYS_POP(PINT2_ASSIGN) | |
719 | PM_SYS_POP(PINT1_ASSIGN) | |
720 | PM_SYS_POP(PINT0_ASSIGN) | |
721 | #endif | |
722 | ||
723 | #ifdef SICA_IWR1 | |
724 | PM_SYS_POP(SICA_IWR1) | |
725 | #endif | |
726 | #ifdef SICA_IWR0 | |
727 | PM_SYS_POP(SICA_IWR0) | |
728 | #endif | |
729 | #ifdef SIC_IWR2 | |
730 | PM_SYS_POP(SIC_IWR2) | |
731 | #endif | |
732 | #ifdef SIC_IWR1 | |
733 | PM_SYS_POP(SIC_IWR1) | |
734 | #endif | |
735 | #ifdef SIC_IWR0 | |
736 | PM_SYS_POP(SIC_IWR0) | |
737 | #endif | |
738 | #ifdef SIC_IWR | |
739 | PM_SYS_POP(SIC_IWR) | |
740 | #endif | |
741 | ||
742 | #ifdef SICA_IAR0 | |
743 | PM_SYS_POP(SICA_IAR7) | |
744 | PM_SYS_POP(SICA_IAR6) | |
745 | PM_SYS_POP(SICA_IAR5) | |
746 | PM_SYS_POP(SICA_IAR4) | |
747 | PM_SYS_POP(SICA_IAR3) | |
748 | PM_SYS_POP(SICA_IAR2) | |
749 | PM_SYS_POP(SICA_IAR1) | |
750 | PM_SYS_POP(SICA_IAR0) | |
751 | #endif | |
752 | ||
753 | #ifdef SIC_IAR8 | |
754 | PM_SYS_POP(SIC_IAR11) | |
755 | PM_SYS_POP(SIC_IAR10) | |
756 | PM_SYS_POP(SIC_IAR9) | |
757 | PM_SYS_POP(SIC_IAR8) | |
758 | #endif | |
759 | #ifdef SIC_IAR7 | |
760 | PM_SYS_POP(SIC_IAR7) | |
761 | #endif | |
762 | #ifdef SIC_IAR6 | |
763 | PM_SYS_POP(SIC_IAR6) | |
764 | PM_SYS_POP(SIC_IAR5) | |
765 | PM_SYS_POP(SIC_IAR4) | |
766 | #endif | |
767 | #ifdef SIC_IAR3 | |
768 | PM_SYS_POP(SIC_IAR3) | |
769 | #endif | |
770 | #ifdef SIC_IAR2 | |
771 | PM_SYS_POP(SIC_IAR2) | |
772 | PM_SYS_POP(SIC_IAR1) | |
773 | PM_SYS_POP(SIC_IAR0) | |
774 | #endif | |
775 | #ifdef SICA_IMASK1 | |
776 | PM_SYS_POP(SICA_IMASK1) | |
777 | #endif | |
778 | #ifdef SICA_IMASK0 | |
779 | PM_SYS_POP(SICA_IMASK0) | |
780 | #endif | |
781 | #ifdef SIC_IMASK | |
782 | PM_SYS_POP(SIC_IMASK) | |
783 | #endif | |
784 | #ifdef SIC_IMASK2 | |
785 | PM_SYS_POP(SIC_IMASK2) | |
786 | #endif | |
787 | #ifdef SIC_IMASK1 | |
788 | PM_SYS_POP(SIC_IMASK1) | |
789 | #endif | |
790 | #ifdef SIC_IMASK0 | |
791 | PM_SYS_POP(SIC_IMASK0) | |
792 | #endif | |
793 | ||
794 | [--sp] = RETI; /* Clear Global Interrupt Disable */ | |
795 | SP += 4; | |
796 | ||
797 | RETS = [SP++]; | |
798 | ( R7:0, P5:0 ) = [SP++]; | |
799 | RTS; | |
1a8caeeb | 800 | ENDPROC(_do_hibernate) |