[deliverable/linux.git] / arch / blackfin / mach-common / head.S

/*
 * Common Blackfin startup code
 *
 * Copyright 2004-2008 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/thread_info.h>
#include <asm/trace.h>
#include <asm/asm-offsets.h>

__INIT

ENTRY(__init_clear_bss)
	r2 = r2 - r1;
	cc = r2 == 0;
	if cc jump .L_bss_done;
	r2 >>= 2;
	p1 = r1;
	p2 = r2;
	lsetup (1f, 1f) lc0 = p2;
1:	[p1++] = r0;
.L_bss_done:
	rts;
ENDPROC(__init_clear_bss)

ENTRY(__start)
	/* R0: argument of command line string, passed from uboot, save it */
	R7 = R0;
	/* Enable Cycle Counter and Nesting Of Interrupts */
#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
	R0 = SYSCFG_SNEN;
#else
	R0 = SYSCFG_SNEN | SYSCFG_CCEN;
#endif
	SYSCFG = R0;
	R0 = 0;

	/* Clear Out All the data and pointer Registers */
	R1 = R0;
	R2 = R0;
	R3 = R0;
	R4 = R0;
	R5 = R0;
	R6 = R0;

	P0 = R0;
	P1 = R0;
	P2 = R0;
	P3 = R0;
	P4 = R0;
	P5 = R0;

	LC0 = r0;
	LC1 = r0;
	L0 = r0;
	L1 = r0;
	L2 = r0;
	L3 = r0;

	/* Clear Out All the DAG Registers */
	B0 = r0;
	B1 = r0;
	B2 = r0;
	B3 = r0;

	I0 = r0;
	I1 = r0;
	I2 = r0;
	I3 = r0;

	M0 = r0;
	M1 = r0;
	M2 = r0;
	M3 = r0;

	/*
	 * Clear ITEST_COMMAND and DTEST_COMMAND registers,
	 * Leaving these as non-zero can confuse the emulator
	 */
	p0.L = LO(DTEST_COMMAND);
	p0.H = HI(DTEST_COMMAND);
	[p0] = R0;
	[p0 + (ITEST_COMMAND - DTEST_COMMAND)] = R0;
	CSYNC;

	trace_buffer_init(p0,r0);
	P0 = R1;
	R0 = R1;

	/* Turn off the icache */
	p0.l = LO(IMEM_CONTROL);
	p0.h = HI(IMEM_CONTROL);
	R1 = [p0];
	R0 = ~ENICPLB;
	R0 = R0 & R1;
	[p0] = R0;
	SSYNC;

	/* Turn off the dcache */
	p0.l = LO(DMEM_CONTROL);
	p0.h = HI(DMEM_CONTROL);
	R1 = [p0];
	R0 = ~ENDCPLB;
	R0 = R0 & R1;
	[p0] = R0;
	SSYNC;

	/* in case of double faults, save a few things */
	p0.l = _init_retx;
	p0.h = _init_retx;
	R0 = RETX;
	[P0] = R0;

#ifdef CONFIG_DEBUG_DOUBLEFAULT
	/* Only save these if we are storing them,
	 * This happens here, since L1 gets clobbered
	 * below
	 */
	GET_PDA(p0, r0);
	r6 = [p0 + PDA_RETX];
	p1.l = _init_saved_retx;
	p1.h = _init_saved_retx;
	[p1] = r6;

	r6 = [p0 + PDA_DCPLB];
	p1.l = _init_saved_dcplb_fault_addr;
	p1.h = _init_saved_dcplb_fault_addr;
	[p1] = r6;

	r6 = [p0 + PDA_ICPLB];
	p1.l = _init_saved_icplb_fault_addr;
	p1.h = _init_saved_icplb_fault_addr;
	[p1] = r6;

	r6 = [p0 + PDA_SEQSTAT];
	p1.l = _init_saved_seqstat;
	p1.h = _init_saved_seqstat;
	[p1] = r6;
#endif

	/* Initialize stack pointer */
	sp.l = _init_thread_union;
	sp.h = _init_thread_union;
	fp = sp;
	usp = sp;

#ifdef CONFIG_EARLY_PRINTK
	call _init_early_exception_vectors;
#endif

	r0 = 0 (x);
	/* Zero out all of the fun bss regions */
#if L1_DATA_A_LENGTH > 0
	r1.l = __sbss_l1;
	r1.h = __sbss_l1;
	r2.l = __ebss_l1;
	r2.h = __ebss_l1;
	call __init_clear_bss
#endif
#if L1_DATA_B_LENGTH > 0
	r1.l = __sbss_b_l1;
	r1.h = __sbss_b_l1;
	r2.l = __ebss_b_l1;
	r2.h = __ebss_b_l1;
	call __init_clear_bss
#endif
#if L2_LENGTH > 0
	r1.l = __sbss_l2;
	r1.h = __sbss_l2;
	r2.l = __ebss_l2;
	r2.h = __ebss_l2;
	call __init_clear_bss
#endif
	r1.l = ___bss_start;
	r1.h = ___bss_start;
	r2.l = ___bss_stop;
	r2.h = ___bss_stop;
	call __init_clear_bss

	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
	call _bfin_relocate_l1_mem;
#ifdef CONFIG_BFIN_KERNEL_CLOCK
	/* Only use on-chip scratch space for stack when absolutely required
	 * to avoid Anomaly 05000227 ... we know the init_clocks() func only
	 * uses L1 text and stack space and no other memory region.
	 */
# define KERNEL_CLOCK_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
	sp.l = lo(KERNEL_CLOCK_STACK);
	sp.h = hi(KERNEL_CLOCK_STACK);
	call _init_clocks;
	sp = usp;	/* usp hasnt been touched, so restore from there */
#endif

	/* This section keeps the processor in supervisor mode
	 * during kernel boot.  Switches to user mode at end of boot.
	 * See page 3-9 of Hardware Reference manual for documentation.
	 */

	/* EVT15 = _real_start */

	p0.l = lo(EVT15);
	p0.h = hi(EVT15);
	p1.l = _real_start;
	p1.h = _real_start;
	[p0] = p1;
	csync;

	r0 = EVT_IVG15 (z);
	sti r0;

	raise 15;
	p0.l = .LWAIT_HERE;
	p0.h = .LWAIT_HERE;
	reti = p0;
#if ANOMALY_05000281
	nop; nop; nop;
#endif
	rti;

.LWAIT_HERE:
	jump .LWAIT_HERE;
ENDPROC(__start)

/* A little BF561 glue ... */
#ifndef WDOG_CTL
# define WDOG_CTL WDOGA_CTL
#endif

ENTRY(_real_start)
	/* Enable nested interrupts */
	[--sp] = reti;

	/* watchdog off for now */
	p0.l = lo(WDOG_CTL);
	p0.h = hi(WDOG_CTL);
	r0 = 0xAD6(z);
	w[p0] = r0;
	ssync;

	/* Pass the u-boot arguments to the global value command line */
	R0 = R7;
	call _cmdline_init;

	/* Load the current thread pointer and stack */
	p1 = THREAD_SIZE + 4 (z);	/* +4 is for reti loading */
	sp = sp + p1;
	usp = sp;
	fp = sp;
	sp += -12;
	call _init_pda
	sp += 12;
	jump.l _start_kernel;
ENDPROC(_real_start)

__FINIT
Commit	Line	Data
09e1f70e MF	1	/*
	2	* Common Blackfin startup code
	3	*
	4	* Copyright 2004-2008 Analog Devices Inc.
	5	*
	6	* Enter bugs at http://blackfin.uclinux.org/
	7	*
	8	* Licensed under the GPL-2 or later.
	9	*/
	10
	11	#include <linux/linkage.h>
	12	#include <linux/init.h>
	13	#include <asm/blackfin.h>
67618fd8	14	#include <asm/thread_info.h>
09e1f70e	15	#include <asm/trace.h>
6b3087c6	16	#include <asm/asm-offsets.h>
09e1f70e	17
17e89bcf MF	18	__INIT
17e89bcf MF	19
9960aa6a GY	20	ENTRY(__init_clear_bss)
	21	r2 = r2 - r1;
	22	cc = r2 == 0;
	23	if cc jump .L_bss_done;
	24	r2 >>= 2;
	25	p1 = r1;
	26	p2 = r2;
	27	lsetup (1f, 1f) lc0 = p2;
	28	1: [p1++] = r0;
	29	.L_bss_done:
	30	rts;
	31	ENDPROC(__init_clear_bss)
	32
17e89bcf MF	33	ENTRY(__start)
	34	/* R0: argument of command line string, passed from uboot, save it */
	35	R7 = R0;
	36	/* Enable Cycle Counter and Nesting Of Interrupts */
	37	#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
	38	R0 = SYSCFG_SNEN;
	39	#else
	40	R0 = SYSCFG_SNEN \| SYSCFG_CCEN;
	41	#endif
	42	SYSCFG = R0;
	43	R0 = 0;
	44
	45	/* Clear Out All the data and pointer Registers */
	46	R1 = R0;
	47	R2 = R0;
	48	R3 = R0;
	49	R4 = R0;
	50	R5 = R0;
	51	R6 = R0;
	52
	53	P0 = R0;
	54	P1 = R0;
	55	P2 = R0;
	56	P3 = R0;
	57	P4 = R0;
	58	P5 = R0;
	59
	60	LC0 = r0;
	61	LC1 = r0;
	62	L0 = r0;
	63	L1 = r0;
	64	L2 = r0;
	65	L3 = r0;
	66
	67	/* Clear Out All the DAG Registers */
	68	B0 = r0;
	69	B1 = r0;
	70	B2 = r0;
	71	B3 = r0;
	72
	73	I0 = r0;
	74	I1 = r0;
	75	I2 = r0;
	76	I3 = r0;
	77
	78	M0 = r0;
	79	M1 = r0;
	80	M2 = r0;
	81	M3 = r0;
	82
9df10281 RG	83	/*
	84	* Clear ITEST_COMMAND and DTEST_COMMAND registers,
	85	* Leaving these as non-zero can confuse the emulator
	86	*/
	87	p0.L = LO(DTEST_COMMAND);
	88	p0.H = HI(DTEST_COMMAND);
	89	[p0] = R0;
	90	[p0 + (ITEST_COMMAND - DTEST_COMMAND)] = R0;
	91	CSYNC;
	92
17e89bcf MF	93	trace_buffer_init(p0,r0);
	94	P0 = R1;
	95	R0 = R1;
	96
	97	/* Turn off the icache */
	98	p0.l = LO(IMEM_CONTROL);
	99	p0.h = HI(IMEM_CONTROL);
	100	R1 = [p0];
	101	R0 = ~ENICPLB;
	102	R0 = R0 & R1;
	103	[p0] = R0;
	104	SSYNC;
	105
	106	/* Turn off the dcache */
	107	p0.l = LO(DMEM_CONTROL);
	108	p0.h = HI(DMEM_CONTROL);
	109	R1 = [p0];
	110	R0 = ~ENDCPLB;
	111	R0 = R0 & R1;
	112	[p0] = R0;
	113	SSYNC;
	114
0c7a6b21 RG	115	/* in case of double faults, save a few things */
	116	p0.l = _init_retx;
	117	p0.h = _init_retx;
cd8fb8df RG	118	R0 = RETX;
	119	[P0] = R0;
	120
0c7a6b21 RG	121	#ifdef CONFIG_DEBUG_DOUBLEFAULT
	122	/* Only save these if we are storing them,
	123	* This happens here, since L1 gets clobbered
	124	* below
	125	*/
6b3087c6	126	GET_PDA(p0, r0);
37082511	127	r6 = [p0 + PDA_RETX];
0c7a6b21 RG	128	p1.l = _init_saved_retx;
0c7a6b21 RG	129	p1.h = _init_saved_retx;
37082511	130	[p1] = r6;
0c7a6b21	131
37082511	132	r6 = [p0 + PDA_DCPLB];
0c7a6b21 RG	133	p1.l = _init_saved_dcplb_fault_addr;
0c7a6b21 RG	134	p1.h = _init_saved_dcplb_fault_addr;
37082511	135	[p1] = r6;
0c7a6b21	136
37082511	137	r6 = [p0 + PDA_ICPLB];
0c7a6b21 RG	138	p1.l = _init_saved_icplb_fault_addr;
0c7a6b21 RG	139	p1.h = _init_saved_icplb_fault_addr;
37082511	140	[p1] = r6;
0c7a6b21	141
37082511	142	r6 = [p0 + PDA_SEQSTAT];
0c7a6b21 RG	143	p1.l = _init_saved_seqstat;
0c7a6b21 RG	144	p1.h = _init_saved_seqstat;
37082511	145	[p1] = r6;
0c7a6b21 RG	146	#endif
0c7a6b21 RG	147
17e89bcf	148	/* Initialize stack pointer */
729a3fa7 MF	149	sp.l = _init_thread_union;
729a3fa7 MF	150	sp.h = _init_thread_union;
17e89bcf MF	151	fp = sp;
	152	usp = sp;
	153
	154	#ifdef CONFIG_EARLY_PRINTK
	155	call _init_early_exception_vectors;
	156	#endif
	157
9960aa6a GY	158	r0 = 0 (x);
	159	/* Zero out all of the fun bss regions */
	160	#if L1_DATA_A_LENGTH > 0
	161	r1.l = __sbss_l1;
	162	r1.h = __sbss_l1;
	163	r2.l = __ebss_l1;
	164	r2.h = __ebss_l1;
	165	call __init_clear_bss
	166	#endif
	167	#if L1_DATA_B_LENGTH > 0
	168	r1.l = __sbss_b_l1;
	169	r1.h = __sbss_b_l1;
	170	r2.l = __ebss_b_l1;
	171	r2.h = __ebss_b_l1;
	172	call __init_clear_bss
	173	#endif
	174	#if L2_LENGTH > 0
	175	r1.l = __sbss_l2;
	176	r1.h = __sbss_l2;
	177	r2.l = __ebss_l2;
	178	r2.h = __ebss_l2;
	179	call __init_clear_bss
	180	#endif
	181	r1.l = ___bss_start;
	182	r1.h = ___bss_start;
	183	r2.l = ___bss_stop;
	184	r2.h = ___bss_stop;
	185	call __init_clear_bss
	186
17e89bcf	187	/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
5b04f271	188	call _bfin_relocate_l1_mem;
17e89bcf	189	#ifdef CONFIG_BFIN_KERNEL_CLOCK
729a3fa7 MF	190	/* Only use on-chip scratch space for stack when absolutely required
	191	* to avoid Anomaly 05000227 ... we know the init_clocks() func only
	192	* uses L1 text and stack space and no other memory region.
	193	*/
	194	# define KERNEL_CLOCK_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
	195	sp.l = lo(KERNEL_CLOCK_STACK);
	196	sp.h = hi(KERNEL_CLOCK_STACK);
73feb5c0	197	call _init_clocks;
729a3fa7	198	sp = usp; /* usp hasnt been touched, so restore from there */
17e89bcf MF	199	#endif
	200
	201	/* This section keeps the processor in supervisor mode
	202	* during kernel boot. Switches to user mode at end of boot.
	203	* See page 3-9 of Hardware Reference manual for documentation.
	204	*/
	205
	206	/* EVT15 = _real_start */
	207
	208	p0.l = lo(EVT15);
	209	p0.h = hi(EVT15);
	210	p1.l = _real_start;
	211	p1.h = _real_start;
	212	[p0] = p1;
	213	csync;
	214
c2414bd0 MF	215	r0 = EVT_IVG15 (z);
c2414bd0 MF	216	sti r0;
17e89bcf MF	217
	218	raise 15;
	219	p0.l = .LWAIT_HERE;
	220	p0.h = .LWAIT_HERE;
	221	reti = p0;
	222	#if ANOMALY_05000281
	223	nop; nop; nop;
	224	#endif
	225	rti;
	226
	227	.LWAIT_HERE:
	228	jump .LWAIT_HERE;
	229	ENDPROC(__start)
	230
09e1f70e MF	231	/* A little BF561 glue ... */
	232	#ifndef WDOG_CTL
	233	# define WDOG_CTL WDOGA_CTL
	234	#endif
	235
09e1f70e MF	236	ENTRY(_real_start)
	237	/* Enable nested interrupts */
	238	[--sp] = reti;
	239
	240	/* watchdog off for now */
	241	p0.l = lo(WDOG_CTL);
	242	p0.h = hi(WDOG_CTL);
	243	r0 = 0xAD6(z);
	244	w[p0] = r0;
	245	ssync;
	246
09e1f70e MF	247	/* Pass the u-boot arguments to the global value command line */
	248	R0 = R7;
	249	call _cmdline_init;
	250
	251	/* Load the current thread pointer and stack */
729a3fa7	252	p1 = THREAD_SIZE + 4 (z); /* +4 is for reti loading */
09e1f70e MF	253	sp = sp + p1;
	254	usp = sp;
	255	fp = sp;
6b3087c6 GY	256	sp += -12;
	257	call _init_pda
	258	sp += 12;
09e1f70e MF	259	jump.l _start_kernel;
	260	ENDPROC(_real_start)
	261
	262	__FINIT