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1394f032 BW |
1 | /* |
2 | * File: arch/blackfin/mach-common/ints-priority-sc.c | |
3 | * Based on: | |
4 | * Author: | |
5 | * | |
6 | * Created: ? | |
d2d50aa9 | 7 | * Description: Set up the interrupt priorities |
1394f032 BW |
8 | * |
9 | * Modified: | |
10 | * 1996 Roman Zippel | |
11 | * 1999 D. Jeff Dionne <jeff@uclinux.org> | |
12 | * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> | |
13 | * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> | |
14 | * 2003 Metrowerks/Motorola | |
15 | * 2003 Bas Vermeulen <bas@buyways.nl> | |
24a07a12 | 16 | * Copyright 2004-2007 Analog Devices Inc. |
1394f032 BW |
17 | * |
18 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; if not, see the file COPYING, or write | |
32 | * to the Free Software Foundation, Inc., | |
33 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
34 | */ | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/kernel_stat.h> | |
38 | #include <linux/seq_file.h> | |
39 | #include <linux/irq.h> | |
40 | #ifdef CONFIG_KGDB | |
41 | #include <linux/kgdb.h> | |
42 | #endif | |
43 | #include <asm/traps.h> | |
44 | #include <asm/blackfin.h> | |
45 | #include <asm/gpio.h> | |
46 | #include <asm/irq_handler.h> | |
47 | ||
48 | #ifdef BF537_FAMILY | |
49 | # define BF537_GENERIC_ERROR_INT_DEMUX | |
50 | #else | |
51 | # undef BF537_GENERIC_ERROR_INT_DEMUX | |
52 | #endif | |
53 | ||
54 | /* | |
55 | * NOTES: | |
56 | * - we have separated the physical Hardware interrupt from the | |
57 | * levels that the LINUX kernel sees (see the description in irq.h) | |
58 | * - | |
59 | */ | |
60 | ||
61 | unsigned long irq_flags = 0; | |
62 | ||
63 | /* The number of spurious interrupts */ | |
64 | atomic_t num_spurious; | |
65 | ||
66 | struct ivgx { | |
67 | /* irq number for request_irq, available in mach-bf533/irq.h */ | |
24a07a12 | 68 | unsigned int irqno; |
1394f032 | 69 | /* corresponding bit in the SIC_ISR register */ |
24a07a12 | 70 | unsigned int isrflag; |
1394f032 BW |
71 | } ivg_table[NR_PERI_INTS]; |
72 | ||
73 | struct ivg_slice { | |
74 | /* position of first irq in ivg_table for given ivg */ | |
75 | struct ivgx *ifirst; | |
76 | struct ivgx *istop; | |
77 | } ivg7_13[IVG13 - IVG7 + 1]; | |
78 | ||
79 | static void search_IAR(void); | |
80 | ||
81 | /* | |
82 | * Search SIC_IAR and fill tables with the irqvalues | |
83 | * and their positions in the SIC_ISR register. | |
84 | */ | |
85 | static void __init search_IAR(void) | |
86 | { | |
87 | unsigned ivg, irq_pos = 0; | |
88 | for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { | |
89 | int irqn; | |
90 | ||
34e0fc89 | 91 | ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos]; |
1394f032 BW |
92 | |
93 | for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { | |
94 | int iar_shift = (irqn & 7) * 4; | |
95 | if (ivg == | |
96 | (0xf & | |
34e0fc89 | 97 | bfin_read32((unsigned long *)SIC_IAR0 + |
1394f032 BW |
98 | (irqn >> 3)) >> iar_shift)) { |
99 | ivg_table[irq_pos].irqno = IVG7 + irqn; | |
24a07a12 | 100 | ivg_table[irq_pos].isrflag = 1 << (irqn % 32); |
1394f032 BW |
101 | ivg7_13[ivg].istop++; |
102 | irq_pos++; | |
103 | } | |
104 | } | |
105 | } | |
106 | } | |
107 | ||
108 | /* | |
109 | * This is for BF533 internal IRQs | |
110 | */ | |
111 | ||
112 | static void ack_noop(unsigned int irq) | |
113 | { | |
114 | /* Dummy function. */ | |
115 | } | |
116 | ||
117 | static void bfin_core_mask_irq(unsigned int irq) | |
118 | { | |
119 | irq_flags &= ~(1 << irq); | |
120 | if (!irqs_disabled()) | |
121 | local_irq_enable(); | |
122 | } | |
123 | ||
124 | static void bfin_core_unmask_irq(unsigned int irq) | |
125 | { | |
126 | irq_flags |= 1 << irq; | |
127 | /* | |
128 | * If interrupts are enabled, IMASK must contain the same value | |
129 | * as irq_flags. Make sure that invariant holds. If interrupts | |
130 | * are currently disabled we need not do anything; one of the | |
131 | * callers will take care of setting IMASK to the proper value | |
132 | * when reenabling interrupts. | |
133 | * local_irq_enable just does "STI irq_flags", so it's exactly | |
134 | * what we need. | |
135 | */ | |
136 | if (!irqs_disabled()) | |
137 | local_irq_enable(); | |
138 | return; | |
139 | } | |
140 | ||
141 | static void bfin_internal_mask_irq(unsigned int irq) | |
142 | { | |
24a07a12 | 143 | #ifndef CONFIG_BF54x |
1394f032 BW |
144 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & |
145 | ~(1 << (irq - (IRQ_CORETMR + 1)))); | |
24a07a12 RH |
146 | #else |
147 | unsigned mask_bank, mask_bit; | |
1f83b8f1 MF |
148 | mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; |
149 | mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; | |
24a07a12 RH |
150 | bfin_write_SIC_IMASK( mask_bank, bfin_read_SIC_IMASK(mask_bank) & \ |
151 | ~(1 << mask_bit)); | |
152 | #endif | |
1394f032 BW |
153 | SSYNC(); |
154 | } | |
155 | ||
156 | static void bfin_internal_unmask_irq(unsigned int irq) | |
157 | { | |
24a07a12 | 158 | #ifndef CONFIG_BF54x |
1394f032 BW |
159 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | |
160 | (1 << (irq - (IRQ_CORETMR + 1)))); | |
24a07a12 RH |
161 | #else |
162 | unsigned mask_bank, mask_bit; | |
1f83b8f1 | 163 | mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; |
24a07a12 RH |
164 | mask_bit = (irq - (IRQ_CORETMR + 1))%32; |
165 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | \ | |
166 | ( 1 << mask_bit)); | |
167 | #endif | |
1394f032 BW |
168 | SSYNC(); |
169 | } | |
170 | ||
171 | static struct irq_chip bfin_core_irqchip = { | |
172 | .ack = ack_noop, | |
173 | .mask = bfin_core_mask_irq, | |
174 | .unmask = bfin_core_unmask_irq, | |
175 | }; | |
176 | ||
177 | static struct irq_chip bfin_internal_irqchip = { | |
178 | .ack = ack_noop, | |
179 | .mask = bfin_internal_mask_irq, | |
180 | .unmask = bfin_internal_unmask_irq, | |
181 | }; | |
182 | ||
183 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | |
184 | static int error_int_mask; | |
185 | ||
186 | static void bfin_generic_error_ack_irq(unsigned int irq) | |
187 | { | |
188 | ||
189 | } | |
190 | ||
191 | static void bfin_generic_error_mask_irq(unsigned int irq) | |
192 | { | |
193 | error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR)); | |
194 | ||
195 | if (!error_int_mask) { | |
196 | local_irq_disable(); | |
197 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & | |
198 | ~(1 << | |
199 | (IRQ_GENERIC_ERROR - | |
200 | (IRQ_CORETMR + 1)))); | |
201 | SSYNC(); | |
202 | local_irq_enable(); | |
203 | } | |
204 | } | |
205 | ||
206 | static void bfin_generic_error_unmask_irq(unsigned int irq) | |
207 | { | |
208 | local_irq_disable(); | |
209 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 << | |
210 | (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1))); | |
211 | SSYNC(); | |
212 | local_irq_enable(); | |
213 | ||
214 | error_int_mask |= 1L << (irq - IRQ_PPI_ERROR); | |
215 | } | |
216 | ||
217 | static struct irq_chip bfin_generic_error_irqchip = { | |
218 | .ack = bfin_generic_error_ack_irq, | |
219 | .mask = bfin_generic_error_mask_irq, | |
220 | .unmask = bfin_generic_error_unmask_irq, | |
221 | }; | |
222 | ||
223 | static void bfin_demux_error_irq(unsigned int int_err_irq, | |
34e0fc89 | 224 | struct irq_desc *intb_desc) |
1394f032 BW |
225 | { |
226 | int irq = 0; | |
227 | ||
228 | SSYNC(); | |
229 | ||
230 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) | |
231 | if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK) | |
232 | irq = IRQ_MAC_ERROR; | |
233 | else | |
234 | #endif | |
235 | if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK) | |
236 | irq = IRQ_SPORT0_ERROR; | |
237 | else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK) | |
238 | irq = IRQ_SPORT1_ERROR; | |
239 | else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK) | |
240 | irq = IRQ_PPI_ERROR; | |
241 | else if (bfin_read_CAN_GIF() & CAN_ERR_MASK) | |
242 | irq = IRQ_CAN_ERROR; | |
243 | else if (bfin_read_SPI_STAT() & SPI_ERR_MASK) | |
244 | irq = IRQ_SPI_ERROR; | |
245 | else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) && | |
246 | (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0)) | |
247 | irq = IRQ_UART0_ERROR; | |
248 | else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) && | |
249 | (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0)) | |
250 | irq = IRQ_UART1_ERROR; | |
251 | ||
252 | if (irq) { | |
253 | if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) { | |
254 | struct irq_desc *desc = irq_desc + irq; | |
255 | desc->handle_irq(irq, desc); | |
256 | } else { | |
257 | ||
258 | switch (irq) { | |
259 | case IRQ_PPI_ERROR: | |
260 | bfin_write_PPI_STATUS(PPI_ERR_MASK); | |
261 | break; | |
262 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) | |
263 | case IRQ_MAC_ERROR: | |
264 | bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK); | |
265 | break; | |
266 | #endif | |
267 | case IRQ_SPORT0_ERROR: | |
268 | bfin_write_SPORT0_STAT(SPORT_ERR_MASK); | |
269 | break; | |
270 | ||
271 | case IRQ_SPORT1_ERROR: | |
272 | bfin_write_SPORT1_STAT(SPORT_ERR_MASK); | |
273 | break; | |
274 | ||
275 | case IRQ_CAN_ERROR: | |
276 | bfin_write_CAN_GIS(CAN_ERR_MASK); | |
277 | break; | |
278 | ||
279 | case IRQ_SPI_ERROR: | |
280 | bfin_write_SPI_STAT(SPI_ERR_MASK); | |
281 | break; | |
282 | ||
283 | default: | |
284 | break; | |
285 | } | |
286 | ||
287 | pr_debug("IRQ %d:" | |
34e0fc89 MH |
288 | " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", |
289 | irq); | |
1394f032 BW |
290 | } |
291 | } else | |
292 | printk(KERN_ERR | |
293 | "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR" | |
294 | " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", | |
295 | __FUNCTION__, __FILE__, __LINE__); | |
296 | ||
1394f032 BW |
297 | } |
298 | #endif /* BF537_GENERIC_ERROR_INT_DEMUX */ | |
299 | ||
34e0fc89 | 300 | #if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x) |
1394f032 BW |
301 | |
302 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; | |
303 | static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; | |
304 | ||
305 | static void bfin_gpio_ack_irq(unsigned int irq) | |
306 | { | |
307 | u16 gpionr = irq - IRQ_PF0; | |
308 | ||
309 | if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { | |
310 | set_gpio_data(gpionr, 0); | |
311 | SSYNC(); | |
312 | } | |
313 | } | |
314 | ||
315 | static void bfin_gpio_mask_ack_irq(unsigned int irq) | |
316 | { | |
317 | u16 gpionr = irq - IRQ_PF0; | |
318 | ||
319 | if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { | |
320 | set_gpio_data(gpionr, 0); | |
321 | SSYNC(); | |
322 | } | |
323 | ||
324 | set_gpio_maska(gpionr, 0); | |
325 | SSYNC(); | |
326 | } | |
327 | ||
328 | static void bfin_gpio_mask_irq(unsigned int irq) | |
329 | { | |
330 | set_gpio_maska(irq - IRQ_PF0, 0); | |
331 | SSYNC(); | |
332 | } | |
333 | ||
334 | static void bfin_gpio_unmask_irq(unsigned int irq) | |
335 | { | |
336 | set_gpio_maska(irq - IRQ_PF0, 1); | |
337 | SSYNC(); | |
338 | } | |
339 | ||
340 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) | |
341 | { | |
342 | unsigned int ret; | |
343 | u16 gpionr = irq - IRQ_PF0; | |
344 | ||
345 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { | |
346 | ret = gpio_request(gpionr, NULL); | |
347 | if (ret) | |
348 | return ret; | |
349 | } | |
350 | ||
351 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); | |
352 | bfin_gpio_unmask_irq(irq); | |
353 | ||
354 | return ret; | |
355 | } | |
356 | ||
357 | static void bfin_gpio_irq_shutdown(unsigned int irq) | |
358 | { | |
359 | bfin_gpio_mask_irq(irq); | |
360 | gpio_free(irq - IRQ_PF0); | |
361 | gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0); | |
362 | } | |
363 | ||
364 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | |
365 | { | |
366 | ||
367 | unsigned int ret; | |
368 | u16 gpionr = irq - IRQ_PF0; | |
369 | ||
370 | if (type == IRQ_TYPE_PROBE) { | |
371 | /* only probe unenabled GPIO interrupt lines */ | |
372 | if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)) | |
373 | return 0; | |
374 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
375 | } | |
376 | ||
377 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | |
34e0fc89 | 378 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
1394f032 BW |
379 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { |
380 | ret = gpio_request(gpionr, NULL); | |
381 | if (ret) | |
382 | return ret; | |
383 | } | |
384 | ||
385 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); | |
386 | } else { | |
387 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); | |
388 | return 0; | |
389 | } | |
390 | ||
391 | set_gpio_dir(gpionr, 0); | |
392 | set_gpio_inen(gpionr, 1); | |
393 | ||
394 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | |
395 | gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr); | |
396 | set_gpio_edge(gpionr, 1); | |
397 | } else { | |
398 | set_gpio_edge(gpionr, 0); | |
399 | gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); | |
400 | } | |
401 | ||
402 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | |
403 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | |
404 | set_gpio_both(gpionr, 1); | |
405 | else | |
406 | set_gpio_both(gpionr, 0); | |
407 | ||
408 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) | |
409 | set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */ | |
410 | else | |
411 | set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */ | |
412 | ||
413 | SSYNC(); | |
414 | ||
415 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | |
416 | set_irq_handler(irq, handle_edge_irq); | |
417 | else | |
418 | set_irq_handler(irq, handle_level_irq); | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
1394f032 BW |
423 | static struct irq_chip bfin_gpio_irqchip = { |
424 | .ack = bfin_gpio_ack_irq, | |
425 | .mask = bfin_gpio_mask_irq, | |
426 | .mask_ack = bfin_gpio_mask_ack_irq, | |
427 | .unmask = bfin_gpio_unmask_irq, | |
428 | .set_type = bfin_gpio_irq_type, | |
429 | .startup = bfin_gpio_irq_startup, | |
430 | .shutdown = bfin_gpio_irq_shutdown | |
431 | }; | |
432 | ||
433 | static void bfin_demux_gpio_irq(unsigned int intb_irq, | |
34e0fc89 | 434 | struct irq_desc *intb_desc) |
1394f032 BW |
435 | { |
436 | u16 i; | |
e3f23000 | 437 | struct irq_desc *desc; |
1394f032 | 438 | |
1f83b8f1 | 439 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) { |
1394f032 BW |
440 | int irq = IRQ_PF0 + i; |
441 | int flag_d = get_gpiop_data(i); | |
442 | int mask = | |
34e0fc89 | 443 | flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i)); |
1394f032 BW |
444 | |
445 | while (mask) { | |
446 | if (mask & 1) { | |
e3f23000 | 447 | desc = irq_desc + irq; |
1394f032 BW |
448 | desc->handle_irq(irq, desc); |
449 | } | |
450 | irq++; | |
451 | mask >>= 1; | |
452 | } | |
453 | } | |
454 | } | |
455 | ||
34e0fc89 MH |
456 | #else /* CONFIG_IRQCHIP_DEMUX_GPIO */ |
457 | ||
458 | #define NR_PINT_SYS_IRQS 4 | |
459 | #define NR_PINT_BITS 32 | |
460 | #define NR_PINTS 160 | |
461 | #define IRQ_NOT_AVAIL 0xFF | |
462 | ||
463 | #define PINT_2_BANK(x) ((x) >> 5) | |
464 | #define PINT_2_BIT(x) ((x) & 0x1F) | |
465 | #define PINT_BIT(x) (1 << (PINT_2_BIT(x))) | |
466 | ||
467 | static unsigned char irq2pint_lut[NR_PINTS]; | |
e3f23000 | 468 | static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; |
34e0fc89 MH |
469 | |
470 | struct pin_int_t { | |
471 | unsigned int mask_set; | |
472 | unsigned int mask_clear; | |
473 | unsigned int request; | |
474 | unsigned int assign; | |
475 | unsigned int edge_set; | |
476 | unsigned int edge_clear; | |
477 | unsigned int invert_set; | |
478 | unsigned int invert_clear; | |
479 | unsigned int pinstate; | |
480 | unsigned int latch; | |
481 | }; | |
482 | ||
483 | static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = { | |
484 | (struct pin_int_t *)PINT0_MASK_SET, | |
485 | (struct pin_int_t *)PINT1_MASK_SET, | |
486 | (struct pin_int_t *)PINT2_MASK_SET, | |
487 | (struct pin_int_t *)PINT3_MASK_SET, | |
488 | }; | |
489 | ||
490 | unsigned short get_irq_base(u8 bank, u8 bmap) | |
491 | { | |
492 | ||
493 | u16 irq_base; | |
494 | ||
495 | if (bank < 2) { /*PA-PB */ | |
496 | irq_base = IRQ_PA0 + bmap * 16; | |
497 | } else { /*PC-PJ */ | |
498 | irq_base = IRQ_PC0 + bmap * 16; | |
499 | } | |
500 | ||
501 | return irq_base; | |
502 | ||
503 | } | |
504 | ||
505 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ | |
506 | void init_pint_lut(void) | |
507 | { | |
508 | u16 bank, bit, irq_base, bit_pos; | |
509 | u32 pint_assign; | |
510 | u8 bmap; | |
511 | ||
512 | memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut)); | |
513 | ||
514 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { | |
515 | ||
516 | pint_assign = pint[bank]->assign; | |
517 | ||
518 | for (bit = 0; bit < NR_PINT_BITS; bit++) { | |
519 | ||
520 | bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF; | |
521 | ||
522 | irq_base = get_irq_base(bank, bmap); | |
523 | ||
524 | irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0); | |
525 | bit_pos = bit + bank * NR_PINT_BITS; | |
526 | ||
e3f23000 | 527 | pint2irq_lut[bit_pos] = irq_base - SYS_IRQS; |
34e0fc89 MH |
528 | irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; |
529 | ||
530 | } | |
531 | ||
532 | } | |
533 | ||
534 | } | |
535 | ||
536 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; | |
537 | ||
538 | static void bfin_gpio_ack_irq(unsigned int irq) | |
539 | { | |
540 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
541 | ||
542 | pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val); | |
543 | SSYNC(); | |
544 | } | |
545 | ||
546 | static void bfin_gpio_mask_ack_irq(unsigned int irq) | |
547 | { | |
548 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
e3f23000 MH |
549 | u32 pintbit = PINT_BIT(pint_val); |
550 | u8 bank = PINT_2_BANK(pint_val); | |
34e0fc89 | 551 | |
e3f23000 MH |
552 | pint[bank]->request = pintbit; |
553 | pint[bank]->mask_clear = pintbit; | |
34e0fc89 MH |
554 | SSYNC(); |
555 | } | |
556 | ||
557 | static void bfin_gpio_mask_irq(unsigned int irq) | |
558 | { | |
559 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
560 | ||
561 | pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); | |
562 | SSYNC(); | |
563 | } | |
564 | ||
565 | static void bfin_gpio_unmask_irq(unsigned int irq) | |
566 | { | |
567 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
e3f23000 MH |
568 | u32 pintbit = PINT_BIT(pint_val); |
569 | u8 bank = PINT_2_BANK(pint_val); | |
34e0fc89 | 570 | |
e3f23000 MH |
571 | pint[bank]->request = pintbit; |
572 | pint[bank]->mask_set = pintbit; | |
34e0fc89 MH |
573 | SSYNC(); |
574 | } | |
575 | ||
576 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) | |
577 | { | |
578 | unsigned int ret; | |
579 | u16 gpionr = irq - IRQ_PA0; | |
580 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
581 | ||
582 | if (pint_val == IRQ_NOT_AVAIL) | |
583 | return -ENODEV; | |
584 | ||
585 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { | |
586 | ret = gpio_request(gpionr, NULL); | |
587 | if (ret) | |
588 | return ret; | |
589 | } | |
590 | ||
591 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); | |
592 | bfin_gpio_unmask_irq(irq); | |
593 | ||
594 | return ret; | |
595 | } | |
596 | ||
597 | static void bfin_gpio_irq_shutdown(unsigned int irq) | |
598 | { | |
599 | bfin_gpio_mask_irq(irq); | |
600 | gpio_free(irq - IRQ_PA0); | |
601 | gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0); | |
602 | } | |
603 | ||
604 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | |
605 | { | |
606 | ||
607 | unsigned int ret; | |
608 | u16 gpionr = irq - IRQ_PA0; | |
609 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
e3f23000 MH |
610 | u32 pintbit = PINT_BIT(pint_val); |
611 | u8 bank = PINT_2_BANK(pint_val); | |
34e0fc89 MH |
612 | |
613 | if (pint_val == IRQ_NOT_AVAIL) | |
614 | return -ENODEV; | |
615 | ||
616 | if (type == IRQ_TYPE_PROBE) { | |
617 | /* only probe unenabled GPIO interrupt lines */ | |
618 | if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)) | |
619 | return 0; | |
620 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
621 | } | |
622 | ||
623 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | |
624 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { | |
625 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { | |
626 | ret = gpio_request(gpionr, NULL); | |
627 | if (ret) | |
628 | return ret; | |
629 | } | |
630 | ||
631 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); | |
632 | } else { | |
633 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); | |
634 | return 0; | |
635 | } | |
636 | ||
637 | gpio_direction_input(gpionr); | |
638 | ||
639 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | |
e3f23000 | 640 | pint[bank]->edge_set = pintbit; |
34e0fc89 | 641 | } else { |
e3f23000 | 642 | pint[bank]->edge_clear = pintbit; |
34e0fc89 MH |
643 | } |
644 | ||
645 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) | |
e3f23000 | 646 | pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ |
34e0fc89 | 647 | else |
e3f23000 | 648 | pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */ |
34e0fc89 MH |
649 | |
650 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | |
e3f23000 | 651 | pint[bank]->invert_set = pintbit; |
34e0fc89 | 652 | else |
e3f23000 | 653 | pint[bank]->invert_set = pintbit; |
34e0fc89 MH |
654 | |
655 | SSYNC(); | |
656 | ||
657 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | |
658 | set_irq_handler(irq, handle_edge_irq); | |
659 | else | |
660 | set_irq_handler(irq, handle_level_irq); | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
665 | static struct irq_chip bfin_gpio_irqchip = { | |
666 | .ack = bfin_gpio_ack_irq, | |
667 | .mask = bfin_gpio_mask_irq, | |
668 | .mask_ack = bfin_gpio_mask_ack_irq, | |
669 | .unmask = bfin_gpio_unmask_irq, | |
670 | .set_type = bfin_gpio_irq_type, | |
671 | .startup = bfin_gpio_irq_startup, | |
672 | .shutdown = bfin_gpio_irq_shutdown | |
673 | }; | |
674 | ||
675 | static void bfin_demux_gpio_irq(unsigned int intb_irq, | |
676 | struct irq_desc *intb_desc) | |
677 | { | |
678 | u8 bank, pint_val; | |
679 | u32 request, irq; | |
e3f23000 | 680 | struct irq_desc *desc; |
34e0fc89 MH |
681 | |
682 | switch (intb_irq) { | |
683 | case IRQ_PINT0: | |
684 | bank = 0; | |
685 | break; | |
686 | case IRQ_PINT2: | |
687 | bank = 2; | |
688 | break; | |
689 | case IRQ_PINT3: | |
690 | bank = 3; | |
691 | break; | |
692 | case IRQ_PINT1: | |
693 | bank = 1; | |
694 | break; | |
e3f23000 MH |
695 | default: |
696 | return; | |
34e0fc89 MH |
697 | } |
698 | ||
699 | pint_val = bank * NR_PINT_BITS; | |
700 | ||
701 | request = pint[bank]->request; | |
702 | ||
703 | while (request) { | |
704 | if (request & 1) { | |
e3f23000 MH |
705 | irq = pint2irq_lut[pint_val] + SYS_IRQS; |
706 | desc = irq_desc + irq; | |
34e0fc89 MH |
707 | desc->handle_irq(irq, desc); |
708 | } | |
709 | pint_val++; | |
710 | request >>= 1; | |
711 | } | |
712 | ||
713 | } | |
1394f032 BW |
714 | #endif /* CONFIG_IRQCHIP_DEMUX_GPIO */ |
715 | ||
716 | /* | |
717 | * This function should be called during kernel startup to initialize | |
718 | * the BFin IRQ handling routines. | |
719 | */ | |
720 | int __init init_arch_irq(void) | |
721 | { | |
722 | int irq; | |
723 | unsigned long ilat = 0; | |
724 | /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ | |
24a07a12 RH |
725 | #ifdef CONFIG_BF54x |
726 | bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); | |
727 | bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); | |
728 | bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); | |
1c5d2265 MH |
729 | bfin_write_SIC_IWR0(IWR_ENABLE_ALL); |
730 | bfin_write_SIC_IWR1(IWR_ENABLE_ALL); | |
731 | bfin_write_SIC_IWR2(IWR_ENABLE_ALL); | |
24a07a12 | 732 | #else |
1394f032 | 733 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); |
1c5d2265 | 734 | bfin_write_SIC_IWR(IWR_ENABLE_ALL); |
24a07a12 RH |
735 | #endif |
736 | ||
1394f032 BW |
737 | SSYNC(); |
738 | ||
739 | local_irq_disable(); | |
740 | ||
741 | #ifndef CONFIG_KGDB | |
742 | bfin_write_EVT0(evt_emulation); | |
743 | #endif | |
744 | bfin_write_EVT2(evt_evt2); | |
745 | bfin_write_EVT3(trap); | |
746 | bfin_write_EVT5(evt_ivhw); | |
747 | bfin_write_EVT6(evt_timer); | |
748 | bfin_write_EVT7(evt_evt7); | |
749 | bfin_write_EVT8(evt_evt8); | |
750 | bfin_write_EVT9(evt_evt9); | |
751 | bfin_write_EVT10(evt_evt10); | |
752 | bfin_write_EVT11(evt_evt11); | |
753 | bfin_write_EVT12(evt_evt12); | |
754 | bfin_write_EVT13(evt_evt13); | |
755 | bfin_write_EVT14(evt14_softirq); | |
756 | bfin_write_EVT15(evt_system_call); | |
757 | CSYNC(); | |
758 | ||
34e0fc89 MH |
759 | #if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x) |
760 | #ifdef CONFIG_PINTx_REASSIGN | |
761 | pint[0]->assign = CONFIG_PINT0_ASSIGN; | |
762 | pint[1]->assign = CONFIG_PINT1_ASSIGN; | |
763 | pint[2]->assign = CONFIG_PINT2_ASSIGN; | |
764 | pint[3]->assign = CONFIG_PINT3_ASSIGN; | |
765 | #endif | |
766 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ | |
767 | init_pint_lut(); | |
768 | #endif | |
769 | ||
770 | for (irq = 0; irq <= SYS_IRQS; irq++) { | |
1394f032 BW |
771 | if (irq <= IRQ_CORETMR) |
772 | set_irq_chip(irq, &bfin_core_irqchip); | |
773 | else | |
774 | set_irq_chip(irq, &bfin_internal_irqchip); | |
775 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | |
776 | if (irq != IRQ_GENERIC_ERROR) { | |
777 | #endif | |
778 | ||
34e0fc89 | 779 | switch (irq) { |
1394f032 | 780 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO |
34e0fc89 MH |
781 | #ifndef CONFIG_BF54x |
782 | case IRQ_PROG_INTA: | |
783 | set_irq_chained_handler(irq, | |
784 | bfin_demux_gpio_irq); | |
785 | break; | |
786 | #if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) | |
787 | case IRQ_MAC_RX: | |
788 | set_irq_chained_handler(irq, | |
789 | bfin_demux_gpio_irq); | |
790 | break; | |
1394f032 | 791 | #endif |
34e0fc89 MH |
792 | #else |
793 | case IRQ_PINT0: | |
1394f032 BW |
794 | set_irq_chained_handler(irq, |
795 | bfin_demux_gpio_irq); | |
34e0fc89 MH |
796 | break; |
797 | case IRQ_PINT1: | |
798 | set_irq_chained_handler(irq, | |
799 | bfin_demux_gpio_irq); | |
800 | break; | |
801 | case IRQ_PINT2: | |
802 | set_irq_chained_handler(irq, | |
803 | bfin_demux_gpio_irq); | |
804 | break; | |
805 | case IRQ_PINT3: | |
806 | set_irq_chained_handler(irq, | |
807 | bfin_demux_gpio_irq); | |
808 | break; | |
809 | #endif /*CONFIG_BF54x */ | |
1394f032 | 810 | #endif |
34e0fc89 MH |
811 | default: |
812 | set_irq_handler(irq, handle_simple_irq); | |
813 | break; | |
814 | } | |
1394f032 BW |
815 | |
816 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | |
817 | } else { | |
818 | set_irq_handler(irq, bfin_demux_error_irq); | |
819 | } | |
820 | #endif | |
821 | } | |
822 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | |
823 | for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) { | |
824 | set_irq_chip(irq, &bfin_generic_error_irqchip); | |
825 | set_irq_handler(irq, handle_level_irq); | |
826 | } | |
827 | #endif | |
828 | ||
829 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO | |
34e0fc89 | 830 | #ifndef CONFIG_BF54x |
1394f032 | 831 | for (irq = IRQ_PF0; irq < NR_IRQS; irq++) { |
34e0fc89 MH |
832 | #else |
833 | for (irq = IRQ_PA0; irq < NR_IRQS; irq++) { | |
834 | #endif | |
1394f032 BW |
835 | set_irq_chip(irq, &bfin_gpio_irqchip); |
836 | /* if configured as edge, then will be changed to do_edge_IRQ */ | |
837 | set_irq_handler(irq, handle_level_irq); | |
838 | } | |
839 | #endif | |
840 | bfin_write_IMASK(0); | |
841 | CSYNC(); | |
842 | ilat = bfin_read_ILAT(); | |
843 | CSYNC(); | |
844 | bfin_write_ILAT(ilat); | |
845 | CSYNC(); | |
846 | ||
34e0fc89 | 847 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); |
1394f032 BW |
848 | /* IMASK=xxx is equivalent to STI xx or irq_flags=xx, |
849 | * local_irq_enable() | |
850 | */ | |
851 | program_IAR(); | |
852 | /* Therefore it's better to setup IARs before interrupts enabled */ | |
853 | search_IAR(); | |
854 | ||
855 | /* Enable interrupts IVG7-15 */ | |
856 | irq_flags = irq_flags | IMASK_IVG15 | | |
857 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | | |
34e0fc89 | 858 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
1394f032 BW |
859 | |
860 | return 0; | |
861 | } | |
862 | ||
863 | #ifdef CONFIG_DO_IRQ_L1 | |
34e0fc89 | 864 | void do_irq(int vec, struct pt_regs *fp) __attribute__((l1_text)); |
1394f032 BW |
865 | #endif |
866 | ||
867 | void do_irq(int vec, struct pt_regs *fp) | |
868 | { | |
869 | if (vec == EVT_IVTMR_P) { | |
870 | vec = IRQ_CORETMR; | |
871 | } else { | |
872 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; | |
873 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; | |
24a07a12 RH |
874 | #ifdef CONFIG_BF54x |
875 | unsigned long sic_status[3]; | |
1394f032 | 876 | |
24a07a12 RH |
877 | SSYNC(); |
878 | sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0); | |
879 | sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1); | |
880 | sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2); | |
e3f23000 MH |
881 | |
882 | ||
1f83b8f1 | 883 | for (;; ivg++) { |
24a07a12 RH |
884 | if (ivg >= ivg_stop) { |
885 | atomic_inc(&num_spurious); | |
886 | return; | |
887 | } | |
34e0fc89 | 888 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) |
24a07a12 RH |
889 | break; |
890 | } | |
891 | #else | |
892 | unsigned long sic_status; | |
1394f032 BW |
893 | SSYNC(); |
894 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); | |
895 | ||
896 | for (;; ivg++) { | |
897 | if (ivg >= ivg_stop) { | |
898 | atomic_inc(&num_spurious); | |
899 | return; | |
900 | } else if (sic_status & ivg->isrflag) | |
901 | break; | |
902 | } | |
24a07a12 | 903 | #endif |
1394f032 BW |
904 | vec = ivg->irqno; |
905 | } | |
906 | asm_do_IRQ(vec, fp); | |
907 | ||
908 | #ifdef CONFIG_KGDB | |
909 | kgdb_process_breakpoint(); | |
910 | #endif | |
911 | } |