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Blackfin arch: Enable BF54x PIN/GPIO interrupts
[deliverable/linux.git] / arch / blackfin / mach-common / ints-priority-sc.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/mach-common/ints-priority-sc.c
3 * Based on:
4 * Author:
5 *
6 * Created: ?
d2d50aa9 7 * Description: Set up the interrupt priorities
1394f032
BW		 8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
24a07a12 16 * Copyright 2004-2007 Analog Devices Inc.
1394f032
BW		 17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36#include <linux/module.h>
37#include <linux/kernel_stat.h>
38#include <linux/seq_file.h>
39#include <linux/irq.h>
40#ifdef CONFIG_KGDB
41#include <linux/kgdb.h>
42#endif
43#include <asm/traps.h>
44#include <asm/blackfin.h>
45#include <asm/gpio.h>
46#include <asm/irq_handler.h>
47
48#ifdef BF537_FAMILY
49# define BF537_GENERIC_ERROR_INT_DEMUX
50#else
51# undef BF537_GENERIC_ERROR_INT_DEMUX
52#endif
53
54/*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
61unsigned long irq_flags = 0;
62
63/* The number of spurious interrupts */
64atomic_t num_spurious;
65
66struct ivgx {
67 /* irq number for request_irq, available in mach-bf533/irq.h */
24a07a12 68 unsigned int irqno;
1394f032 69 /* corresponding bit in the SIC_ISR register */
24a07a12 70 unsigned int isrflag;
1394f032
BW		 71} ivg_table[NR_PERI_INTS];
72
73struct ivg_slice {
74 /* position of first irq in ivg_table for given ivg */
75 struct ivgx *ifirst;
76 struct ivgx *istop;
77} ivg7_13[IVG13 - IVG7 + 1];
78
79static void search_IAR(void);
80
81/*
82 * Search SIC_IAR and fill tables with the irqvalues
83 * and their positions in the SIC_ISR register.
84 */
85static void __init search_IAR(void)
86{
87 unsigned ivg, irq_pos = 0;
88 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
89 int irqn;
90
34e0fc89 91 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
1394f032
BW		 92
93 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
94 int iar_shift = (irqn & 7) * 4;
95 if (ivg ==
96 (0xf &
34e0fc89 97 bfin_read32((unsigned long *)SIC_IAR0 +
1394f032
BW		 98 (irqn >> 3)) >> iar_shift)) {
99 ivg_table[irq_pos].irqno = IVG7 + irqn;
24a07a12 100 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
1394f032
BW		 101 ivg7_13[ivg].istop++;
102 irq_pos++;
103 }
104 }
105 }
106}
107
108/*
109 * This is for BF533 internal IRQs
110 */
111
112static void ack_noop(unsigned int irq)
113{
114 /* Dummy function. */
115}
116
117static void bfin_core_mask_irq(unsigned int irq)
118{
119 irq_flags &= ~(1 << irq);
120 if (!irqs_disabled())
121 local_irq_enable();
122}
123
124static void bfin_core_unmask_irq(unsigned int irq)
125{
126 irq_flags |= 1 << irq;
127 /*
128 * If interrupts are enabled, IMASK must contain the same value
129 * as irq_flags. Make sure that invariant holds. If interrupts
130 * are currently disabled we need not do anything; one of the
131 * callers will take care of setting IMASK to the proper value
132 * when reenabling interrupts.
133 * local_irq_enable just does "STI irq_flags", so it's exactly
134 * what we need.
135 */
136 if (!irqs_disabled())
137 local_irq_enable();
138 return;
139}
140
141static void bfin_internal_mask_irq(unsigned int irq)
142{
24a07a12 143#ifndef CONFIG_BF54x
1394f032
BW		 144 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
145 ~(1 << (irq - (IRQ_CORETMR + 1))));
24a07a12
RH		 146#else
147 unsigned mask_bank, mask_bit;
1f83b8f1
MF		 148 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
149 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
24a07a12
RH		 150 bfin_write_SIC_IMASK( mask_bank, bfin_read_SIC_IMASK(mask_bank) & \
151 ~(1 << mask_bit));
152#endif
1394f032
BW		 153 SSYNC();
154}
155
156static void bfin_internal_unmask_irq(unsigned int irq)
157{
24a07a12 158#ifndef CONFIG_BF54x
1394f032
BW		 159 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
160 (1 << (irq - (IRQ_CORETMR + 1))));
24a07a12
RH		 161#else
162 unsigned mask_bank, mask_bit;
1f83b8f1 163 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
24a07a12
RH		 164 mask_bit = (irq - (IRQ_CORETMR + 1))%32;
165 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | \
166 ( 1 << mask_bit));
167#endif
1394f032
BW		 168 SSYNC();
169}
170
171static struct irq_chip bfin_core_irqchip = {
172 .ack = ack_noop,
173 .mask = bfin_core_mask_irq,
174 .unmask = bfin_core_unmask_irq,
175};
176
177static struct irq_chip bfin_internal_irqchip = {
178 .ack = ack_noop,
179 .mask = bfin_internal_mask_irq,
180 .unmask = bfin_internal_unmask_irq,
181};
182
183#ifdef BF537_GENERIC_ERROR_INT_DEMUX
184static int error_int_mask;
185
186static void bfin_generic_error_ack_irq(unsigned int irq)
187{
188
189}
190
191static void bfin_generic_error_mask_irq(unsigned int irq)
192{
193 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
194
195 if (!error_int_mask) {
196 local_irq_disable();
197 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
198 ~(1 <<
199 (IRQ_GENERIC_ERROR -
200 (IRQ_CORETMR + 1))));
201 SSYNC();
202 local_irq_enable();
203 }
204}
205
206static void bfin_generic_error_unmask_irq(unsigned int irq)
207{
208 local_irq_disable();
209 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
210 (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
211 SSYNC();
212 local_irq_enable();
213
214 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
215}
216
217static struct irq_chip bfin_generic_error_irqchip = {
218 .ack = bfin_generic_error_ack_irq,
219 .mask = bfin_generic_error_mask_irq,
220 .unmask = bfin_generic_error_unmask_irq,
221};
222
223static void bfin_demux_error_irq(unsigned int int_err_irq,
34e0fc89 224 struct irq_desc *intb_desc)
1394f032
BW		 225{
226 int irq = 0;
227
228 SSYNC();
229
230#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
231 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
232 irq = IRQ_MAC_ERROR;
233 else
234#endif
235 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
236 irq = IRQ_SPORT0_ERROR;
237 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
238 irq = IRQ_SPORT1_ERROR;
239 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
240 irq = IRQ_PPI_ERROR;
241 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
242 irq = IRQ_CAN_ERROR;
243 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
244 irq = IRQ_SPI_ERROR;
245 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
246 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
247 irq = IRQ_UART0_ERROR;
248 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
249 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
250 irq = IRQ_UART1_ERROR;
251
252 if (irq) {
253 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
254 struct irq_desc *desc = irq_desc + irq;
255 desc->handle_irq(irq, desc);
256 } else {
257
258 switch (irq) {
259 case IRQ_PPI_ERROR:
260 bfin_write_PPI_STATUS(PPI_ERR_MASK);
261 break;
262#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
263 case IRQ_MAC_ERROR:
264 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
265 break;
266#endif
267 case IRQ_SPORT0_ERROR:
268 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
269 break;
270
271 case IRQ_SPORT1_ERROR:
272 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
273 break;
274
275 case IRQ_CAN_ERROR:
276 bfin_write_CAN_GIS(CAN_ERR_MASK);
277 break;
278
279 case IRQ_SPI_ERROR:
280 bfin_write_SPI_STAT(SPI_ERR_MASK);
281 break;
282
283 default:
284 break;
285 }
286
287 pr_debug("IRQ %d:"
34e0fc89
MH		 288 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
289 irq);
1394f032
BW		 290 }
291 } else
292 printk(KERN_ERR
293 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
294 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
295 __FUNCTION__, __FILE__, __LINE__);
296
1394f032
BW		 297}
298#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
299
34e0fc89 300#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x)
1394f032
BW		 301
302static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
303static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
304
305static void bfin_gpio_ack_irq(unsigned int irq)
306{
307 u16 gpionr = irq - IRQ_PF0;
308
309 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
310 set_gpio_data(gpionr, 0);
311 SSYNC();
312 }
313}
314
315static void bfin_gpio_mask_ack_irq(unsigned int irq)
316{
317 u16 gpionr = irq - IRQ_PF0;
318
319 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
320 set_gpio_data(gpionr, 0);
321 SSYNC();
322 }
323
324 set_gpio_maska(gpionr, 0);
325 SSYNC();
326}
327
328static void bfin_gpio_mask_irq(unsigned int irq)
329{
330 set_gpio_maska(irq - IRQ_PF0, 0);
331 SSYNC();
332}
333
334static void bfin_gpio_unmask_irq(unsigned int irq)
335{
336 set_gpio_maska(irq - IRQ_PF0, 1);
337 SSYNC();
338}
339
340static unsigned int bfin_gpio_irq_startup(unsigned int irq)
341{
342 unsigned int ret;
343 u16 gpionr = irq - IRQ_PF0;
344
345 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
346 ret = gpio_request(gpionr, NULL);
347 if (ret)
348 return ret;
349 }
350
351 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
352 bfin_gpio_unmask_irq(irq);
353
354 return ret;
355}
356
357static void bfin_gpio_irq_shutdown(unsigned int irq)
358{
359 bfin_gpio_mask_irq(irq);
360 gpio_free(irq - IRQ_PF0);
361 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
362}
363
364static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
365{
366
367 unsigned int ret;
368 u16 gpionr = irq - IRQ_PF0;
369
370 if (type == IRQ_TYPE_PROBE) {
371 /* only probe unenabled GPIO interrupt lines */
372 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
373 return 0;
374 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
375 }
376
377 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
34e0fc89 378 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1394f032
BW		 379 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
380 ret = gpio_request(gpionr, NULL);
381 if (ret)
382 return ret;
383 }
384
385 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
386 } else {
387 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
388 return 0;
389 }
390
391 set_gpio_dir(gpionr, 0);
392 set_gpio_inen(gpionr, 1);
393
394 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
395 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
396 set_gpio_edge(gpionr, 1);
397 } else {
398 set_gpio_edge(gpionr, 0);
399 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
400 }
401
402 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
403 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
404 set_gpio_both(gpionr, 1);
405 else
406 set_gpio_both(gpionr, 0);
407
408 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
409 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
410 else
411 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
412
413 SSYNC();
414
415 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
416 set_irq_handler(irq, handle_edge_irq);
417 else
418 set_irq_handler(irq, handle_level_irq);
419
420 return 0;
421}
422
1394f032
BW		 423static struct irq_chip bfin_gpio_irqchip = {
424 .ack = bfin_gpio_ack_irq,
425 .mask = bfin_gpio_mask_irq,
426 .mask_ack = bfin_gpio_mask_ack_irq,
427 .unmask = bfin_gpio_unmask_irq,
428 .set_type = bfin_gpio_irq_type,
429 .startup = bfin_gpio_irq_startup,
430 .shutdown = bfin_gpio_irq_shutdown
431};
432
433static void bfin_demux_gpio_irq(unsigned int intb_irq,
34e0fc89 434 struct irq_desc *intb_desc)
1394f032
BW		 435{
436 u16 i;
437
1f83b8f1 438 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
1394f032
BW		 439 int irq = IRQ_PF0 + i;
440 int flag_d = get_gpiop_data(i);
441 int mask =
34e0fc89 442 flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i));
1394f032
BW		 443
444 while (mask) {
445 if (mask & 1) {
446 struct irq_desc *desc = irq_desc + irq;
447 desc->handle_irq(irq, desc);
448 }
449 irq++;
450 mask >>= 1;
451 }
452 }
453}
454
34e0fc89
MH		 455#else /* CONFIG_IRQCHIP_DEMUX_GPIO */
456
457#define NR_PINT_SYS_IRQS 4
458#define NR_PINT_BITS 32
459#define NR_PINTS 160
460#define IRQ_NOT_AVAIL 0xFF
461
462#define PINT_2_BANK(x) ((x) >> 5)
463#define PINT_2_BIT(x) ((x) & 0x1F)
464#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
465
466static unsigned char irq2pint_lut[NR_PINTS];
467static unsigned short pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
468
469struct pin_int_t {
470 unsigned int mask_set;
471 unsigned int mask_clear;
472 unsigned int request;
473 unsigned int assign;
474 unsigned int edge_set;
475 unsigned int edge_clear;
476 unsigned int invert_set;
477 unsigned int invert_clear;
478 unsigned int pinstate;
479 unsigned int latch;
480};
481
482static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
483 (struct pin_int_t *)PINT0_MASK_SET,
484 (struct pin_int_t *)PINT1_MASK_SET,
485 (struct pin_int_t *)PINT2_MASK_SET,
486 (struct pin_int_t *)PINT3_MASK_SET,
487};
488
489unsigned short get_irq_base(u8 bank, u8 bmap)
490{
491
492 u16 irq_base;
493
494 if (bank < 2) { /*PA-PB */
495 irq_base = IRQ_PA0 + bmap * 16;
496 } else { /*PC-PJ */
497 irq_base = IRQ_PC0 + bmap * 16;
498 }
499
500 return irq_base;
501
502}
503
504 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
505void init_pint_lut(void)
506{
507 u16 bank, bit, irq_base, bit_pos;
508 u32 pint_assign;
509 u8 bmap;
510
511 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
512
513 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
514
515 pint_assign = pint[bank]->assign;
516
517 for (bit = 0; bit < NR_PINT_BITS; bit++) {
518
519 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
520
521 irq_base = get_irq_base(bank, bmap);
522
523 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
524 bit_pos = bit + bank * NR_PINT_BITS;
525
526 pint2irq_lut[bit_pos] = irq_base;
527 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
528
529 }
530
531 }
532
533}
534
535static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
536
537static void bfin_gpio_ack_irq(unsigned int irq)
538{
539 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
540
541 pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
542 SSYNC();
543}
544
545static void bfin_gpio_mask_ack_irq(unsigned int irq)
546{
547 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
548
549 pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
550 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
551 SSYNC();
552}
553
554static void bfin_gpio_mask_irq(unsigned int irq)
555{
556 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
557
558 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
559 SSYNC();
560}
561
562static void bfin_gpio_unmask_irq(unsigned int irq)
563{
564 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
565
566 pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
567 pint[PINT_2_BANK(pint_val)]->mask_set = PINT_BIT(pint_val);
568 SSYNC();
569}
570
571static unsigned int bfin_gpio_irq_startup(unsigned int irq)
572{
573 unsigned int ret;
574 u16 gpionr = irq - IRQ_PA0;
575 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
576
577 if (pint_val == IRQ_NOT_AVAIL)
578 return -ENODEV;
579
580 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
581 ret = gpio_request(gpionr, NULL);
582 if (ret)
583 return ret;
584 }
585
586 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
587 bfin_gpio_unmask_irq(irq);
588
589 return ret;
590}
591
592static void bfin_gpio_irq_shutdown(unsigned int irq)
593{
594 bfin_gpio_mask_irq(irq);
595 gpio_free(irq - IRQ_PA0);
596 gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0);
597}
598
599static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
600{
601
602 unsigned int ret;
603 u16 gpionr = irq - IRQ_PA0;
604 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
605
606 if (pint_val == IRQ_NOT_AVAIL)
607 return -ENODEV;
608
609 if (type == IRQ_TYPE_PROBE) {
610 /* only probe unenabled GPIO interrupt lines */
611 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
612 return 0;
613 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
614 }
615
616 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
617 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
618 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
619 ret = gpio_request(gpionr, NULL);
620 if (ret)
621 return ret;
622 }
623
624 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
625 } else {
626 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
627 return 0;
628 }
629
630 gpio_direction_input(gpionr);
631
632 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
633 pint[PINT_2_BANK(pint_val)]->edge_set = PINT_BIT(pint_val);
634 } else {
635 pint[PINT_2_BANK(pint_val)]->edge_clear = PINT_BIT(pint_val);
636 }
637
638 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
639 pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); /* low or falling edge denoted by one */
640 else
641 pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); /* high or rising edge denoted by zero */
642
643 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
644 pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val);
645 else
646 pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val);
647
648 SSYNC();
649
650 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
651 set_irq_handler(irq, handle_edge_irq);
652 else
653 set_irq_handler(irq, handle_level_irq);
654
655 return 0;
656}
657
658static struct irq_chip bfin_gpio_irqchip = {
659 .ack = bfin_gpio_ack_irq,
660 .mask = bfin_gpio_mask_irq,
661 .mask_ack = bfin_gpio_mask_ack_irq,
662 .unmask = bfin_gpio_unmask_irq,
663 .set_type = bfin_gpio_irq_type,
664 .startup = bfin_gpio_irq_startup,
665 .shutdown = bfin_gpio_irq_shutdown
666};
667
668static void bfin_demux_gpio_irq(unsigned int intb_irq,
669 struct irq_desc *intb_desc)
670{
671 u8 bank, pint_val;
672 u32 request, irq;
673
674 switch (intb_irq) {
675 case IRQ_PINT0:
676 bank = 0;
677 break;
678 case IRQ_PINT2:
679 bank = 2;
680 break;
681 case IRQ_PINT3:
682 bank = 3;
683 break;
684 case IRQ_PINT1:
685 bank = 1;
686 break;
687 }
688
689 pint_val = bank * NR_PINT_BITS;
690
691 request = pint[bank]->request;
692
693 while (request) {
694 if (request & 1) {
695 irq = pint2irq_lut[pint_val];
696 struct irq_desc *desc = irq_desc + irq;
697 desc->handle_irq(irq, desc);
698 }
699 pint_val++;
700 request >>= 1;
701 }
702
703}
1394f032
BW		 704#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */
705
706/*
707 * This function should be called during kernel startup to initialize
708 * the BFin IRQ handling routines.
709 */
710int __init init_arch_irq(void)
711{
712 int irq;
713 unsigned long ilat = 0;
714 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
24a07a12
RH		 715#ifdef CONFIG_BF54x
716 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
717 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
718 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1c5d2265
MH		 719 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
720 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
721 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
24a07a12 722#else
1394f032 723 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1c5d2265 724 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
24a07a12
RH		 725#endif
726
1394f032
BW		 727 SSYNC();
728
729 local_irq_disable();
730
731#ifndef CONFIG_KGDB
732 bfin_write_EVT0(evt_emulation);
733#endif
734 bfin_write_EVT2(evt_evt2);
735 bfin_write_EVT3(trap);
736 bfin_write_EVT5(evt_ivhw);
737 bfin_write_EVT6(evt_timer);
738 bfin_write_EVT7(evt_evt7);
739 bfin_write_EVT8(evt_evt8);
740 bfin_write_EVT9(evt_evt9);
741 bfin_write_EVT10(evt_evt10);
742 bfin_write_EVT11(evt_evt11);
743 bfin_write_EVT12(evt_evt12);
744 bfin_write_EVT13(evt_evt13);
745 bfin_write_EVT14(evt14_softirq);
746 bfin_write_EVT15(evt_system_call);
747 CSYNC();
748
34e0fc89
MH		 749#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x)
750#ifdef CONFIG_PINTx_REASSIGN
751 pint[0]->assign = CONFIG_PINT0_ASSIGN;
752 pint[1]->assign = CONFIG_PINT1_ASSIGN;
753 pint[2]->assign = CONFIG_PINT2_ASSIGN;
754 pint[3]->assign = CONFIG_PINT3_ASSIGN;
755#endif
756 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
757 init_pint_lut();
758#endif
759
760 for (irq = 0; irq <= SYS_IRQS; irq++) {
1394f032
BW		 761 if (irq <= IRQ_CORETMR)
762 set_irq_chip(irq, &bfin_core_irqchip);
763 else
764 set_irq_chip(irq, &bfin_internal_irqchip);
765#ifdef BF537_GENERIC_ERROR_INT_DEMUX
766 if (irq != IRQ_GENERIC_ERROR) {
767#endif
768
34e0fc89 769 switch (irq) {
1394f032 770#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
34e0fc89
MH		 771#ifndef CONFIG_BF54x
772 case IRQ_PROG_INTA:
773 set_irq_chained_handler(irq,
774 bfin_demux_gpio_irq);
775 break;
776#if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
777 case IRQ_MAC_RX:
778 set_irq_chained_handler(irq,
779 bfin_demux_gpio_irq);
780 break;
1394f032 781#endif
34e0fc89
MH		 782#else
783 case IRQ_PINT0:
1394f032
BW		 784 set_irq_chained_handler(irq,
785 bfin_demux_gpio_irq);
34e0fc89
MH		 786 break;
787 case IRQ_PINT1:
788 set_irq_chained_handler(irq,
789 bfin_demux_gpio_irq);
790 break;
791 case IRQ_PINT2:
792 set_irq_chained_handler(irq,
793 bfin_demux_gpio_irq);
794 break;
795 case IRQ_PINT3:
796 set_irq_chained_handler(irq,
797 bfin_demux_gpio_irq);
798 break;
799#endif /*CONFIG_BF54x */
1394f032 800#endif
34e0fc89
MH		 801 default:
802 set_irq_handler(irq, handle_simple_irq);
803 break;
804 }
1394f032
BW		 805
806#ifdef BF537_GENERIC_ERROR_INT_DEMUX
807 } else {
808 set_irq_handler(irq, bfin_demux_error_irq);
809 }
810#endif
811 }
812#ifdef BF537_GENERIC_ERROR_INT_DEMUX
813 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) {
814 set_irq_chip(irq, &bfin_generic_error_irqchip);
815 set_irq_handler(irq, handle_level_irq);
816 }
817#endif
818
819#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
34e0fc89 820#ifndef CONFIG_BF54x
1394f032 821 for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
34e0fc89
MH		 822#else
823 for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
824#endif
1394f032
BW		 825 set_irq_chip(irq, &bfin_gpio_irqchip);
826 /* if configured as edge, then will be changed to do_edge_IRQ */
827 set_irq_handler(irq, handle_level_irq);
828 }
829#endif
830 bfin_write_IMASK(0);
831 CSYNC();
832 ilat = bfin_read_ILAT();
833 CSYNC();
834 bfin_write_ILAT(ilat);
835 CSYNC();
836
34e0fc89 837 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1394f032
BW		 838 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
839 * local_irq_enable()
840 */
841 program_IAR();
842 /* Therefore it's better to setup IARs before interrupts enabled */
843 search_IAR();
844
845 /* Enable interrupts IVG7-15 */
846 irq_flags = irq_flags | IMASK_IVG15 |
847 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
34e0fc89 848 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1394f032
BW		 849
850 return 0;
851}
852
853#ifdef CONFIG_DO_IRQ_L1
34e0fc89 854void do_irq(int vec, struct pt_regs *fp) __attribute__((l1_text));
1394f032
BW		 855#endif
856
857void do_irq(int vec, struct pt_regs *fp)
858{
859 if (vec == EVT_IVTMR_P) {
860 vec = IRQ_CORETMR;
861 } else {
862 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
863 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
24a07a12
RH		 864#ifdef CONFIG_BF54x
865 unsigned long sic_status[3];
1394f032 866
24a07a12
RH		 867 SSYNC();
868 sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
869 sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
870 sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
871 SSYNC();
1f83b8f1 872 for (;; ivg++) {
24a07a12
RH		 873 if (ivg >= ivg_stop) {
874 atomic_inc(&num_spurious);
875 return;
876 }
34e0fc89 877 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
24a07a12
RH		 878 break;
879 }
880#else
881 unsigned long sic_status;
1394f032
BW		 882 SSYNC();
883 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
884
885 for (;; ivg++) {
886 if (ivg >= ivg_stop) {
887 atomic_inc(&num_spurious);
888 return;
889 } else if (sic_status & ivg->isrflag)
890 break;
891 }
24a07a12 892#endif
1394f032
BW		 893 vec = ivg->irqno;
894 }
895 asm_do_IRQ(vec, fp);
896
897#ifdef CONFIG_KGDB
898 kgdb_process_breakpoint();
899#endif
900}
Linux kernel - Deliverables
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