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1394f032 BW |
1 | /* |
2 | * File: arch/blackfin/mach-common/ints-priority-sc.c | |
3 | * Based on: | |
4 | * Author: | |
5 | * | |
6 | * Created: ? | |
d2d50aa9 | 7 | * Description: Set up the interrupt priorities |
1394f032 BW |
8 | * |
9 | * Modified: | |
10 | * 1996 Roman Zippel | |
11 | * 1999 D. Jeff Dionne <jeff@uclinux.org> | |
12 | * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> | |
13 | * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> | |
14 | * 2003 Metrowerks/Motorola | |
15 | * 2003 Bas Vermeulen <bas@buyways.nl> | |
24a07a12 | 16 | * Copyright 2004-2007 Analog Devices Inc. |
1394f032 BW |
17 | * |
18 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; if not, see the file COPYING, or write | |
32 | * to the Free Software Foundation, Inc., | |
33 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
34 | */ | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/kernel_stat.h> | |
38 | #include <linux/seq_file.h> | |
39 | #include <linux/irq.h> | |
40 | #ifdef CONFIG_KGDB | |
41 | #include <linux/kgdb.h> | |
42 | #endif | |
43 | #include <asm/traps.h> | |
44 | #include <asm/blackfin.h> | |
45 | #include <asm/gpio.h> | |
46 | #include <asm/irq_handler.h> | |
47 | ||
48 | #ifdef BF537_FAMILY | |
49 | # define BF537_GENERIC_ERROR_INT_DEMUX | |
50 | #else | |
51 | # undef BF537_GENERIC_ERROR_INT_DEMUX | |
52 | #endif | |
53 | ||
54 | /* | |
55 | * NOTES: | |
56 | * - we have separated the physical Hardware interrupt from the | |
57 | * levels that the LINUX kernel sees (see the description in irq.h) | |
58 | * - | |
59 | */ | |
60 | ||
a99bbccd MF |
61 | /* Initialize this to an actual value to force it into the .data |
62 | * section so that we know it is properly initialized at entry into | |
63 | * the kernel but before bss is initialized to zero (which is where | |
64 | * it would live otherwise). The 0x1f magic represents the IRQs we | |
65 | * cannot actually mask out in hardware. | |
66 | */ | |
67 | unsigned long irq_flags = 0x1f; | |
1394f032 BW |
68 | |
69 | /* The number of spurious interrupts */ | |
70 | atomic_t num_spurious; | |
71 | ||
72 | struct ivgx { | |
73 | /* irq number for request_irq, available in mach-bf533/irq.h */ | |
24a07a12 | 74 | unsigned int irqno; |
1394f032 | 75 | /* corresponding bit in the SIC_ISR register */ |
24a07a12 | 76 | unsigned int isrflag; |
1394f032 BW |
77 | } ivg_table[NR_PERI_INTS]; |
78 | ||
79 | struct ivg_slice { | |
80 | /* position of first irq in ivg_table for given ivg */ | |
81 | struct ivgx *ifirst; | |
82 | struct ivgx *istop; | |
83 | } ivg7_13[IVG13 - IVG7 + 1]; | |
84 | ||
85 | static void search_IAR(void); | |
86 | ||
87 | /* | |
88 | * Search SIC_IAR and fill tables with the irqvalues | |
89 | * and their positions in the SIC_ISR register. | |
90 | */ | |
91 | static void __init search_IAR(void) | |
92 | { | |
93 | unsigned ivg, irq_pos = 0; | |
94 | for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { | |
95 | int irqn; | |
96 | ||
34e0fc89 | 97 | ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos]; |
1394f032 BW |
98 | |
99 | for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { | |
100 | int iar_shift = (irqn & 7) * 4; | |
2c4f829b | 101 | if (ivg == (0xf & |
59003145 | 102 | #ifndef CONFIG_BF52x |
34e0fc89 | 103 | bfin_read32((unsigned long *)SIC_IAR0 + |
1394f032 | 104 | (irqn >> 3)) >> iar_shift)) { |
59003145 MH |
105 | #else |
106 | bfin_read32((unsigned long *)SIC_IAR0 + | |
107 | ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) { | |
108 | #endif | |
1394f032 | 109 | ivg_table[irq_pos].irqno = IVG7 + irqn; |
24a07a12 | 110 | ivg_table[irq_pos].isrflag = 1 << (irqn % 32); |
1394f032 BW |
111 | ivg7_13[ivg].istop++; |
112 | irq_pos++; | |
113 | } | |
114 | } | |
115 | } | |
116 | } | |
117 | ||
118 | /* | |
119 | * This is for BF533 internal IRQs | |
120 | */ | |
121 | ||
122 | static void ack_noop(unsigned int irq) | |
123 | { | |
124 | /* Dummy function. */ | |
125 | } | |
126 | ||
127 | static void bfin_core_mask_irq(unsigned int irq) | |
128 | { | |
129 | irq_flags &= ~(1 << irq); | |
130 | if (!irqs_disabled()) | |
131 | local_irq_enable(); | |
132 | } | |
133 | ||
134 | static void bfin_core_unmask_irq(unsigned int irq) | |
135 | { | |
136 | irq_flags |= 1 << irq; | |
137 | /* | |
138 | * If interrupts are enabled, IMASK must contain the same value | |
139 | * as irq_flags. Make sure that invariant holds. If interrupts | |
140 | * are currently disabled we need not do anything; one of the | |
141 | * callers will take care of setting IMASK to the proper value | |
142 | * when reenabling interrupts. | |
143 | * local_irq_enable just does "STI irq_flags", so it's exactly | |
144 | * what we need. | |
145 | */ | |
146 | if (!irqs_disabled()) | |
147 | local_irq_enable(); | |
148 | return; | |
149 | } | |
150 | ||
151 | static void bfin_internal_mask_irq(unsigned int irq) | |
152 | { | |
59003145 | 153 | #ifdef CONFIG_BF53x |
1394f032 BW |
154 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & |
155 | ~(1 << (irq - (IRQ_CORETMR + 1)))); | |
24a07a12 RH |
156 | #else |
157 | unsigned mask_bank, mask_bit; | |
1f83b8f1 MF |
158 | mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; |
159 | mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; | |
c04d66bb BW |
160 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & |
161 | ~(1 << mask_bit)); | |
24a07a12 | 162 | #endif |
1394f032 BW |
163 | SSYNC(); |
164 | } | |
165 | ||
166 | static void bfin_internal_unmask_irq(unsigned int irq) | |
167 | { | |
59003145 | 168 | #ifdef CONFIG_BF53x |
1394f032 BW |
169 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | |
170 | (1 << (irq - (IRQ_CORETMR + 1)))); | |
24a07a12 RH |
171 | #else |
172 | unsigned mask_bank, mask_bit; | |
1f83b8f1 | 173 | mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; |
c04d66bb BW |
174 | mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; |
175 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | | |
176 | (1 << mask_bit)); | |
24a07a12 | 177 | #endif |
1394f032 BW |
178 | SSYNC(); |
179 | } | |
180 | ||
181 | static struct irq_chip bfin_core_irqchip = { | |
182 | .ack = ack_noop, | |
183 | .mask = bfin_core_mask_irq, | |
184 | .unmask = bfin_core_unmask_irq, | |
185 | }; | |
186 | ||
187 | static struct irq_chip bfin_internal_irqchip = { | |
188 | .ack = ack_noop, | |
189 | .mask = bfin_internal_mask_irq, | |
190 | .unmask = bfin_internal_unmask_irq, | |
191 | }; | |
192 | ||
193 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | |
194 | static int error_int_mask; | |
195 | ||
196 | static void bfin_generic_error_ack_irq(unsigned int irq) | |
197 | { | |
198 | ||
199 | } | |
200 | ||
201 | static void bfin_generic_error_mask_irq(unsigned int irq) | |
202 | { | |
203 | error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR)); | |
204 | ||
205 | if (!error_int_mask) { | |
206 | local_irq_disable(); | |
207 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & | |
2c4f829b | 208 | ~(1 << (IRQ_GENERIC_ERROR - |
1394f032 BW |
209 | (IRQ_CORETMR + 1)))); |
210 | SSYNC(); | |
211 | local_irq_enable(); | |
212 | } | |
213 | } | |
214 | ||
215 | static void bfin_generic_error_unmask_irq(unsigned int irq) | |
216 | { | |
217 | local_irq_disable(); | |
218 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 << | |
219 | (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1))); | |
220 | SSYNC(); | |
221 | local_irq_enable(); | |
222 | ||
223 | error_int_mask |= 1L << (irq - IRQ_PPI_ERROR); | |
224 | } | |
225 | ||
226 | static struct irq_chip bfin_generic_error_irqchip = { | |
227 | .ack = bfin_generic_error_ack_irq, | |
228 | .mask = bfin_generic_error_mask_irq, | |
229 | .unmask = bfin_generic_error_unmask_irq, | |
230 | }; | |
231 | ||
232 | static void bfin_demux_error_irq(unsigned int int_err_irq, | |
2c4f829b | 233 | struct irq_desc *inta_desc) |
1394f032 BW |
234 | { |
235 | int irq = 0; | |
236 | ||
237 | SSYNC(); | |
238 | ||
239 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) | |
240 | if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK) | |
241 | irq = IRQ_MAC_ERROR; | |
242 | else | |
243 | #endif | |
244 | if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK) | |
245 | irq = IRQ_SPORT0_ERROR; | |
246 | else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK) | |
247 | irq = IRQ_SPORT1_ERROR; | |
248 | else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK) | |
249 | irq = IRQ_PPI_ERROR; | |
250 | else if (bfin_read_CAN_GIF() & CAN_ERR_MASK) | |
251 | irq = IRQ_CAN_ERROR; | |
252 | else if (bfin_read_SPI_STAT() & SPI_ERR_MASK) | |
253 | irq = IRQ_SPI_ERROR; | |
254 | else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) && | |
255 | (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0)) | |
256 | irq = IRQ_UART0_ERROR; | |
257 | else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) && | |
258 | (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0)) | |
259 | irq = IRQ_UART1_ERROR; | |
260 | ||
261 | if (irq) { | |
262 | if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) { | |
263 | struct irq_desc *desc = irq_desc + irq; | |
264 | desc->handle_irq(irq, desc); | |
265 | } else { | |
266 | ||
267 | switch (irq) { | |
268 | case IRQ_PPI_ERROR: | |
269 | bfin_write_PPI_STATUS(PPI_ERR_MASK); | |
270 | break; | |
271 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) | |
272 | case IRQ_MAC_ERROR: | |
273 | bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK); | |
274 | break; | |
275 | #endif | |
276 | case IRQ_SPORT0_ERROR: | |
277 | bfin_write_SPORT0_STAT(SPORT_ERR_MASK); | |
278 | break; | |
279 | ||
280 | case IRQ_SPORT1_ERROR: | |
281 | bfin_write_SPORT1_STAT(SPORT_ERR_MASK); | |
282 | break; | |
283 | ||
284 | case IRQ_CAN_ERROR: | |
285 | bfin_write_CAN_GIS(CAN_ERR_MASK); | |
286 | break; | |
287 | ||
288 | case IRQ_SPI_ERROR: | |
289 | bfin_write_SPI_STAT(SPI_ERR_MASK); | |
290 | break; | |
291 | ||
292 | default: | |
293 | break; | |
294 | } | |
295 | ||
296 | pr_debug("IRQ %d:" | |
34e0fc89 MH |
297 | " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", |
298 | irq); | |
1394f032 BW |
299 | } |
300 | } else | |
301 | printk(KERN_ERR | |
302 | "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR" | |
303 | " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", | |
304 | __FUNCTION__, __FILE__, __LINE__); | |
305 | ||
1394f032 BW |
306 | } |
307 | #endif /* BF537_GENERIC_ERROR_INT_DEMUX */ | |
308 | ||
a055b2b4 | 309 | #if !defined(CONFIG_BF54x) |
1394f032 BW |
310 | |
311 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; | |
312 | static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; | |
313 | ||
6fce6a8d | 314 | |
1394f032 BW |
315 | static void bfin_gpio_ack_irq(unsigned int irq) |
316 | { | |
317 | u16 gpionr = irq - IRQ_PF0; | |
318 | ||
319 | if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { | |
320 | set_gpio_data(gpionr, 0); | |
321 | SSYNC(); | |
322 | } | |
323 | } | |
324 | ||
325 | static void bfin_gpio_mask_ack_irq(unsigned int irq) | |
326 | { | |
327 | u16 gpionr = irq - IRQ_PF0; | |
328 | ||
329 | if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { | |
330 | set_gpio_data(gpionr, 0); | |
331 | SSYNC(); | |
332 | } | |
333 | ||
334 | set_gpio_maska(gpionr, 0); | |
335 | SSYNC(); | |
336 | } | |
337 | ||
338 | static void bfin_gpio_mask_irq(unsigned int irq) | |
339 | { | |
340 | set_gpio_maska(irq - IRQ_PF0, 0); | |
341 | SSYNC(); | |
342 | } | |
343 | ||
344 | static void bfin_gpio_unmask_irq(unsigned int irq) | |
345 | { | |
346 | set_gpio_maska(irq - IRQ_PF0, 1); | |
347 | SSYNC(); | |
348 | } | |
349 | ||
350 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) | |
351 | { | |
352 | unsigned int ret; | |
353 | u16 gpionr = irq - IRQ_PF0; | |
6fce6a8d | 354 | char buf[8]; |
1394f032 BW |
355 | |
356 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { | |
6fce6a8d MH |
357 | snprintf(buf, sizeof buf, "IRQ %d", irq); |
358 | ret = gpio_request(gpionr, buf); | |
1394f032 BW |
359 | if (ret) |
360 | return ret; | |
361 | } | |
362 | ||
363 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); | |
364 | bfin_gpio_unmask_irq(irq); | |
365 | ||
366 | return ret; | |
367 | } | |
368 | ||
369 | static void bfin_gpio_irq_shutdown(unsigned int irq) | |
370 | { | |
371 | bfin_gpio_mask_irq(irq); | |
372 | gpio_free(irq - IRQ_PF0); | |
373 | gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0); | |
374 | } | |
375 | ||
376 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | |
377 | { | |
378 | ||
379 | unsigned int ret; | |
6fce6a8d | 380 | char buf[8]; |
1394f032 BW |
381 | u16 gpionr = irq - IRQ_PF0; |
382 | ||
383 | if (type == IRQ_TYPE_PROBE) { | |
384 | /* only probe unenabled GPIO interrupt lines */ | |
385 | if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)) | |
386 | return 0; | |
387 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
388 | } | |
389 | ||
390 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | |
34e0fc89 | 391 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
1394f032 | 392 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { |
6fce6a8d MH |
393 | snprintf(buf, sizeof buf, "IRQ %d", irq); |
394 | ret = gpio_request(gpionr, buf); | |
1394f032 BW |
395 | if (ret) |
396 | return ret; | |
397 | } | |
398 | ||
399 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); | |
400 | } else { | |
401 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); | |
402 | return 0; | |
403 | } | |
404 | ||
405 | set_gpio_dir(gpionr, 0); | |
406 | set_gpio_inen(gpionr, 1); | |
407 | ||
408 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | |
409 | gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr); | |
410 | set_gpio_edge(gpionr, 1); | |
411 | } else { | |
412 | set_gpio_edge(gpionr, 0); | |
413 | gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); | |
414 | } | |
415 | ||
416 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | |
417 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | |
418 | set_gpio_both(gpionr, 1); | |
419 | else | |
420 | set_gpio_both(gpionr, 0); | |
421 | ||
422 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) | |
423 | set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */ | |
424 | else | |
425 | set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */ | |
426 | ||
427 | SSYNC(); | |
428 | ||
429 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | |
430 | set_irq_handler(irq, handle_edge_irq); | |
431 | else | |
432 | set_irq_handler(irq, handle_level_irq); | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
1394f032 BW |
437 | static struct irq_chip bfin_gpio_irqchip = { |
438 | .ack = bfin_gpio_ack_irq, | |
439 | .mask = bfin_gpio_mask_irq, | |
440 | .mask_ack = bfin_gpio_mask_ack_irq, | |
441 | .unmask = bfin_gpio_unmask_irq, | |
442 | .set_type = bfin_gpio_irq_type, | |
443 | .startup = bfin_gpio_irq_startup, | |
444 | .shutdown = bfin_gpio_irq_shutdown | |
445 | }; | |
446 | ||
2c4f829b MH |
447 | static void bfin_demux_gpio_irq(unsigned int inta_irq, |
448 | struct irq_desc *desc) | |
1394f032 | 449 | { |
2c4f829b MH |
450 | unsigned int i, gpio, mask, irq, search = 0; |
451 | ||
452 | switch (inta_irq) { | |
453 | #if defined(CONFIG_BF53x) | |
454 | case IRQ_PROG_INTA: | |
455 | irq = IRQ_PF0; | |
456 | search = 1; | |
457 | break; | |
458 | # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) | |
459 | case IRQ_MAC_RX: | |
460 | irq = IRQ_PH0; | |
461 | break; | |
462 | # endif | |
463 | #elif defined(CONFIG_BF52x) | |
464 | case IRQ_PORTF_INTA: | |
465 | irq = IRQ_PF0; | |
466 | break; | |
467 | case IRQ_PORTG_INTA: | |
468 | irq = IRQ_PG0; | |
469 | break; | |
470 | case IRQ_PORTH_INTA: | |
471 | irq = IRQ_PH0; | |
472 | break; | |
473 | #elif defined(CONFIG_BF561) | |
474 | case IRQ_PROG0_INTA: | |
475 | irq = IRQ_PF0; | |
476 | break; | |
477 | case IRQ_PROG1_INTA: | |
478 | irq = IRQ_PF16; | |
479 | break; | |
480 | case IRQ_PROG2_INTA: | |
481 | irq = IRQ_PF32; | |
482 | break; | |
483 | #endif | |
484 | default: | |
485 | BUG(); | |
486 | return; | |
487 | } | |
488 | ||
489 | if (search) { | |
490 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) { | |
491 | irq += i; | |
492 | ||
493 | mask = get_gpiop_data(i) & | |
494 | (gpio_enabled[gpio_bank(i)] & | |
495 | get_gpiop_maska(i)); | |
496 | ||
497 | while (mask) { | |
498 | if (mask & 1) { | |
499 | desc = irq_desc + irq; | |
500 | desc->handle_irq(irq, desc); | |
501 | } | |
502 | irq++; | |
503 | mask >>= 1; | |
1394f032 | 504 | } |
1394f032 | 505 | } |
2c4f829b MH |
506 | } else { |
507 | gpio = irq_to_gpio(irq); | |
508 | mask = get_gpiop_data(gpio) & | |
509 | (gpio_enabled[gpio_bank(gpio)] & | |
510 | get_gpiop_maska(gpio)); | |
511 | ||
512 | do { | |
513 | if (mask & 1) { | |
514 | desc = irq_desc + irq; | |
515 | desc->handle_irq(irq, desc); | |
516 | } | |
517 | irq++; | |
518 | mask >>= 1; | |
519 | } while (mask); | |
1394f032 | 520 | } |
2c4f829b | 521 | |
1394f032 BW |
522 | } |
523 | ||
a055b2b4 | 524 | #else /* CONFIG_BF54x */ |
34e0fc89 MH |
525 | |
526 | #define NR_PINT_SYS_IRQS 4 | |
527 | #define NR_PINT_BITS 32 | |
528 | #define NR_PINTS 160 | |
529 | #define IRQ_NOT_AVAIL 0xFF | |
530 | ||
531 | #define PINT_2_BANK(x) ((x) >> 5) | |
532 | #define PINT_2_BIT(x) ((x) & 0x1F) | |
533 | #define PINT_BIT(x) (1 << (PINT_2_BIT(x))) | |
534 | ||
535 | static unsigned char irq2pint_lut[NR_PINTS]; | |
e3f23000 | 536 | static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; |
34e0fc89 | 537 | |
8baf560b MH |
538 | static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS]; |
539 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; | |
540 | ||
541 | ||
34e0fc89 MH |
542 | struct pin_int_t { |
543 | unsigned int mask_set; | |
544 | unsigned int mask_clear; | |
545 | unsigned int request; | |
546 | unsigned int assign; | |
547 | unsigned int edge_set; | |
548 | unsigned int edge_clear; | |
549 | unsigned int invert_set; | |
550 | unsigned int invert_clear; | |
551 | unsigned int pinstate; | |
552 | unsigned int latch; | |
553 | }; | |
554 | ||
555 | static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = { | |
556 | (struct pin_int_t *)PINT0_MASK_SET, | |
557 | (struct pin_int_t *)PINT1_MASK_SET, | |
558 | (struct pin_int_t *)PINT2_MASK_SET, | |
559 | (struct pin_int_t *)PINT3_MASK_SET, | |
560 | }; | |
561 | ||
562 | unsigned short get_irq_base(u8 bank, u8 bmap) | |
563 | { | |
564 | ||
565 | u16 irq_base; | |
566 | ||
567 | if (bank < 2) { /*PA-PB */ | |
568 | irq_base = IRQ_PA0 + bmap * 16; | |
569 | } else { /*PC-PJ */ | |
570 | irq_base = IRQ_PC0 + bmap * 16; | |
571 | } | |
572 | ||
573 | return irq_base; | |
574 | ||
575 | } | |
576 | ||
577 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ | |
578 | void init_pint_lut(void) | |
579 | { | |
580 | u16 bank, bit, irq_base, bit_pos; | |
581 | u32 pint_assign; | |
582 | u8 bmap; | |
583 | ||
584 | memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut)); | |
585 | ||
586 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { | |
587 | ||
588 | pint_assign = pint[bank]->assign; | |
589 | ||
590 | for (bit = 0; bit < NR_PINT_BITS; bit++) { | |
591 | ||
592 | bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF; | |
593 | ||
594 | irq_base = get_irq_base(bank, bmap); | |
595 | ||
596 | irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0); | |
597 | bit_pos = bit + bank * NR_PINT_BITS; | |
598 | ||
e3f23000 | 599 | pint2irq_lut[bit_pos] = irq_base - SYS_IRQS; |
34e0fc89 MH |
600 | irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; |
601 | ||
602 | } | |
603 | ||
604 | } | |
605 | ||
606 | } | |
607 | ||
34e0fc89 MH |
608 | static void bfin_gpio_ack_irq(unsigned int irq) |
609 | { | |
610 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
8baf560b MH |
611 | u32 pintbit = PINT_BIT(pint_val); |
612 | u8 bank = PINT_2_BANK(pint_val); | |
613 | ||
614 | if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) { | |
615 | if (pint[bank]->invert_set & pintbit) | |
616 | pint[bank]->invert_clear = pintbit; | |
617 | else | |
618 | pint[bank]->invert_set = pintbit; | |
619 | } | |
620 | pint[bank]->request = pintbit; | |
34e0fc89 | 621 | |
34e0fc89 MH |
622 | SSYNC(); |
623 | } | |
624 | ||
625 | static void bfin_gpio_mask_ack_irq(unsigned int irq) | |
626 | { | |
627 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
e3f23000 MH |
628 | u32 pintbit = PINT_BIT(pint_val); |
629 | u8 bank = PINT_2_BANK(pint_val); | |
34e0fc89 | 630 | |
8baf560b MH |
631 | if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) { |
632 | if (pint[bank]->invert_set & pintbit) | |
633 | pint[bank]->invert_clear = pintbit; | |
634 | else | |
635 | pint[bank]->invert_set = pintbit; | |
636 | } | |
637 | ||
e3f23000 MH |
638 | pint[bank]->request = pintbit; |
639 | pint[bank]->mask_clear = pintbit; | |
34e0fc89 MH |
640 | SSYNC(); |
641 | } | |
642 | ||
643 | static void bfin_gpio_mask_irq(unsigned int irq) | |
644 | { | |
645 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
646 | ||
647 | pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); | |
648 | SSYNC(); | |
649 | } | |
650 | ||
651 | static void bfin_gpio_unmask_irq(unsigned int irq) | |
652 | { | |
653 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; | |
e3f23000 MH |
654 | u32 pintbit = PINT_BIT(pint_val); |
655 | u8 bank = PINT_2_BANK(pint_val); | |
34e0fc89 | 656 | |
e3f23000 MH |
657 | pint[bank]->request = pintbit; |
658 | pint[bank]->mask_set = pintbit; | |
34e0fc89 MH |
659 | SSYNC(); |
660 | } | |
661 | ||
662 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) | |
663 | { | |
664 | unsigned int ret; | |
6fce6a8d | 665 | char buf[8]; |
8baf560b | 666 | u16 gpionr = irq_to_gpio(irq); |
34e0fc89 MH |
667 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
668 | ||
50e163ce MH |
669 | if (pint_val == IRQ_NOT_AVAIL) { |
670 | printk(KERN_ERR | |
671 | "GPIO IRQ %d :Not in PINT Assign table " | |
672 | "Reconfigure Interrupt to Port Assignemt\n", irq); | |
34e0fc89 | 673 | return -ENODEV; |
50e163ce | 674 | } |
34e0fc89 MH |
675 | |
676 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { | |
6fce6a8d MH |
677 | snprintf(buf, sizeof buf, "IRQ %d", irq); |
678 | ret = gpio_request(gpionr, buf); | |
34e0fc89 MH |
679 | if (ret) |
680 | return ret; | |
681 | } | |
682 | ||
683 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); | |
684 | bfin_gpio_unmask_irq(irq); | |
685 | ||
686 | return ret; | |
687 | } | |
688 | ||
689 | static void bfin_gpio_irq_shutdown(unsigned int irq) | |
690 | { | |
8baf560b MH |
691 | u16 gpionr = irq_to_gpio(irq); |
692 | ||
34e0fc89 | 693 | bfin_gpio_mask_irq(irq); |
8baf560b MH |
694 | gpio_free(gpionr); |
695 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); | |
34e0fc89 MH |
696 | } |
697 | ||
698 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) | |
699 | { | |
700 | ||
701 | unsigned int ret; | |
6fce6a8d | 702 | char buf[8]; |
8baf560b | 703 | u16 gpionr = irq_to_gpio(irq); |
34e0fc89 | 704 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
e3f23000 MH |
705 | u32 pintbit = PINT_BIT(pint_val); |
706 | u8 bank = PINT_2_BANK(pint_val); | |
34e0fc89 MH |
707 | |
708 | if (pint_val == IRQ_NOT_AVAIL) | |
709 | return -ENODEV; | |
710 | ||
711 | if (type == IRQ_TYPE_PROBE) { | |
712 | /* only probe unenabled GPIO interrupt lines */ | |
713 | if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)) | |
714 | return 0; | |
715 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
716 | } | |
717 | ||
718 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | |
719 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { | |
720 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { | |
6fce6a8d MH |
721 | snprintf(buf, sizeof buf, "IRQ %d", irq); |
722 | ret = gpio_request(gpionr, buf); | |
34e0fc89 MH |
723 | if (ret) |
724 | return ret; | |
725 | } | |
726 | ||
727 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); | |
728 | } else { | |
729 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); | |
730 | return 0; | |
731 | } | |
732 | ||
733 | gpio_direction_input(gpionr); | |
734 | ||
34e0fc89 | 735 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) |
e3f23000 | 736 | pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ |
34e0fc89 | 737 | else |
8baf560b | 738 | pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */ |
34e0fc89 | 739 | |
8baf560b MH |
740 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
741 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | |
34e0fc89 | 742 | |
8baf560b | 743 | gpio_both_edge_triggered[bank] |= pintbit; |
34e0fc89 | 744 | |
8baf560b MH |
745 | if (gpio_get_value(gpionr)) |
746 | pint[bank]->invert_set = pintbit; | |
747 | else | |
748 | pint[bank]->invert_clear = pintbit; | |
749 | } else { | |
750 | gpio_both_edge_triggered[bank] &= ~pintbit; | |
751 | } | |
752 | ||
753 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | |
754 | pint[bank]->edge_set = pintbit; | |
34e0fc89 | 755 | set_irq_handler(irq, handle_edge_irq); |
8baf560b MH |
756 | } else { |
757 | pint[bank]->edge_clear = pintbit; | |
34e0fc89 | 758 | set_irq_handler(irq, handle_level_irq); |
8baf560b MH |
759 | } |
760 | ||
761 | SSYNC(); | |
34e0fc89 MH |
762 | |
763 | return 0; | |
764 | } | |
765 | ||
766 | static struct irq_chip bfin_gpio_irqchip = { | |
767 | .ack = bfin_gpio_ack_irq, | |
768 | .mask = bfin_gpio_mask_irq, | |
769 | .mask_ack = bfin_gpio_mask_ack_irq, | |
770 | .unmask = bfin_gpio_unmask_irq, | |
771 | .set_type = bfin_gpio_irq_type, | |
772 | .startup = bfin_gpio_irq_startup, | |
773 | .shutdown = bfin_gpio_irq_shutdown | |
774 | }; | |
775 | ||
2c4f829b MH |
776 | static void bfin_demux_gpio_irq(unsigned int inta_irq, |
777 | struct irq_desc *desc) | |
34e0fc89 MH |
778 | { |
779 | u8 bank, pint_val; | |
780 | u32 request, irq; | |
781 | ||
2c4f829b | 782 | switch (inta_irq) { |
34e0fc89 MH |
783 | case IRQ_PINT0: |
784 | bank = 0; | |
785 | break; | |
786 | case IRQ_PINT2: | |
787 | bank = 2; | |
788 | break; | |
789 | case IRQ_PINT3: | |
790 | bank = 3; | |
791 | break; | |
792 | case IRQ_PINT1: | |
793 | bank = 1; | |
794 | break; | |
e3f23000 MH |
795 | default: |
796 | return; | |
34e0fc89 MH |
797 | } |
798 | ||
799 | pint_val = bank * NR_PINT_BITS; | |
800 | ||
801 | request = pint[bank]->request; | |
802 | ||
803 | while (request) { | |
804 | if (request & 1) { | |
e3f23000 MH |
805 | irq = pint2irq_lut[pint_val] + SYS_IRQS; |
806 | desc = irq_desc + irq; | |
34e0fc89 MH |
807 | desc->handle_irq(irq, desc); |
808 | } | |
809 | pint_val++; | |
810 | request >>= 1; | |
811 | } | |
812 | ||
813 | } | |
a055b2b4 | 814 | #endif |
1394f032 | 815 | |
8be80ed3 BS |
816 | void __init init_exception_vectors(void) |
817 | { | |
818 | SSYNC(); | |
819 | ||
f0b5d12f MF |
820 | /* cannot program in software: |
821 | * evt0 - emulation (jtag) | |
822 | * evt1 - reset | |
823 | */ | |
824 | bfin_write_EVT2(evt_nmi); | |
8be80ed3 BS |
825 | bfin_write_EVT3(trap); |
826 | bfin_write_EVT5(evt_ivhw); | |
827 | bfin_write_EVT6(evt_timer); | |
828 | bfin_write_EVT7(evt_evt7); | |
829 | bfin_write_EVT8(evt_evt8); | |
830 | bfin_write_EVT9(evt_evt9); | |
831 | bfin_write_EVT10(evt_evt10); | |
832 | bfin_write_EVT11(evt_evt11); | |
833 | bfin_write_EVT12(evt_evt12); | |
834 | bfin_write_EVT13(evt_evt13); | |
835 | bfin_write_EVT14(evt14_softirq); | |
836 | bfin_write_EVT15(evt_system_call); | |
837 | CSYNC(); | |
838 | } | |
839 | ||
1394f032 BW |
840 | /* |
841 | * This function should be called during kernel startup to initialize | |
842 | * the BFin IRQ handling routines. | |
843 | */ | |
844 | int __init init_arch_irq(void) | |
845 | { | |
846 | int irq; | |
847 | unsigned long ilat = 0; | |
848 | /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ | |
2c4f829b | 849 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) |
24a07a12 RH |
850 | bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); |
851 | bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); | |
1c5d2265 MH |
852 | bfin_write_SIC_IWR0(IWR_ENABLE_ALL); |
853 | bfin_write_SIC_IWR1(IWR_ENABLE_ALL); | |
a055b2b4 | 854 | # ifdef CONFIG_BF54x |
59003145 | 855 | bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); |
c04d66bb | 856 | bfin_write_SIC_IWR2(IWR_ENABLE_ALL); |
a055b2b4 | 857 | # endif |
24a07a12 | 858 | #else |
1394f032 | 859 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); |
1c5d2265 | 860 | bfin_write_SIC_IWR(IWR_ENABLE_ALL); |
24a07a12 | 861 | #endif |
1394f032 BW |
862 | SSYNC(); |
863 | ||
864 | local_irq_disable(); | |
865 | ||
2c4f829b MH |
866 | init_exception_buff(); |
867 | ||
a055b2b4 MF |
868 | #ifdef CONFIG_BF54x |
869 | # ifdef CONFIG_PINTx_REASSIGN | |
34e0fc89 MH |
870 | pint[0]->assign = CONFIG_PINT0_ASSIGN; |
871 | pint[1]->assign = CONFIG_PINT1_ASSIGN; | |
872 | pint[2]->assign = CONFIG_PINT2_ASSIGN; | |
873 | pint[3]->assign = CONFIG_PINT3_ASSIGN; | |
a055b2b4 | 874 | # endif |
34e0fc89 MH |
875 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
876 | init_pint_lut(); | |
877 | #endif | |
878 | ||
879 | for (irq = 0; irq <= SYS_IRQS; irq++) { | |
1394f032 BW |
880 | if (irq <= IRQ_CORETMR) |
881 | set_irq_chip(irq, &bfin_core_irqchip); | |
882 | else | |
883 | set_irq_chip(irq, &bfin_internal_irqchip); | |
884 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | |
885 | if (irq != IRQ_GENERIC_ERROR) { | |
886 | #endif | |
887 | ||
34e0fc89 | 888 | switch (irq) { |
59003145 | 889 | #if defined(CONFIG_BF53x) |
34e0fc89 MH |
890 | case IRQ_PROG_INTA: |
891 | set_irq_chained_handler(irq, | |
892 | bfin_demux_gpio_irq); | |
893 | break; | |
a055b2b4 | 894 | # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) |
34e0fc89 MH |
895 | case IRQ_MAC_RX: |
896 | set_irq_chained_handler(irq, | |
897 | bfin_demux_gpio_irq); | |
898 | break; | |
a055b2b4 | 899 | # endif |
59003145 | 900 | #elif defined(CONFIG_BF54x) |
34e0fc89 | 901 | case IRQ_PINT0: |
1394f032 BW |
902 | set_irq_chained_handler(irq, |
903 | bfin_demux_gpio_irq); | |
34e0fc89 MH |
904 | break; |
905 | case IRQ_PINT1: | |
906 | set_irq_chained_handler(irq, | |
907 | bfin_demux_gpio_irq); | |
908 | break; | |
909 | case IRQ_PINT2: | |
910 | set_irq_chained_handler(irq, | |
911 | bfin_demux_gpio_irq); | |
912 | break; | |
913 | case IRQ_PINT3: | |
914 | set_irq_chained_handler(irq, | |
915 | bfin_demux_gpio_irq); | |
916 | break; | |
59003145 MH |
917 | #elif defined(CONFIG_BF52x) |
918 | case IRQ_PORTF_INTA: | |
919 | set_irq_chained_handler(irq, | |
920 | bfin_demux_gpio_irq); | |
921 | break; | |
922 | case IRQ_PORTG_INTA: | |
923 | set_irq_chained_handler(irq, | |
924 | bfin_demux_gpio_irq); | |
925 | break; | |
926 | case IRQ_PORTH_INTA: | |
927 | set_irq_chained_handler(irq, | |
928 | bfin_demux_gpio_irq); | |
929 | break; | |
2c4f829b MH |
930 | #elif defined(CONFIG_BF561) |
931 | case IRQ_PROG0_INTA: | |
932 | set_irq_chained_handler(irq, | |
933 | bfin_demux_gpio_irq); | |
934 | break; | |
935 | case IRQ_PROG1_INTA: | |
936 | set_irq_chained_handler(irq, | |
937 | bfin_demux_gpio_irq); | |
938 | break; | |
939 | case IRQ_PROG2_INTA: | |
940 | set_irq_chained_handler(irq, | |
941 | bfin_demux_gpio_irq); | |
942 | break; | |
1394f032 | 943 | #endif |
34e0fc89 MH |
944 | default: |
945 | set_irq_handler(irq, handle_simple_irq); | |
946 | break; | |
947 | } | |
1394f032 BW |
948 | |
949 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | |
950 | } else { | |
951 | set_irq_handler(irq, bfin_demux_error_irq); | |
952 | } | |
953 | #endif | |
954 | } | |
955 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | |
956 | for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) { | |
957 | set_irq_chip(irq, &bfin_generic_error_irqchip); | |
958 | set_irq_handler(irq, handle_level_irq); | |
959 | } | |
960 | #endif | |
961 | ||
2c4f829b MH |
962 | for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) { |
963 | ||
1394f032 BW |
964 | set_irq_chip(irq, &bfin_gpio_irqchip); |
965 | /* if configured as edge, then will be changed to do_edge_IRQ */ | |
966 | set_irq_handler(irq, handle_level_irq); | |
967 | } | |
a055b2b4 | 968 | |
1394f032 BW |
969 | bfin_write_IMASK(0); |
970 | CSYNC(); | |
971 | ilat = bfin_read_ILAT(); | |
972 | CSYNC(); | |
973 | bfin_write_ILAT(ilat); | |
974 | CSYNC(); | |
975 | ||
34e0fc89 | 976 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); |
1394f032 BW |
977 | /* IMASK=xxx is equivalent to STI xx or irq_flags=xx, |
978 | * local_irq_enable() | |
979 | */ | |
980 | program_IAR(); | |
981 | /* Therefore it's better to setup IARs before interrupts enabled */ | |
982 | search_IAR(); | |
983 | ||
984 | /* Enable interrupts IVG7-15 */ | |
985 | irq_flags = irq_flags | IMASK_IVG15 | | |
986 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | | |
34e0fc89 | 987 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
1394f032 BW |
988 | |
989 | return 0; | |
990 | } | |
991 | ||
992 | #ifdef CONFIG_DO_IRQ_L1 | |
a055b2b4 | 993 | __attribute__((l1_text)) |
1394f032 | 994 | #endif |
1394f032 BW |
995 | void do_irq(int vec, struct pt_regs *fp) |
996 | { | |
997 | if (vec == EVT_IVTMR_P) { | |
998 | vec = IRQ_CORETMR; | |
999 | } else { | |
1000 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; | |
1001 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; | |
2c4f829b | 1002 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) |
24a07a12 | 1003 | unsigned long sic_status[3]; |
1394f032 | 1004 | |
24a07a12 | 1005 | SSYNC(); |
4fb45241 MH |
1006 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); |
1007 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); | |
59003145 | 1008 | #ifdef CONFIG_BF54x |
4fb45241 | 1009 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); |
59003145 | 1010 | #endif |
1f83b8f1 | 1011 | for (;; ivg++) { |
24a07a12 RH |
1012 | if (ivg >= ivg_stop) { |
1013 | atomic_inc(&num_spurious); | |
1014 | return; | |
1015 | } | |
34e0fc89 | 1016 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) |
24a07a12 RH |
1017 | break; |
1018 | } | |
1019 | #else | |
1020 | unsigned long sic_status; | |
1394f032 BW |
1021 | SSYNC(); |
1022 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); | |
1023 | ||
1024 | for (;; ivg++) { | |
1025 | if (ivg >= ivg_stop) { | |
1026 | atomic_inc(&num_spurious); | |
1027 | return; | |
1028 | } else if (sic_status & ivg->isrflag) | |
1029 | break; | |
1030 | } | |
24a07a12 | 1031 | #endif |
1394f032 BW |
1032 | vec = ivg->irqno; |
1033 | } | |
1034 | asm_do_IRQ(vec, fp); | |
1035 | ||
1036 | #ifdef CONFIG_KGDB | |
1037 | kgdb_process_breakpoint(); | |
1038 | #endif | |
1039 | } |