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Blackfin arch: add CONFIG_APP_STACKS_L1 to enable or disable putting kernel stacks...
[deliverable/linux.git] / arch / blackfin / mach-common / ints-priority.c
CommitLineData
1394f032 1/*
cfefe3c6 2 * File: arch/blackfin/mach-common/ints-priority.c
1394f032
BW		 3 * Based on:
4 * Author:
5 *
6 * Created: ?
d2d50aa9 7 * Description: Set up the interrupt priorities
1394f032
BW		 8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
cfefe3c6 16 * Copyright 2004-2008 Analog Devices Inc.
1394f032
BW		 17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36#include <linux/module.h>
37#include <linux/kernel_stat.h>
38#include <linux/seq_file.h>
39#include <linux/irq.h>
40#ifdef CONFIG_KGDB
41#include <linux/kgdb.h>
42#endif
43#include <asm/traps.h>
44#include <asm/blackfin.h>
45#include <asm/gpio.h>
46#include <asm/irq_handler.h>
47
48#ifdef BF537_FAMILY
49# define BF537_GENERIC_ERROR_INT_DEMUX
50#else
51# undef BF537_GENERIC_ERROR_INT_DEMUX
52#endif
53
54/*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
a99bbccd
MF		 61/* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
66 */
67unsigned long irq_flags = 0x1f;
1394f032
BW		 68
69/* The number of spurious interrupts */
70atomic_t num_spurious;
71
cfefe3c6
MH		 72#ifdef CONFIG_PM
73unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
4a88d0ce 74unsigned vr_wakeup;
cfefe3c6
MH		 75#endif
76
1394f032 77struct ivgx {
464abc5d 78 /* irq number for request_irq, available in mach-bf5xx/irq.h */
24a07a12 79 unsigned int irqno;
1394f032 80 /* corresponding bit in the SIC_ISR register */
24a07a12 81 unsigned int isrflag;
1394f032
BW		 82} ivg_table[NR_PERI_INTS];
83
84struct ivg_slice {
85 /* position of first irq in ivg_table for given ivg */
86 struct ivgx *ifirst;
87 struct ivgx *istop;
88} ivg7_13[IVG13 - IVG7 + 1];
89
1394f032
BW		 90
91/*
92 * Search SIC_IAR and fill tables with the irqvalues
93 * and their positions in the SIC_ISR register.
94 */
95static void __init search_IAR(void)
96{
97 unsigned ivg, irq_pos = 0;
98 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
99 int irqn;
100
34e0fc89 101 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
1394f032
BW		 102
103 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
104 int iar_shift = (irqn & 7) * 4;
2c4f829b 105 if (ivg == (0xf &
59003145 106#ifndef CONFIG_BF52x
34e0fc89 107 bfin_read32((unsigned long *)SIC_IAR0 +
1394f032 108 (irqn >> 3)) >> iar_shift)) {
59003145
MH		 109#else
110 bfin_read32((unsigned long *)SIC_IAR0 +
111 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
112#endif
1394f032 113 ivg_table[irq_pos].irqno = IVG7 + irqn;
24a07a12 114 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
1394f032
BW		 115 ivg7_13[ivg].istop++;
116 irq_pos++;
117 }
118 }
119 }
120}
121
122/*
464abc5d 123 * This is for core internal IRQs
1394f032
BW		 124 */
125
464abc5d 126static void bfin_ack_noop(unsigned int irq)
1394f032
BW		 127{
128 /* Dummy function. */
129}
130
131static void bfin_core_mask_irq(unsigned int irq)
132{
133 irq_flags &= ~(1 << irq);
134 if (!irqs_disabled())
135 local_irq_enable();
136}
137
138static void bfin_core_unmask_irq(unsigned int irq)
139{
140 irq_flags |= 1 << irq;
141 /*
142 * If interrupts are enabled, IMASK must contain the same value
143 * as irq_flags. Make sure that invariant holds. If interrupts
144 * are currently disabled we need not do anything; one of the
145 * callers will take care of setting IMASK to the proper value
146 * when reenabling interrupts.
147 * local_irq_enable just does "STI irq_flags", so it's exactly
148 * what we need.
149 */
150 if (!irqs_disabled())
151 local_irq_enable();
152 return;
153}
154
155static void bfin_internal_mask_irq(unsigned int irq)
156{
59003145 157#ifdef CONFIG_BF53x
1394f032 158 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
464abc5d 159 ~(1 << SIC_SYSIRQ(irq)));
24a07a12
RH		 160#else
161 unsigned mask_bank, mask_bit;
464abc5d
MH		 162 mask_bank = SIC_SYSIRQ(irq) / 32;
163 mask_bit = SIC_SYSIRQ(irq) % 32;
c04d66bb
BW		 164 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
165 ~(1 << mask_bit));
24a07a12 166#endif
1394f032
BW		 167 SSYNC();
168}
169
170static void bfin_internal_unmask_irq(unsigned int irq)
171{
59003145 172#ifdef CONFIG_BF53x
1394f032 173 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
464abc5d 174 (1 << SIC_SYSIRQ(irq)));
24a07a12
RH		 175#else
176 unsigned mask_bank, mask_bit;
464abc5d
MH		 177 mask_bank = SIC_SYSIRQ(irq) / 32;
178 mask_bit = SIC_SYSIRQ(irq) % 32;
c04d66bb
BW		 179 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
180 (1 << mask_bit));
24a07a12 181#endif
1394f032
BW		 182 SSYNC();
183}
184
cfefe3c6
MH		 185#ifdef CONFIG_PM
186int bfin_internal_set_wake(unsigned int irq, unsigned int state)
187{
4a88d0ce 188 unsigned bank, bit, wakeup = 0;
cfefe3c6 189 unsigned long flags;
464abc5d
MH		 190 bank = SIC_SYSIRQ(irq) / 32;
191 bit = SIC_SYSIRQ(irq) % 32;
cfefe3c6 192
4a88d0ce
MH		 193 switch (irq) {
194#ifdef IRQ_RTC
195 case IRQ_RTC:
196 wakeup |= WAKE;
197 break;
198#endif
199#ifdef IRQ_CAN0_RX
200 case IRQ_CAN0_RX:
201 wakeup |= CANWE;
202 break;
203#endif
204#ifdef IRQ_CAN1_RX
205 case IRQ_CAN1_RX:
206 wakeup |= CANWE;
207 break;
208#endif
209#ifdef IRQ_USB_INT0
210 case IRQ_USB_INT0:
211 wakeup |= USBWE;
212 break;
213#endif
214#ifdef IRQ_KEY
215 case IRQ_KEY:
216 wakeup |= KPADWE;
217 break;
218#endif
d310fb4b 219#ifdef CONFIG_BF54x
4a88d0ce
MH		 220 case IRQ_CNT:
221 wakeup |= ROTWE;
222 break;
223#endif
224 default:
225 break;
226 }
227
cfefe3c6
MH		 228 local_irq_save(flags);
229
4a88d0ce 230 if (state) {
cfefe3c6 231 bfin_sic_iwr[bank] |= (1 << bit);
4a88d0ce
MH		 232 vr_wakeup |= wakeup;
233
234 } else {
cfefe3c6 235 bfin_sic_iwr[bank] &= ~(1 << bit);
4a88d0ce
MH		 236 vr_wakeup &= ~wakeup;
237 }
cfefe3c6
MH		 238
239 local_irq_restore(flags);
240
241 return 0;
242}
243#endif
244
1394f032 245static struct irq_chip bfin_core_irqchip = {
464abc5d 246 .ack = bfin_ack_noop,
1394f032
BW		 247 .mask = bfin_core_mask_irq,
248 .unmask = bfin_core_unmask_irq,
249};
250
251static struct irq_chip bfin_internal_irqchip = {
464abc5d 252 .ack = bfin_ack_noop,
1394f032
BW		 253 .mask = bfin_internal_mask_irq,
254 .unmask = bfin_internal_unmask_irq,
ce3b7bb6
MH		 255 .mask_ack = bfin_internal_mask_irq,
256 .disable = bfin_internal_mask_irq,
257 .enable = bfin_internal_unmask_irq,
cfefe3c6
MH		 258#ifdef CONFIG_PM
259 .set_wake = bfin_internal_set_wake,
260#endif
1394f032
BW		 261};
262
263#ifdef BF537_GENERIC_ERROR_INT_DEMUX
264static int error_int_mask;
265
1394f032
BW		 266static void bfin_generic_error_mask_irq(unsigned int irq)
267{
268 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
269
464abc5d
MH		 270 if (!error_int_mask)
271 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
1394f032
BW		 272}
273
274static void bfin_generic_error_unmask_irq(unsigned int irq)
275{
464abc5d 276 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
1394f032
BW		 277 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
278}
279
280static struct irq_chip bfin_generic_error_irqchip = {
464abc5d
MH		 281 .ack = bfin_ack_noop,
282 .mask_ack = bfin_generic_error_mask_irq,
1394f032
BW		 283 .mask = bfin_generic_error_mask_irq,
284 .unmask = bfin_generic_error_unmask_irq,
285};
286
287static void bfin_demux_error_irq(unsigned int int_err_irq,
2c4f829b 288 struct irq_desc *inta_desc)
1394f032
BW		 289{
290 int irq = 0;
291
292 SSYNC();
293
294#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
295 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
296 irq = IRQ_MAC_ERROR;
297 else
298#endif
299 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
300 irq = IRQ_SPORT0_ERROR;
301 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
302 irq = IRQ_SPORT1_ERROR;
303 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
304 irq = IRQ_PPI_ERROR;
305 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
306 irq = IRQ_CAN_ERROR;
307 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
308 irq = IRQ_SPI_ERROR;
309 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
310 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
311 irq = IRQ_UART0_ERROR;
312 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
313 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
314 irq = IRQ_UART1_ERROR;
315
316 if (irq) {
317 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
318 struct irq_desc *desc = irq_desc + irq;
319 desc->handle_irq(irq, desc);
320 } else {
321
322 switch (irq) {
323 case IRQ_PPI_ERROR:
324 bfin_write_PPI_STATUS(PPI_ERR_MASK);
325 break;
326#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
327 case IRQ_MAC_ERROR:
328 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
329 break;
330#endif
331 case IRQ_SPORT0_ERROR:
332 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
333 break;
334
335 case IRQ_SPORT1_ERROR:
336 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
337 break;
338
339 case IRQ_CAN_ERROR:
340 bfin_write_CAN_GIS(CAN_ERR_MASK);
341 break;
342
343 case IRQ_SPI_ERROR:
344 bfin_write_SPI_STAT(SPI_ERR_MASK);
345 break;
346
347 default:
348 break;
349 }
350
351 pr_debug("IRQ %d:"
34e0fc89
MH		 352 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
353 irq);
1394f032
BW		 354 }
355 } else
356 printk(KERN_ERR
357 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
358 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
b85d858b 359 __func__, __FILE__, __LINE__);
1394f032 360
1394f032
BW		 361}
362#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
363
a055b2b4 364#if !defined(CONFIG_BF54x)
1394f032
BW		 365
366static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
367static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
368
affee2b2 369extern void bfin_gpio_irq_prepare(unsigned gpio);
6fce6a8d 370
1394f032
BW		 371static void bfin_gpio_ack_irq(unsigned int irq)
372{
373 u16 gpionr = irq - IRQ_PF0;
374
375 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
376 set_gpio_data(gpionr, 0);
377 SSYNC();
378 }
379}
380
381static void bfin_gpio_mask_ack_irq(unsigned int irq)
382{
383 u16 gpionr = irq - IRQ_PF0;
384
385 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
386 set_gpio_data(gpionr, 0);
387 SSYNC();
388 }
389
390 set_gpio_maska(gpionr, 0);
391 SSYNC();
392}
393
394static void bfin_gpio_mask_irq(unsigned int irq)
395{
396 set_gpio_maska(irq - IRQ_PF0, 0);
397 SSYNC();
398}
399
400static void bfin_gpio_unmask_irq(unsigned int irq)
401{
402 set_gpio_maska(irq - IRQ_PF0, 1);
403 SSYNC();
404}
405
406static unsigned int bfin_gpio_irq_startup(unsigned int irq)
407{
1394f032
BW		 408 u16 gpionr = irq - IRQ_PF0;
409
affee2b2
MH		 410 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
411 bfin_gpio_irq_prepare(gpionr);
1394f032
BW		 412
413 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
414 bfin_gpio_unmask_irq(irq);
415
affee2b2 416 return 0;
1394f032
BW		 417}
418
419static void bfin_gpio_irq_shutdown(unsigned int irq)
420{
421 bfin_gpio_mask_irq(irq);
1394f032
BW		 422 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
423}
424
425static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
426{
1394f032
BW		 427 u16 gpionr = irq - IRQ_PF0;
428
429 if (type == IRQ_TYPE_PROBE) {
430 /* only probe unenabled GPIO interrupt lines */
431 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
432 return 0;
433 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
434 }
435
436 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
34e0fc89 437 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
affee2b2
MH		 438 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
439 bfin_gpio_irq_prepare(gpionr);
1394f032
BW		 440
441 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
442 } else {
443 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
444 return 0;
445 }
446
f1bceb47 447 set_gpio_inen(gpionr, 0);
1394f032 448 set_gpio_dir(gpionr, 0);
1394f032
BW		 449
450 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
451 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
452 set_gpio_both(gpionr, 1);
453 else
454 set_gpio_both(gpionr, 0);
455
456 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
457 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
458 else
459 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
460
f1bceb47
MH		 461 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
462 set_gpio_edge(gpionr, 1);
463 set_gpio_inen(gpionr, 1);
464 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
465 set_gpio_data(gpionr, 0);
466
467 } else {
468 set_gpio_edge(gpionr, 0);
469 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
470 set_gpio_inen(gpionr, 1);
471 }
472
1394f032
BW		 473 SSYNC();
474
475 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
476 set_irq_handler(irq, handle_edge_irq);
477 else
478 set_irq_handler(irq, handle_level_irq);
479
480 return 0;
481}
482
cfefe3c6
MH		 483#ifdef CONFIG_PM
484int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
485{
486 unsigned gpio = irq_to_gpio(irq);
487
488 if (state)
489 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
490 else
491 gpio_pm_wakeup_free(gpio);
492
493 return 0;
494}
495#endif
496
1394f032
BW		 497static struct irq_chip bfin_gpio_irqchip = {
498 .ack = bfin_gpio_ack_irq,
499 .mask = bfin_gpio_mask_irq,
500 .mask_ack = bfin_gpio_mask_ack_irq,
501 .unmask = bfin_gpio_unmask_irq,
1f2d1869
MH		 502 .disable = bfin_gpio_mask_irq,
503 .enable = bfin_gpio_unmask_irq,
1394f032
BW		 504 .set_type = bfin_gpio_irq_type,
505 .startup = bfin_gpio_irq_startup,
cfefe3c6
MH		 506 .shutdown = bfin_gpio_irq_shutdown,
507#ifdef CONFIG_PM
508 .set_wake = bfin_gpio_set_wake,
509#endif
1394f032
BW		 510};
511
2c4f829b
MH		 512static void bfin_demux_gpio_irq(unsigned int inta_irq,
513 struct irq_desc *desc)
1394f032 514{
2c4f829b
MH		 515 unsigned int i, gpio, mask, irq, search = 0;
516
517 switch (inta_irq) {
518#if defined(CONFIG_BF53x)
519 case IRQ_PROG_INTA:
520 irq = IRQ_PF0;
521 search = 1;
522 break;
523# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
524 case IRQ_MAC_RX:
525 irq = IRQ_PH0;
526 break;
527# endif
528#elif defined(CONFIG_BF52x)
529 case IRQ_PORTF_INTA:
530 irq = IRQ_PF0;
531 break;
532 case IRQ_PORTG_INTA:
533 irq = IRQ_PG0;
534 break;
535 case IRQ_PORTH_INTA:
536 irq = IRQ_PH0;
537 break;
538#elif defined(CONFIG_BF561)
539 case IRQ_PROG0_INTA:
540 irq = IRQ_PF0;
541 break;
542 case IRQ_PROG1_INTA:
543 irq = IRQ_PF16;
544 break;
545 case IRQ_PROG2_INTA:
546 irq = IRQ_PF32;
547 break;
548#endif
549 default:
550 BUG();
551 return;
552 }
553
554 if (search) {
cfefe3c6 555 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
2c4f829b
MH		 556 irq += i;
557
558 mask = get_gpiop_data(i) &
559 (gpio_enabled[gpio_bank(i)] &
560 get_gpiop_maska(i));
561
562 while (mask) {
563 if (mask & 1) {
564 desc = irq_desc + irq;
565 desc->handle_irq(irq, desc);
566 }
567 irq++;
568 mask >>= 1;
1394f032 569 }
1394f032 570 }
2c4f829b
MH		 571 } else {
572 gpio = irq_to_gpio(irq);
573 mask = get_gpiop_data(gpio) &
574 (gpio_enabled[gpio_bank(gpio)] &
575 get_gpiop_maska(gpio));
576
577 do {
578 if (mask & 1) {
579 desc = irq_desc + irq;
580 desc->handle_irq(irq, desc);
581 }
582 irq++;
583 mask >>= 1;
584 } while (mask);
1394f032 585 }
2c4f829b 586
1394f032
BW		 587}
588
a055b2b4 589#else /* CONFIG_BF54x */
34e0fc89
MH		 590
591#define NR_PINT_SYS_IRQS 4
592#define NR_PINT_BITS 32
593#define NR_PINTS 160
594#define IRQ_NOT_AVAIL 0xFF
595
596#define PINT_2_BANK(x) ((x) >> 5)
597#define PINT_2_BIT(x) ((x) & 0x1F)
598#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
599
600static unsigned char irq2pint_lut[NR_PINTS];
e3f23000 601static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
34e0fc89 602
8baf560b
MH		 603static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
604static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
605
606
34e0fc89
MH		 607struct pin_int_t {
608 unsigned int mask_set;
609 unsigned int mask_clear;
610 unsigned int request;
611 unsigned int assign;
612 unsigned int edge_set;
613 unsigned int edge_clear;
614 unsigned int invert_set;
615 unsigned int invert_clear;
616 unsigned int pinstate;
617 unsigned int latch;
618};
619
620static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
621 (struct pin_int_t *)PINT0_MASK_SET,
622 (struct pin_int_t *)PINT1_MASK_SET,
623 (struct pin_int_t *)PINT2_MASK_SET,
624 (struct pin_int_t *)PINT3_MASK_SET,
625};
626
affee2b2
MH		 627extern void bfin_gpio_irq_prepare(unsigned gpio);
628
464abc5d 629inline unsigned short get_irq_base(u8 bank, u8 bmap)
34e0fc89
MH		 630{
631
632 u16 irq_base;
633
634 if (bank < 2) { /*PA-PB */
635 irq_base = IRQ_PA0 + bmap * 16;
636 } else { /*PC-PJ */
637 irq_base = IRQ_PC0 + bmap * 16;
638 }
639
640 return irq_base;
641
642}
643
644 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
645void init_pint_lut(void)
646{
647 u16 bank, bit, irq_base, bit_pos;
648 u32 pint_assign;
649 u8 bmap;
650
651 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
652
653 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
654
655 pint_assign = pint[bank]->assign;
656
657 for (bit = 0; bit < NR_PINT_BITS; bit++) {
658
659 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
660
661 irq_base = get_irq_base(bank, bmap);
662
663 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
664 bit_pos = bit + bank * NR_PINT_BITS;
665
e3f23000 666 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
34e0fc89
MH		 667 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
668
669 }
670
671 }
672
673}
674
34e0fc89
MH		 675static void bfin_gpio_ack_irq(unsigned int irq)
676{
677 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
8baf560b
MH		 678 u32 pintbit = PINT_BIT(pint_val);
679 u8 bank = PINT_2_BANK(pint_val);
680
681 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
682 if (pint[bank]->invert_set & pintbit)
683 pint[bank]->invert_clear = pintbit;
684 else
685 pint[bank]->invert_set = pintbit;
686 }
687 pint[bank]->request = pintbit;
34e0fc89 688
34e0fc89
MH		 689 SSYNC();
690}
691
692static void bfin_gpio_mask_ack_irq(unsigned int irq)
693{
694 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 695 u32 pintbit = PINT_BIT(pint_val);
696 u8 bank = PINT_2_BANK(pint_val);
34e0fc89 697
8baf560b
MH		 698 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
699 if (pint[bank]->invert_set & pintbit)
700 pint[bank]->invert_clear = pintbit;
701 else
702 pint[bank]->invert_set = pintbit;
703 }
704
e3f23000
MH		 705 pint[bank]->request = pintbit;
706 pint[bank]->mask_clear = pintbit;
34e0fc89
MH		 707 SSYNC();
708}
709
710static void bfin_gpio_mask_irq(unsigned int irq)
711{
712 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
713
714 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
715 SSYNC();
716}
717
718static void bfin_gpio_unmask_irq(unsigned int irq)
719{
720 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 721 u32 pintbit = PINT_BIT(pint_val);
722 u8 bank = PINT_2_BANK(pint_val);
34e0fc89 723
e3f23000
MH		 724 pint[bank]->request = pintbit;
725 pint[bank]->mask_set = pintbit;
34e0fc89
MH		 726 SSYNC();
727}
728
729static unsigned int bfin_gpio_irq_startup(unsigned int irq)
730{
8baf560b 731 u16 gpionr = irq_to_gpio(irq);
34e0fc89
MH		 732 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
733
50e163ce
MH		 734 if (pint_val == IRQ_NOT_AVAIL) {
735 printk(KERN_ERR
736 "GPIO IRQ %d :Not in PINT Assign table "
737 "Reconfigure Interrupt to Port Assignemt\n", irq);
34e0fc89 738 return -ENODEV;
50e163ce 739 }
34e0fc89 740
affee2b2
MH		 741 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
742 bfin_gpio_irq_prepare(gpionr);
34e0fc89
MH		 743
744 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
745 bfin_gpio_unmask_irq(irq);
746
affee2b2 747 return 0;
34e0fc89
MH		 748}
749
750static void bfin_gpio_irq_shutdown(unsigned int irq)
751{
8baf560b
MH		 752 u16 gpionr = irq_to_gpio(irq);
753
34e0fc89 754 bfin_gpio_mask_irq(irq);
8baf560b 755 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
34e0fc89
MH		 756}
757
758static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
759{
760
8baf560b 761 u16 gpionr = irq_to_gpio(irq);
34e0fc89 762 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 763 u32 pintbit = PINT_BIT(pint_val);
764 u8 bank = PINT_2_BANK(pint_val);
34e0fc89
MH		 765
766 if (pint_val == IRQ_NOT_AVAIL)
767 return -ENODEV;
768
769 if (type == IRQ_TYPE_PROBE) {
770 /* only probe unenabled GPIO interrupt lines */
771 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
772 return 0;
773 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
774 }
775
776 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
777 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
affee2b2
MH		 778 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
779 bfin_gpio_irq_prepare(gpionr);
34e0fc89
MH		 780
781 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
782 } else {
783 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
784 return 0;
785 }
786
34e0fc89 787 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
e3f23000 788 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
34e0fc89 789 else
8baf560b 790 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
34e0fc89 791
8baf560b
MH		 792 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
793 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
34e0fc89 794
8baf560b 795 gpio_both_edge_triggered[bank] |= pintbit;
34e0fc89 796
8baf560b
MH		 797 if (gpio_get_value(gpionr))
798 pint[bank]->invert_set = pintbit;
799 else
800 pint[bank]->invert_clear = pintbit;
801 } else {
802 gpio_both_edge_triggered[bank] &= ~pintbit;
803 }
804
805 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
806 pint[bank]->edge_set = pintbit;
34e0fc89 807 set_irq_handler(irq, handle_edge_irq);
8baf560b
MH		 808 } else {
809 pint[bank]->edge_clear = pintbit;
34e0fc89 810 set_irq_handler(irq, handle_level_irq);
8baf560b
MH		 811 }
812
813 SSYNC();
34e0fc89
MH		 814
815 return 0;
816}
817
cfefe3c6
MH		 818#ifdef CONFIG_PM
819u32 pint_saved_masks[NR_PINT_SYS_IRQS];
820u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
821
822int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
823{
824 u32 pint_irq;
825 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
826 u32 bank = PINT_2_BANK(pint_val);
827 u32 pintbit = PINT_BIT(pint_val);
828
829 switch (bank) {
830 case 0:
831 pint_irq = IRQ_PINT0;
832 break;
833 case 2:
834 pint_irq = IRQ_PINT2;
835 break;
836 case 3:
837 pint_irq = IRQ_PINT3;
838 break;
839 case 1:
840 pint_irq = IRQ_PINT1;
841 break;
842 default:
843 return -EINVAL;
844 }
845
846 bfin_internal_set_wake(pint_irq, state);
847
848 if (state)
849 pint_wakeup_masks[bank] |= pintbit;
850 else
851 pint_wakeup_masks[bank] &= ~pintbit;
852
853 return 0;
854}
855
856u32 bfin_pm_setup(void)
857{
858 u32 val, i;
859
860 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
861 val = pint[i]->mask_clear;
862 pint_saved_masks[i] = val;
863 if (val ^ pint_wakeup_masks[i]) {
864 pint[i]->mask_clear = val;
865 pint[i]->mask_set = pint_wakeup_masks[i];
866 }
867 }
868
869 return 0;
870}
871
872void bfin_pm_restore(void)
873{
874 u32 i, val;
875
876 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
877 val = pint_saved_masks[i];
878 if (val ^ pint_wakeup_masks[i]) {
879 pint[i]->mask_clear = pint[i]->mask_clear;
880 pint[i]->mask_set = val;
881 }
882 }
883}
884#endif
885
34e0fc89
MH		 886static struct irq_chip bfin_gpio_irqchip = {
887 .ack = bfin_gpio_ack_irq,
888 .mask = bfin_gpio_mask_irq,
889 .mask_ack = bfin_gpio_mask_ack_irq,
890 .unmask = bfin_gpio_unmask_irq,
1f2d1869
MH		 891 .disable = bfin_gpio_mask_irq,
892 .enable = bfin_gpio_unmask_irq,
34e0fc89
MH		 893 .set_type = bfin_gpio_irq_type,
894 .startup = bfin_gpio_irq_startup,
cfefe3c6
MH		 895 .shutdown = bfin_gpio_irq_shutdown,
896#ifdef CONFIG_PM
897 .set_wake = bfin_gpio_set_wake,
898#endif
34e0fc89
MH		 899};
900
2c4f829b
MH		 901static void bfin_demux_gpio_irq(unsigned int inta_irq,
902 struct irq_desc *desc)
34e0fc89
MH		 903{
904 u8 bank, pint_val;
905 u32 request, irq;
906
2c4f829b 907 switch (inta_irq) {
34e0fc89
MH		 908 case IRQ_PINT0:
909 bank = 0;
910 break;
911 case IRQ_PINT2:
912 bank = 2;
913 break;
914 case IRQ_PINT3:
915 bank = 3;
916 break;
917 case IRQ_PINT1:
918 bank = 1;
919 break;
e3f23000
MH		 920 default:
921 return;
34e0fc89
MH		 922 }
923
924 pint_val = bank * NR_PINT_BITS;
925
926 request = pint[bank]->request;
927
928 while (request) {
929 if (request & 1) {
e3f23000
MH		 930 irq = pint2irq_lut[pint_val] + SYS_IRQS;
931 desc = irq_desc + irq;
34e0fc89
MH		 932 desc->handle_irq(irq, desc);
933 }
934 pint_val++;
935 request >>= 1;
936 }
937
938}
a055b2b4 939#endif
1394f032 940
8be80ed3
BS		 941void __init init_exception_vectors(void)
942{
943 SSYNC();
944
f0b5d12f
MF		 945 /* cannot program in software:
946 * evt0 - emulation (jtag)
947 * evt1 - reset
948 */
949 bfin_write_EVT2(evt_nmi);
8be80ed3
BS		 950 bfin_write_EVT3(trap);
951 bfin_write_EVT5(evt_ivhw);
952 bfin_write_EVT6(evt_timer);
953 bfin_write_EVT7(evt_evt7);
954 bfin_write_EVT8(evt_evt8);
955 bfin_write_EVT9(evt_evt9);
956 bfin_write_EVT10(evt_evt10);
957 bfin_write_EVT11(evt_evt11);
958 bfin_write_EVT12(evt_evt12);
959 bfin_write_EVT13(evt_evt13);
960 bfin_write_EVT14(evt14_softirq);
961 bfin_write_EVT15(evt_system_call);
962 CSYNC();
963}
964
1394f032
BW		 965/*
966 * This function should be called during kernel startup to initialize
967 * the BFin IRQ handling routines.
968 */
969int __init init_arch_irq(void)
970{
971 int irq;
972 unsigned long ilat = 0;
973 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
2c4f829b 974#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
24a07a12
RH		 975 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
976 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
a055b2b4 977# ifdef CONFIG_BF54x
59003145 978 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
a055b2b4 979# endif
24a07a12 980#else
1394f032 981 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
24a07a12 982#endif
1394f032
BW		 983
984 local_irq_disable();
985
d70536ec 986#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
95a86b5e
MF		 987 /* Clear EMAC Interrupt Status bits so we can demux it later */
988 bfin_write_EMAC_SYSTAT(-1);
989#endif
990
a055b2b4
MF		 991#ifdef CONFIG_BF54x
992# ifdef CONFIG_PINTx_REASSIGN
34e0fc89
MH		 993 pint[0]->assign = CONFIG_PINT0_ASSIGN;
994 pint[1]->assign = CONFIG_PINT1_ASSIGN;
995 pint[2]->assign = CONFIG_PINT2_ASSIGN;
996 pint[3]->assign = CONFIG_PINT3_ASSIGN;
a055b2b4 997# endif
34e0fc89
MH		 998 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
999 init_pint_lut();
1000#endif
1001
1002 for (irq = 0; irq <= SYS_IRQS; irq++) {
1394f032
BW		 1003 if (irq <= IRQ_CORETMR)
1004 set_irq_chip(irq, &bfin_core_irqchip);
1005 else
1006 set_irq_chip(irq, &bfin_internal_irqchip);
1394f032 1007
464abc5d 1008 switch (irq) {
59003145 1009#if defined(CONFIG_BF53x)
464abc5d 1010 case IRQ_PROG_INTA:
a055b2b4 1011# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
464abc5d 1012 case IRQ_MAC_RX:
a055b2b4 1013# endif
59003145 1014#elif defined(CONFIG_BF54x)
464abc5d
MH		 1015 case IRQ_PINT0:
1016 case IRQ_PINT1:
1017 case IRQ_PINT2:
1018 case IRQ_PINT3:
59003145 1019#elif defined(CONFIG_BF52x)
464abc5d
MH		 1020 case IRQ_PORTF_INTA:
1021 case IRQ_PORTG_INTA:
1022 case IRQ_PORTH_INTA:
2c4f829b 1023#elif defined(CONFIG_BF561)
464abc5d
MH		 1024 case IRQ_PROG0_INTA:
1025 case IRQ_PROG1_INTA:
1026 case IRQ_PROG2_INTA:
1394f032 1027#endif
464abc5d
MH		 1028 set_irq_chained_handler(irq,
1029 bfin_demux_gpio_irq);
1030 break;
1394f032 1031#ifdef BF537_GENERIC_ERROR_INT_DEMUX
464abc5d 1032 case IRQ_GENERIC_ERROR:
1394f032 1033 set_irq_handler(irq, bfin_demux_error_irq);
464abc5d
MH		 1034
1035 break;
1394f032 1036#endif
464abc5d
MH		 1037 default:
1038 set_irq_handler(irq, handle_simple_irq);
1039 break;
1040 }
1394f032 1041 }
464abc5d 1042
1394f032 1043#ifdef BF537_GENERIC_ERROR_INT_DEMUX
464abc5d
MH		 1044 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1045 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1046 handle_level_irq);
1394f032
BW		 1047#endif
1048
464abc5d
MH		 1049 /* if configured as edge, then will be changed to do_edge_IRQ */
1050 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1051 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1052 handle_level_irq);
2c4f829b 1053
a055b2b4 1054
1394f032
BW		 1055 bfin_write_IMASK(0);
1056 CSYNC();
1057 ilat = bfin_read_ILAT();
1058 CSYNC();
1059 bfin_write_ILAT(ilat);
1060 CSYNC();
1061
34e0fc89 1062 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1394f032
BW		 1063 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1064 * local_irq_enable()
1065 */
1066 program_IAR();
1067 /* Therefore it's better to setup IARs before interrupts enabled */
1068 search_IAR();
1069
1070 /* Enable interrupts IVG7-15 */
1071 irq_flags = irq_flags | IMASK_IVG15 |
1072 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
34e0fc89 1073 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1394f032 1074
fe9ec9b9 1075#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
56f5f590 1076 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
55546ac4
MH		 1077#if defined(CONFIG_BF52x)
1078 /* BF52x system reset does not properly reset SIC_IWR1 which
1079 * will screw up the bootrom as it relies on MDMA0/1 waking it
1080 * up from IDLE instructions. See this report for more info:
1081 * http://blackfin.uclinux.org/gf/tracker/4323
1082 */
1083 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1084#else
56f5f590 1085 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
55546ac4 1086#endif
fe9ec9b9 1087# ifdef CONFIG_BF54x
56f5f590 1088 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
fe9ec9b9
MH		 1089# endif
1090#else
56f5f590 1091 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
fe9ec9b9
MH		 1092#endif
1093
1394f032
BW		 1094 return 0;
1095}
1096
1097#ifdef CONFIG_DO_IRQ_L1
a055b2b4 1098__attribute__((l1_text))
1394f032 1099#endif
1394f032
BW		 1100void do_irq(int vec, struct pt_regs *fp)
1101{
1102 if (vec == EVT_IVTMR_P) {
1103 vec = IRQ_CORETMR;
1104 } else {
1105 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1106 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
2c4f829b 1107#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
24a07a12 1108 unsigned long sic_status[3];
1394f032 1109
4fb45241
MH		 1110 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1111 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
59003145 1112#ifdef CONFIG_BF54x
4fb45241 1113 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
59003145 1114#endif
1f83b8f1 1115 for (;; ivg++) {
24a07a12
RH		 1116 if (ivg >= ivg_stop) {
1117 atomic_inc(&num_spurious);
1118 return;
1119 }
34e0fc89 1120 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
24a07a12
RH		 1121 break;
1122 }
1123#else
1124 unsigned long sic_status;
464abc5d 1125
1394f032
BW		 1126 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1127
1128 for (;; ivg++) {
1129 if (ivg >= ivg_stop) {
1130 atomic_inc(&num_spurious);
1131 return;
1132 } else if (sic_status & ivg->isrflag)
1133 break;
1134 }
24a07a12 1135#endif
1394f032
BW		 1136 vec = ivg->irqno;
1137 }
1138 asm_do_IRQ(vec, fp);
1394f032 1139}
Linux kernel - Deliverables
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