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[Blackfin] arch: fix bug - linux-2.6.24 (delayed) disable IRQ feature not functional...
[deliverable/linux.git] / arch / blackfin / mach-common / ints-priority.c
CommitLineData
1394f032 1/*
cfefe3c6 2 * File: arch/blackfin/mach-common/ints-priority.c
1394f032
BW		 3 * Based on:
4 * Author:
5 *
6 * Created: ?
d2d50aa9 7 * Description: Set up the interrupt priorities
1394f032
BW		 8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
cfefe3c6 16 * Copyright 2004-2008 Analog Devices Inc.
1394f032
BW		 17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36#include <linux/module.h>
37#include <linux/kernel_stat.h>
38#include <linux/seq_file.h>
39#include <linux/irq.h>
40#ifdef CONFIG_KGDB
41#include <linux/kgdb.h>
42#endif
43#include <asm/traps.h>
44#include <asm/blackfin.h>
45#include <asm/gpio.h>
46#include <asm/irq_handler.h>
47
48#ifdef BF537_FAMILY
49# define BF537_GENERIC_ERROR_INT_DEMUX
50#else
51# undef BF537_GENERIC_ERROR_INT_DEMUX
52#endif
53
54/*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
a99bbccd
MF		 61/* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
66 */
67unsigned long irq_flags = 0x1f;
1394f032
BW		 68
69/* The number of spurious interrupts */
70atomic_t num_spurious;
71
cfefe3c6
MH		 72#ifdef CONFIG_PM
73unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
74#endif
75
1394f032
BW		 76struct ivgx {
77 /* irq number for request_irq, available in mach-bf533/irq.h */
24a07a12 78 unsigned int irqno;
1394f032 79 /* corresponding bit in the SIC_ISR register */
24a07a12 80 unsigned int isrflag;
1394f032
BW		 81} ivg_table[NR_PERI_INTS];
82
83struct ivg_slice {
84 /* position of first irq in ivg_table for given ivg */
85 struct ivgx *ifirst;
86 struct ivgx *istop;
87} ivg7_13[IVG13 - IVG7 + 1];
88
89static void search_IAR(void);
90
91/*
92 * Search SIC_IAR and fill tables with the irqvalues
93 * and their positions in the SIC_ISR register.
94 */
95static void __init search_IAR(void)
96{
97 unsigned ivg, irq_pos = 0;
98 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
99 int irqn;
100
34e0fc89 101 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
1394f032
BW		 102
103 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
104 int iar_shift = (irqn & 7) * 4;
2c4f829b 105 if (ivg == (0xf &
59003145 106#ifndef CONFIG_BF52x
34e0fc89 107 bfin_read32((unsigned long *)SIC_IAR0 +
1394f032 108 (irqn >> 3)) >> iar_shift)) {
59003145
MH		 109#else
110 bfin_read32((unsigned long *)SIC_IAR0 +
111 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
112#endif
1394f032 113 ivg_table[irq_pos].irqno = IVG7 + irqn;
24a07a12 114 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
1394f032
BW		 115 ivg7_13[ivg].istop++;
116 irq_pos++;
117 }
118 }
119 }
120}
121
122/*
123 * This is for BF533 internal IRQs
124 */
125
126static void ack_noop(unsigned int irq)
127{
128 /* Dummy function. */
129}
130
131static void bfin_core_mask_irq(unsigned int irq)
132{
133 irq_flags &= ~(1 << irq);
134 if (!irqs_disabled())
135 local_irq_enable();
136}
137
138static void bfin_core_unmask_irq(unsigned int irq)
139{
140 irq_flags |= 1 << irq;
141 /*
142 * If interrupts are enabled, IMASK must contain the same value
143 * as irq_flags. Make sure that invariant holds. If interrupts
144 * are currently disabled we need not do anything; one of the
145 * callers will take care of setting IMASK to the proper value
146 * when reenabling interrupts.
147 * local_irq_enable just does "STI irq_flags", so it's exactly
148 * what we need.
149 */
150 if (!irqs_disabled())
151 local_irq_enable();
152 return;
153}
154
155static void bfin_internal_mask_irq(unsigned int irq)
156{
59003145 157#ifdef CONFIG_BF53x
1394f032
BW		 158 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
159 ~(1 << (irq - (IRQ_CORETMR + 1))));
24a07a12
RH		 160#else
161 unsigned mask_bank, mask_bit;
1f83b8f1
MF		 162 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
163 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
c04d66bb
BW		 164 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
165 ~(1 << mask_bit));
24a07a12 166#endif
1394f032
BW		 167 SSYNC();
168}
169
170static void bfin_internal_unmask_irq(unsigned int irq)
171{
59003145 172#ifdef CONFIG_BF53x
1394f032
BW		 173 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
174 (1 << (irq - (IRQ_CORETMR + 1))));
24a07a12
RH		 175#else
176 unsigned mask_bank, mask_bit;
1f83b8f1 177 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
c04d66bb
BW		 178 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
179 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
180 (1 << mask_bit));
24a07a12 181#endif
1394f032
BW		 182 SSYNC();
183}
184
cfefe3c6
MH		 185#ifdef CONFIG_PM
186int bfin_internal_set_wake(unsigned int irq, unsigned int state)
187{
188 unsigned bank, bit;
189 unsigned long flags;
190 bank = (irq - (IRQ_CORETMR + 1)) / 32;
191 bit = (irq - (IRQ_CORETMR + 1)) % 32;
192
193 local_irq_save(flags);
194
195 if (state)
196 bfin_sic_iwr[bank] |= (1 << bit);
197 else
198 bfin_sic_iwr[bank] &= ~(1 << bit);
199
200 local_irq_restore(flags);
201
202 return 0;
203}
204#endif
205
1394f032
BW		 206static struct irq_chip bfin_core_irqchip = {
207 .ack = ack_noop,
208 .mask = bfin_core_mask_irq,
209 .unmask = bfin_core_unmask_irq,
210};
211
212static struct irq_chip bfin_internal_irqchip = {
213 .ack = ack_noop,
214 .mask = bfin_internal_mask_irq,
215 .unmask = bfin_internal_unmask_irq,
ce3b7bb6
MH		 216 .mask_ack = bfin_internal_mask_irq,
217 .disable = bfin_internal_mask_irq,
218 .enable = bfin_internal_unmask_irq,
cfefe3c6
MH		 219#ifdef CONFIG_PM
220 .set_wake = bfin_internal_set_wake,
221#endif
1394f032
BW		 222};
223
224#ifdef BF537_GENERIC_ERROR_INT_DEMUX
225static int error_int_mask;
226
227static void bfin_generic_error_ack_irq(unsigned int irq)
228{
229
230}
231
232static void bfin_generic_error_mask_irq(unsigned int irq)
233{
234 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
235
236 if (!error_int_mask) {
237 local_irq_disable();
238 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
2c4f829b 239 ~(1 << (IRQ_GENERIC_ERROR -
1394f032
BW		 240 (IRQ_CORETMR + 1))));
241 SSYNC();
242 local_irq_enable();
243 }
244}
245
246static void bfin_generic_error_unmask_irq(unsigned int irq)
247{
248 local_irq_disable();
249 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
250 (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
251 SSYNC();
252 local_irq_enable();
253
254 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
255}
256
257static struct irq_chip bfin_generic_error_irqchip = {
258 .ack = bfin_generic_error_ack_irq,
259 .mask = bfin_generic_error_mask_irq,
260 .unmask = bfin_generic_error_unmask_irq,
261};
262
263static void bfin_demux_error_irq(unsigned int int_err_irq,
2c4f829b 264 struct irq_desc *inta_desc)
1394f032
BW		 265{
266 int irq = 0;
267
268 SSYNC();
269
270#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
271 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
272 irq = IRQ_MAC_ERROR;
273 else
274#endif
275 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
276 irq = IRQ_SPORT0_ERROR;
277 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
278 irq = IRQ_SPORT1_ERROR;
279 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
280 irq = IRQ_PPI_ERROR;
281 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
282 irq = IRQ_CAN_ERROR;
283 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
284 irq = IRQ_SPI_ERROR;
285 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
286 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
287 irq = IRQ_UART0_ERROR;
288 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
289 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
290 irq = IRQ_UART1_ERROR;
291
292 if (irq) {
293 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
294 struct irq_desc *desc = irq_desc + irq;
295 desc->handle_irq(irq, desc);
296 } else {
297
298 switch (irq) {
299 case IRQ_PPI_ERROR:
300 bfin_write_PPI_STATUS(PPI_ERR_MASK);
301 break;
302#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
303 case IRQ_MAC_ERROR:
304 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
305 break;
306#endif
307 case IRQ_SPORT0_ERROR:
308 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
309 break;
310
311 case IRQ_SPORT1_ERROR:
312 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
313 break;
314
315 case IRQ_CAN_ERROR:
316 bfin_write_CAN_GIS(CAN_ERR_MASK);
317 break;
318
319 case IRQ_SPI_ERROR:
320 bfin_write_SPI_STAT(SPI_ERR_MASK);
321 break;
322
323 default:
324 break;
325 }
326
327 pr_debug("IRQ %d:"
34e0fc89
MH		 328 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
329 irq);
1394f032
BW		 330 }
331 } else
332 printk(KERN_ERR
333 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
334 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
335 __FUNCTION__, __FILE__, __LINE__);
336
1394f032
BW		 337}
338#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
339
a055b2b4 340#if !defined(CONFIG_BF54x)
1394f032
BW		 341
342static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
343static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
344
6fce6a8d 345
1394f032
BW		 346static void bfin_gpio_ack_irq(unsigned int irq)
347{
348 u16 gpionr = irq - IRQ_PF0;
349
350 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
351 set_gpio_data(gpionr, 0);
352 SSYNC();
353 }
354}
355
356static void bfin_gpio_mask_ack_irq(unsigned int irq)
357{
358 u16 gpionr = irq - IRQ_PF0;
359
360 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
361 set_gpio_data(gpionr, 0);
362 SSYNC();
363 }
364
365 set_gpio_maska(gpionr, 0);
366 SSYNC();
367}
368
369static void bfin_gpio_mask_irq(unsigned int irq)
370{
371 set_gpio_maska(irq - IRQ_PF0, 0);
372 SSYNC();
373}
374
375static void bfin_gpio_unmask_irq(unsigned int irq)
376{
377 set_gpio_maska(irq - IRQ_PF0, 1);
378 SSYNC();
379}
380
381static unsigned int bfin_gpio_irq_startup(unsigned int irq)
382{
383 unsigned int ret;
384 u16 gpionr = irq - IRQ_PF0;
6fce6a8d 385 char buf[8];
1394f032
BW		 386
387 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
6fce6a8d
MH		 388 snprintf(buf, sizeof buf, "IRQ %d", irq);
389 ret = gpio_request(gpionr, buf);
1394f032
BW		 390 if (ret)
391 return ret;
392 }
393
394 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
395 bfin_gpio_unmask_irq(irq);
396
397 return ret;
398}
399
400static void bfin_gpio_irq_shutdown(unsigned int irq)
401{
402 bfin_gpio_mask_irq(irq);
403 gpio_free(irq - IRQ_PF0);
404 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
405}
406
407static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
408{
409
410 unsigned int ret;
6fce6a8d 411 char buf[8];
1394f032
BW		 412 u16 gpionr = irq - IRQ_PF0;
413
414 if (type == IRQ_TYPE_PROBE) {
415 /* only probe unenabled GPIO interrupt lines */
416 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
417 return 0;
418 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
419 }
420
421 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
34e0fc89 422 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1394f032 423 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
6fce6a8d
MH		 424 snprintf(buf, sizeof buf, "IRQ %d", irq);
425 ret = gpio_request(gpionr, buf);
1394f032
BW		 426 if (ret)
427 return ret;
428 }
429
430 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
431 } else {
432 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
433 return 0;
434 }
435
f1bceb47 436 set_gpio_inen(gpionr, 0);
1394f032 437 set_gpio_dir(gpionr, 0);
1394f032
BW		 438
439 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
440 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
441 set_gpio_both(gpionr, 1);
442 else
443 set_gpio_both(gpionr, 0);
444
445 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
446 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
447 else
448 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
449
f1bceb47
MH		 450 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
451 set_gpio_edge(gpionr, 1);
452 set_gpio_inen(gpionr, 1);
453 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
454 set_gpio_data(gpionr, 0);
455
456 } else {
457 set_gpio_edge(gpionr, 0);
458 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
459 set_gpio_inen(gpionr, 1);
460 }
461
1394f032
BW		 462 SSYNC();
463
464 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
465 set_irq_handler(irq, handle_edge_irq);
466 else
467 set_irq_handler(irq, handle_level_irq);
468
469 return 0;
470}
471
cfefe3c6
MH		 472#ifdef CONFIG_PM
473int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
474{
475 unsigned gpio = irq_to_gpio(irq);
476
477 if (state)
478 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
479 else
480 gpio_pm_wakeup_free(gpio);
481
482 return 0;
483}
484#endif
485
1394f032
BW		 486static struct irq_chip bfin_gpio_irqchip = {
487 .ack = bfin_gpio_ack_irq,
488 .mask = bfin_gpio_mask_irq,
489 .mask_ack = bfin_gpio_mask_ack_irq,
490 .unmask = bfin_gpio_unmask_irq,
491 .set_type = bfin_gpio_irq_type,
492 .startup = bfin_gpio_irq_startup,
cfefe3c6
MH		 493 .shutdown = bfin_gpio_irq_shutdown,
494#ifdef CONFIG_PM
495 .set_wake = bfin_gpio_set_wake,
496#endif
1394f032
BW		 497};
498
2c4f829b
MH		 499static void bfin_demux_gpio_irq(unsigned int inta_irq,
500 struct irq_desc *desc)
1394f032 501{
2c4f829b
MH		 502 unsigned int i, gpio, mask, irq, search = 0;
503
504 switch (inta_irq) {
505#if defined(CONFIG_BF53x)
506 case IRQ_PROG_INTA:
507 irq = IRQ_PF0;
508 search = 1;
509 break;
510# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
511 case IRQ_MAC_RX:
512 irq = IRQ_PH0;
513 break;
514# endif
515#elif defined(CONFIG_BF52x)
516 case IRQ_PORTF_INTA:
517 irq = IRQ_PF0;
518 break;
519 case IRQ_PORTG_INTA:
520 irq = IRQ_PG0;
521 break;
522 case IRQ_PORTH_INTA:
523 irq = IRQ_PH0;
524 break;
525#elif defined(CONFIG_BF561)
526 case IRQ_PROG0_INTA:
527 irq = IRQ_PF0;
528 break;
529 case IRQ_PROG1_INTA:
530 irq = IRQ_PF16;
531 break;
532 case IRQ_PROG2_INTA:
533 irq = IRQ_PF32;
534 break;
535#endif
536 default:
537 BUG();
538 return;
539 }
540
541 if (search) {
cfefe3c6 542 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
2c4f829b
MH		 543 irq += i;
544
545 mask = get_gpiop_data(i) &
546 (gpio_enabled[gpio_bank(i)] &
547 get_gpiop_maska(i));
548
549 while (mask) {
550 if (mask & 1) {
551 desc = irq_desc + irq;
552 desc->handle_irq(irq, desc);
553 }
554 irq++;
555 mask >>= 1;
1394f032 556 }
1394f032 557 }
2c4f829b
MH		 558 } else {
559 gpio = irq_to_gpio(irq);
560 mask = get_gpiop_data(gpio) &
561 (gpio_enabled[gpio_bank(gpio)] &
562 get_gpiop_maska(gpio));
563
564 do {
565 if (mask & 1) {
566 desc = irq_desc + irq;
567 desc->handle_irq(irq, desc);
568 }
569 irq++;
570 mask >>= 1;
571 } while (mask);
1394f032 572 }
2c4f829b 573
1394f032
BW		 574}
575
a055b2b4 576#else /* CONFIG_BF54x */
34e0fc89
MH		 577
578#define NR_PINT_SYS_IRQS 4
579#define NR_PINT_BITS 32
580#define NR_PINTS 160
581#define IRQ_NOT_AVAIL 0xFF
582
583#define PINT_2_BANK(x) ((x) >> 5)
584#define PINT_2_BIT(x) ((x) & 0x1F)
585#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
586
587static unsigned char irq2pint_lut[NR_PINTS];
e3f23000 588static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
34e0fc89 589
8baf560b
MH		 590static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
591static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
592
593
34e0fc89
MH		 594struct pin_int_t {
595 unsigned int mask_set;
596 unsigned int mask_clear;
597 unsigned int request;
598 unsigned int assign;
599 unsigned int edge_set;
600 unsigned int edge_clear;
601 unsigned int invert_set;
602 unsigned int invert_clear;
603 unsigned int pinstate;
604 unsigned int latch;
605};
606
607static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
608 (struct pin_int_t *)PINT0_MASK_SET,
609 (struct pin_int_t *)PINT1_MASK_SET,
610 (struct pin_int_t *)PINT2_MASK_SET,
611 (struct pin_int_t *)PINT3_MASK_SET,
612};
613
614unsigned short get_irq_base(u8 bank, u8 bmap)
615{
616
617 u16 irq_base;
618
619 if (bank < 2) { /*PA-PB */
620 irq_base = IRQ_PA0 + bmap * 16;
621 } else { /*PC-PJ */
622 irq_base = IRQ_PC0 + bmap * 16;
623 }
624
625 return irq_base;
626
627}
628
629 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
630void init_pint_lut(void)
631{
632 u16 bank, bit, irq_base, bit_pos;
633 u32 pint_assign;
634 u8 bmap;
635
636 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
637
638 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
639
640 pint_assign = pint[bank]->assign;
641
642 for (bit = 0; bit < NR_PINT_BITS; bit++) {
643
644 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
645
646 irq_base = get_irq_base(bank, bmap);
647
648 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
649 bit_pos = bit + bank * NR_PINT_BITS;
650
e3f23000 651 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
34e0fc89
MH		 652 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
653
654 }
655
656 }
657
658}
659
34e0fc89
MH		 660static void bfin_gpio_ack_irq(unsigned int irq)
661{
662 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
8baf560b
MH		 663 u32 pintbit = PINT_BIT(pint_val);
664 u8 bank = PINT_2_BANK(pint_val);
665
666 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
667 if (pint[bank]->invert_set & pintbit)
668 pint[bank]->invert_clear = pintbit;
669 else
670 pint[bank]->invert_set = pintbit;
671 }
672 pint[bank]->request = pintbit;
34e0fc89 673
34e0fc89
MH		 674 SSYNC();
675}
676
677static void bfin_gpio_mask_ack_irq(unsigned int irq)
678{
679 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 680 u32 pintbit = PINT_BIT(pint_val);
681 u8 bank = PINT_2_BANK(pint_val);
34e0fc89 682
8baf560b
MH		 683 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
684 if (pint[bank]->invert_set & pintbit)
685 pint[bank]->invert_clear = pintbit;
686 else
687 pint[bank]->invert_set = pintbit;
688 }
689
e3f23000
MH		 690 pint[bank]->request = pintbit;
691 pint[bank]->mask_clear = pintbit;
34e0fc89
MH		 692 SSYNC();
693}
694
695static void bfin_gpio_mask_irq(unsigned int irq)
696{
697 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
698
699 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
700 SSYNC();
701}
702
703static void bfin_gpio_unmask_irq(unsigned int irq)
704{
705 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 706 u32 pintbit = PINT_BIT(pint_val);
707 u8 bank = PINT_2_BANK(pint_val);
34e0fc89 708
e3f23000
MH		 709 pint[bank]->request = pintbit;
710 pint[bank]->mask_set = pintbit;
34e0fc89
MH		 711 SSYNC();
712}
713
714static unsigned int bfin_gpio_irq_startup(unsigned int irq)
715{
716 unsigned int ret;
6fce6a8d 717 char buf[8];
8baf560b 718 u16 gpionr = irq_to_gpio(irq);
34e0fc89
MH		 719 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
720
50e163ce
MH		 721 if (pint_val == IRQ_NOT_AVAIL) {
722 printk(KERN_ERR
723 "GPIO IRQ %d :Not in PINT Assign table "
724 "Reconfigure Interrupt to Port Assignemt\n", irq);
34e0fc89 725 return -ENODEV;
50e163ce 726 }
34e0fc89
MH		 727
728 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
6fce6a8d
MH		 729 snprintf(buf, sizeof buf, "IRQ %d", irq);
730 ret = gpio_request(gpionr, buf);
34e0fc89
MH		 731 if (ret)
732 return ret;
733 }
734
735 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
736 bfin_gpio_unmask_irq(irq);
737
738 return ret;
739}
740
741static void bfin_gpio_irq_shutdown(unsigned int irq)
742{
8baf560b
MH		 743 u16 gpionr = irq_to_gpio(irq);
744
34e0fc89 745 bfin_gpio_mask_irq(irq);
8baf560b
MH		 746 gpio_free(gpionr);
747 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
34e0fc89
MH		 748}
749
750static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
751{
752
753 unsigned int ret;
6fce6a8d 754 char buf[8];
8baf560b 755 u16 gpionr = irq_to_gpio(irq);
34e0fc89 756 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 757 u32 pintbit = PINT_BIT(pint_val);
758 u8 bank = PINT_2_BANK(pint_val);
34e0fc89
MH		 759
760 if (pint_val == IRQ_NOT_AVAIL)
761 return -ENODEV;
762
763 if (type == IRQ_TYPE_PROBE) {
764 /* only probe unenabled GPIO interrupt lines */
765 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
766 return 0;
767 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
768 }
769
770 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
771 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
772 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
6fce6a8d
MH		 773 snprintf(buf, sizeof buf, "IRQ %d", irq);
774 ret = gpio_request(gpionr, buf);
34e0fc89
MH		 775 if (ret)
776 return ret;
777 }
778
779 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
780 } else {
781 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
782 return 0;
783 }
784
785 gpio_direction_input(gpionr);
786
34e0fc89 787 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
e3f23000 788 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
34e0fc89 789 else
8baf560b 790 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
34e0fc89 791
8baf560b
MH		 792 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
793 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
34e0fc89 794
8baf560b 795 gpio_both_edge_triggered[bank] |= pintbit;
34e0fc89 796
8baf560b
MH		 797 if (gpio_get_value(gpionr))
798 pint[bank]->invert_set = pintbit;
799 else
800 pint[bank]->invert_clear = pintbit;
801 } else {
802 gpio_both_edge_triggered[bank] &= ~pintbit;
803 }
804
805 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
806 pint[bank]->edge_set = pintbit;
34e0fc89 807 set_irq_handler(irq, handle_edge_irq);
8baf560b
MH		 808 } else {
809 pint[bank]->edge_clear = pintbit;
34e0fc89 810 set_irq_handler(irq, handle_level_irq);
8baf560b
MH		 811 }
812
813 SSYNC();
34e0fc89
MH		 814
815 return 0;
816}
817
cfefe3c6
MH		 818#ifdef CONFIG_PM
819u32 pint_saved_masks[NR_PINT_SYS_IRQS];
820u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
821
822int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
823{
824 u32 pint_irq;
825 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
826 u32 bank = PINT_2_BANK(pint_val);
827 u32 pintbit = PINT_BIT(pint_val);
828
829 switch (bank) {
830 case 0:
831 pint_irq = IRQ_PINT0;
832 break;
833 case 2:
834 pint_irq = IRQ_PINT2;
835 break;
836 case 3:
837 pint_irq = IRQ_PINT3;
838 break;
839 case 1:
840 pint_irq = IRQ_PINT1;
841 break;
842 default:
843 return -EINVAL;
844 }
845
846 bfin_internal_set_wake(pint_irq, state);
847
848 if (state)
849 pint_wakeup_masks[bank] |= pintbit;
850 else
851 pint_wakeup_masks[bank] &= ~pintbit;
852
853 return 0;
854}
855
856u32 bfin_pm_setup(void)
857{
858 u32 val, i;
859
860 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
861 val = pint[i]->mask_clear;
862 pint_saved_masks[i] = val;
863 if (val ^ pint_wakeup_masks[i]) {
864 pint[i]->mask_clear = val;
865 pint[i]->mask_set = pint_wakeup_masks[i];
866 }
867 }
868
869 return 0;
870}
871
872void bfin_pm_restore(void)
873{
874 u32 i, val;
875
876 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
877 val = pint_saved_masks[i];
878 if (val ^ pint_wakeup_masks[i]) {
879 pint[i]->mask_clear = pint[i]->mask_clear;
880 pint[i]->mask_set = val;
881 }
882 }
883}
884#endif
885
34e0fc89
MH		 886static struct irq_chip bfin_gpio_irqchip = {
887 .ack = bfin_gpio_ack_irq,
888 .mask = bfin_gpio_mask_irq,
889 .mask_ack = bfin_gpio_mask_ack_irq,
890 .unmask = bfin_gpio_unmask_irq,
891 .set_type = bfin_gpio_irq_type,
892 .startup = bfin_gpio_irq_startup,
cfefe3c6
MH		 893 .shutdown = bfin_gpio_irq_shutdown,
894#ifdef CONFIG_PM
895 .set_wake = bfin_gpio_set_wake,
896#endif
34e0fc89
MH		 897};
898
2c4f829b
MH		 899static void bfin_demux_gpio_irq(unsigned int inta_irq,
900 struct irq_desc *desc)
34e0fc89
MH		 901{
902 u8 bank, pint_val;
903 u32 request, irq;
904
2c4f829b 905 switch (inta_irq) {
34e0fc89
MH		 906 case IRQ_PINT0:
907 bank = 0;
908 break;
909 case IRQ_PINT2:
910 bank = 2;
911 break;
912 case IRQ_PINT3:
913 bank = 3;
914 break;
915 case IRQ_PINT1:
916 bank = 1;
917 break;
e3f23000
MH		 918 default:
919 return;
34e0fc89
MH		 920 }
921
922 pint_val = bank * NR_PINT_BITS;
923
924 request = pint[bank]->request;
925
926 while (request) {
927 if (request & 1) {
e3f23000
MH		 928 irq = pint2irq_lut[pint_val] + SYS_IRQS;
929 desc = irq_desc + irq;
34e0fc89
MH		 930 desc->handle_irq(irq, desc);
931 }
932 pint_val++;
933 request >>= 1;
934 }
935
936}
a055b2b4 937#endif
1394f032 938
8be80ed3
BS		 939void __init init_exception_vectors(void)
940{
941 SSYNC();
942
f0b5d12f
MF		 943 /* cannot program in software:
944 * evt0 - emulation (jtag)
945 * evt1 - reset
946 */
947 bfin_write_EVT2(evt_nmi);
8be80ed3
BS		 948 bfin_write_EVT3(trap);
949 bfin_write_EVT5(evt_ivhw);
950 bfin_write_EVT6(evt_timer);
951 bfin_write_EVT7(evt_evt7);
952 bfin_write_EVT8(evt_evt8);
953 bfin_write_EVT9(evt_evt9);
954 bfin_write_EVT10(evt_evt10);
955 bfin_write_EVT11(evt_evt11);
956 bfin_write_EVT12(evt_evt12);
957 bfin_write_EVT13(evt_evt13);
958 bfin_write_EVT14(evt14_softirq);
959 bfin_write_EVT15(evt_system_call);
960 CSYNC();
961}
962
1394f032
BW		 963/*
964 * This function should be called during kernel startup to initialize
965 * the BFin IRQ handling routines.
966 */
967int __init init_arch_irq(void)
968{
969 int irq;
970 unsigned long ilat = 0;
971 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
2c4f829b 972#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
24a07a12
RH		 973 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
974 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
a055b2b4 975# ifdef CONFIG_BF54x
59003145 976 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
a055b2b4 977# endif
24a07a12 978#else
1394f032 979 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
24a07a12 980#endif
1394f032
BW		 981 SSYNC();
982
983 local_irq_disable();
984
2c4f829b
MH		 985 init_exception_buff();
986
a055b2b4
MF		 987#ifdef CONFIG_BF54x
988# ifdef CONFIG_PINTx_REASSIGN
34e0fc89
MH		 989 pint[0]->assign = CONFIG_PINT0_ASSIGN;
990 pint[1]->assign = CONFIG_PINT1_ASSIGN;
991 pint[2]->assign = CONFIG_PINT2_ASSIGN;
992 pint[3]->assign = CONFIG_PINT3_ASSIGN;
a055b2b4 993# endif
34e0fc89
MH		 994 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
995 init_pint_lut();
996#endif
997
998 for (irq = 0; irq <= SYS_IRQS; irq++) {
1394f032
BW		 999 if (irq <= IRQ_CORETMR)
1000 set_irq_chip(irq, &bfin_core_irqchip);
1001 else
1002 set_irq_chip(irq, &bfin_internal_irqchip);
1003#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1004 if (irq != IRQ_GENERIC_ERROR) {
1005#endif
1006
34e0fc89 1007 switch (irq) {
59003145 1008#if defined(CONFIG_BF53x)
34e0fc89
MH		 1009 case IRQ_PROG_INTA:
1010 set_irq_chained_handler(irq,
1011 bfin_demux_gpio_irq);
1012 break;
a055b2b4 1013# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
34e0fc89
MH		 1014 case IRQ_MAC_RX:
1015 set_irq_chained_handler(irq,
1016 bfin_demux_gpio_irq);
1017 break;
a055b2b4 1018# endif
59003145 1019#elif defined(CONFIG_BF54x)
34e0fc89 1020 case IRQ_PINT0:
1394f032
BW		 1021 set_irq_chained_handler(irq,
1022 bfin_demux_gpio_irq);
34e0fc89
MH		 1023 break;
1024 case IRQ_PINT1:
1025 set_irq_chained_handler(irq,
1026 bfin_demux_gpio_irq);
1027 break;
1028 case IRQ_PINT2:
1029 set_irq_chained_handler(irq,
1030 bfin_demux_gpio_irq);
1031 break;
1032 case IRQ_PINT3:
1033 set_irq_chained_handler(irq,
1034 bfin_demux_gpio_irq);
1035 break;
59003145
MH		 1036#elif defined(CONFIG_BF52x)
1037 case IRQ_PORTF_INTA:
1038 set_irq_chained_handler(irq,
1039 bfin_demux_gpio_irq);
1040 break;
1041 case IRQ_PORTG_INTA:
1042 set_irq_chained_handler(irq,
1043 bfin_demux_gpio_irq);
1044 break;
1045 case IRQ_PORTH_INTA:
1046 set_irq_chained_handler(irq,
1047 bfin_demux_gpio_irq);
1048 break;
2c4f829b
MH		 1049#elif defined(CONFIG_BF561)
1050 case IRQ_PROG0_INTA:
1051 set_irq_chained_handler(irq,
1052 bfin_demux_gpio_irq);
1053 break;
1054 case IRQ_PROG1_INTA:
1055 set_irq_chained_handler(irq,
1056 bfin_demux_gpio_irq);
1057 break;
1058 case IRQ_PROG2_INTA:
1059 set_irq_chained_handler(irq,
1060 bfin_demux_gpio_irq);
1061 break;
1394f032 1062#endif
34e0fc89
MH		 1063 default:
1064 set_irq_handler(irq, handle_simple_irq);
1065 break;
1066 }
1394f032
BW		 1067
1068#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1069 } else {
1070 set_irq_handler(irq, bfin_demux_error_irq);
1071 }
1072#endif
1073 }
1074#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1075 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) {
1076 set_irq_chip(irq, &bfin_generic_error_irqchip);
1077 set_irq_handler(irq, handle_level_irq);
1078 }
1079#endif
1080
2c4f829b
MH		 1081 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) {
1082
1394f032
BW		 1083 set_irq_chip(irq, &bfin_gpio_irqchip);
1084 /* if configured as edge, then will be changed to do_edge_IRQ */
1085 set_irq_handler(irq, handle_level_irq);
1086 }
a055b2b4 1087
1394f032
BW		 1088 bfin_write_IMASK(0);
1089 CSYNC();
1090 ilat = bfin_read_ILAT();
1091 CSYNC();
1092 bfin_write_ILAT(ilat);
1093 CSYNC();
1094
34e0fc89 1095 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1394f032
BW		 1096 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1097 * local_irq_enable()
1098 */
1099 program_IAR();
1100 /* Therefore it's better to setup IARs before interrupts enabled */
1101 search_IAR();
1102
1103 /* Enable interrupts IVG7-15 */
1104 irq_flags = irq_flags | IMASK_IVG15 |
1105 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
34e0fc89 1106 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1394f032 1107
fe9ec9b9
MH		 1108#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1109 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
1110 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
1111# ifdef CONFIG_BF54x
1112 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
1113# endif
1114#else
1115 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
1116#endif
1117
1394f032
BW		 1118 return 0;
1119}
1120
1121#ifdef CONFIG_DO_IRQ_L1
a055b2b4 1122__attribute__((l1_text))
1394f032 1123#endif
1394f032
BW		 1124void do_irq(int vec, struct pt_regs *fp)
1125{
1126 if (vec == EVT_IVTMR_P) {
1127 vec = IRQ_CORETMR;
1128 } else {
1129 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1130 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
2c4f829b 1131#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
24a07a12 1132 unsigned long sic_status[3];
1394f032 1133
24a07a12 1134 SSYNC();
4fb45241
MH		 1135 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1136 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
59003145 1137#ifdef CONFIG_BF54x
4fb45241 1138 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
59003145 1139#endif
1f83b8f1 1140 for (;; ivg++) {
24a07a12
RH		 1141 if (ivg >= ivg_stop) {
1142 atomic_inc(&num_spurious);
1143 return;
1144 }
34e0fc89 1145 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
24a07a12
RH		 1146 break;
1147 }
1148#else
1149 unsigned long sic_status;
1394f032
BW		 1150 SSYNC();
1151 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1152
1153 for (;; ivg++) {
1154 if (ivg >= ivg_stop) {
1155 atomic_inc(&num_spurious);
1156 return;
1157 } else if (sic_status & ivg->isrflag)
1158 break;
1159 }
24a07a12 1160#endif
1394f032
BW		 1161 vec = ivg->irqno;
1162 }
1163 asm_do_IRQ(vec, fp);
1164
1165#ifdef CONFIG_KGDB
1166 kgdb_process_breakpoint();
1167#endif
1168}
Linux kernel - Deliverables
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