Commit | Line | Data |
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1394f032 | 1 | /* |
96f1050d | 2 | * Blackfin power management |
1394f032 | 3 | * |
96f1050d | 4 | * Copyright 2006-2009 Analog Devices Inc. |
1394f032 | 5 | * |
96f1050d RG |
6 | * Licensed under the GPL-2 |
7 | * based on arm/mach-omap/pm.c | |
8 | * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others | |
1394f032 BW |
9 | */ |
10 | ||
95d9ffbe | 11 | #include <linux/suspend.h> |
1394f032 BW |
12 | #include <linux/sched.h> |
13 | #include <linux/proc_fs.h> | |
5a0e3ad6 | 14 | #include <linux/slab.h> |
1f83b8f1 MF |
15 | #include <linux/io.h> |
16 | #include <linux/irq.h> | |
1394f032 | 17 | |
eb7bd9c4 | 18 | #include <asm/cplb.h> |
fd92348e | 19 | #include <asm/gpio.h> |
1efc80b5 MH |
20 | #include <asm/dma.h> |
21 | #include <asm/dpmc.h> | |
93f89519 | 22 | #include <asm/pm.h> |
1394f032 | 23 | |
93f89519 SM |
24 | #ifdef CONFIG_BF60x |
25 | struct bfin_cpu_pm_fns *bfin_cpu_pm; | |
26 | #endif | |
1efc80b5 | 27 | |
1394f032 BW |
28 | void bfin_pm_suspend_standby_enter(void) |
29 | { | |
93f89519 | 30 | #ifndef CONFIG_BF60x |
1efc80b5 | 31 | bfin_pm_standby_setup(); |
93f89519 | 32 | #endif |
1394f032 | 33 | |
93f89519 SM |
34 | #ifdef CONFIG_BF60x |
35 | bfin_cpu_pm->enter(PM_SUSPEND_STANDBY); | |
fb5f0049 | 36 | #else |
93f89519 SM |
37 | # ifdef CONFIG_PM_BFIN_SLEEP_DEEPER |
38 | sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); | |
39 | # else | |
cfefe3c6 | 40 | sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); |
93f89519 | 41 | # endif |
fb5f0049 | 42 | #endif |
1394f032 | 43 | |
93f89519 | 44 | #ifndef CONFIG_BF60x |
1efc80b5 | 45 | bfin_pm_standby_restore(); |
93f89519 | 46 | #endif |
1394f032 | 47 | |
93f89519 | 48 | #ifndef CONFIG_BF60x |
be1d8543 | 49 | #ifdef SIC_IWR0 |
56f5f590 | 50 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
be1d8543 | 51 | # ifdef SIC_IWR1 |
55546ac4 MH |
52 | /* BF52x system reset does not properly reset SIC_IWR1 which |
53 | * will screw up the bootrom as it relies on MDMA0/1 waking it | |
54 | * up from IDLE instructions. See this report for more info: | |
55 | * http://blackfin.uclinux.org/gf/tracker/4323 | |
56 | */ | |
b7e11293 MF |
57 | if (ANOMALY_05000435) |
58 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); | |
59 | else | |
60 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | |
be1d8543 MF |
61 | # endif |
62 | # ifdef SIC_IWR2 | |
56f5f590 | 63 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); |
fb5f0049 | 64 | # endif |
cfefe3c6 | 65 | #else |
56f5f590 | 66 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
cfefe3c6 | 67 | #endif |
93f89519 SM |
68 | |
69 | #endif | |
1394f032 BW |
70 | } |
71 | ||
1efc80b5 MH |
72 | int bf53x_suspend_l1_mem(unsigned char *memptr) |
73 | { | |
d1401e1d MH |
74 | dma_memcpy_nocache(memptr, (const void *) L1_CODE_START, |
75 | L1_CODE_LENGTH); | |
76 | dma_memcpy_nocache(memptr + L1_CODE_LENGTH, | |
77 | (const void *) L1_DATA_A_START, L1_DATA_A_LENGTH); | |
78 | dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH, | |
1efc80b5 MH |
79 | (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH); |
80 | memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH + | |
81 | L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START, | |
82 | L1_SCRATCH_LENGTH); | |
83 | ||
84 | return 0; | |
85 | } | |
86 | ||
87 | int bf53x_resume_l1_mem(unsigned char *memptr) | |
88 | { | |
d1401e1d MH |
89 | dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH); |
90 | dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH, | |
1efc80b5 | 91 | L1_DATA_A_LENGTH); |
d1401e1d | 92 | dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH + |
1efc80b5 MH |
93 | L1_DATA_A_LENGTH, L1_DATA_B_LENGTH); |
94 | memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH + | |
95 | L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH); | |
96 | ||
97 | return 0; | |
98 | } | |
99 | ||
41ba653f | 100 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
93f89519 SM |
101 | # ifdef CONFIG_BF60x |
102 | __attribute__((l1_text)) | |
103 | # endif | |
1efc80b5 MH |
104 | static void flushinv_all_dcache(void) |
105 | { | |
93f89519 SM |
106 | register u32 way, bank, subbank, set; |
107 | register u32 status, addr; | |
1efc80b5 MH |
108 | u32 dmem_ctl = bfin_read_DMEM_CONTROL(); |
109 | ||
110 | for (bank = 0; bank < 2; ++bank) { | |
111 | if (!(dmem_ctl & (1 << (DMC1_P - bank)))) | |
112 | continue; | |
113 | ||
114 | for (way = 0; way < 2; ++way) | |
115 | for (subbank = 0; subbank < 4; ++subbank) | |
116 | for (set = 0; set < 64; ++set) { | |
117 | ||
118 | bfin_write_DTEST_COMMAND( | |
119 | way << 26 | | |
120 | bank << 23 | | |
121 | subbank << 16 | | |
122 | set << 5 | |
123 | ); | |
124 | CSYNC(); | |
125 | status = bfin_read_DTEST_DATA0(); | |
126 | ||
127 | /* only worry about valid/dirty entries */ | |
128 | if ((status & 0x3) != 0x3) | |
129 | continue; | |
130 | ||
131 | /* construct the address using the tag */ | |
132 | addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5); | |
133 | ||
134 | /* flush it */ | |
135 | __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr)); | |
136 | } | |
137 | } | |
138 | } | |
139 | #endif | |
140 | ||
1efc80b5 MH |
141 | int bfin_pm_suspend_mem_enter(void) |
142 | { | |
1efc80b5 MH |
143 | int wakeup, ret; |
144 | ||
145 | unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH | |
146 | + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH, | |
147 | GFP_KERNEL); | |
148 | ||
149 | if (memptr == NULL) { | |
150 | panic("bf53x_suspend_l1_mem malloc failed"); | |
151 | return -ENOMEM; | |
152 | } | |
153 | ||
93f89519 | 154 | #ifndef CONFIG_BF60x |
1efc80b5 MH |
155 | wakeup = bfin_read_VR_CTL() & ~FREQ; |
156 | wakeup |= SCKELOW; | |
157 | ||
1efc80b5 MH |
158 | #ifdef CONFIG_PM_BFIN_WAKE_PH6 |
159 | wakeup |= PHYWE; | |
160 | #endif | |
1efc80b5 MH |
161 | #ifdef CONFIG_PM_BFIN_WAKE_GP |
162 | wakeup |= GPWE; | |
0fbd88ca | 163 | #endif |
1efc80b5 | 164 | #endif |
1efc80b5 | 165 | |
1efc80b5 MH |
166 | ret = blackfin_dma_suspend(); |
167 | ||
168 | if (ret) { | |
1efc80b5 MH |
169 | kfree(memptr); |
170 | return ret; | |
171 | } | |
172 | ||
173 | bfin_gpio_pm_hibernate_suspend(); | |
174 | ||
d49cdf84 SM |
175 | bfin_pint_suspend(); |
176 | ||
eb7bd9c4 YL |
177 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
178 | flushinv_all_dcache(); | |
179 | #endif | |
180 | _disable_dcplb(); | |
181 | _disable_icplb(); | |
1efc80b5 MH |
182 | bf53x_suspend_l1_mem(memptr); |
183 | ||
93f89519 | 184 | #ifndef CONFIG_BF60x |
d1401e1d | 185 | do_hibernate(wakeup | vr_wakeup); /* See you later! */ |
93f89519 SM |
186 | #else |
187 | bfin_cpu_pm->enter(PM_SUSPEND_MEM); | |
188 | #endif | |
1efc80b5 MH |
189 | |
190 | bf53x_resume_l1_mem(memptr); | |
191 | ||
eb7bd9c4 YL |
192 | _enable_icplb(); |
193 | _enable_dcplb(); | |
1efc80b5 | 194 | |
d49cdf84 SM |
195 | bfin_pint_resume(); |
196 | ||
1efc80b5 MH |
197 | bfin_gpio_pm_hibernate_restore(); |
198 | blackfin_dma_resume(); | |
199 | ||
1efc80b5 MH |
200 | kfree(memptr); |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
1394f032 | 205 | /* |
e6c5eb95 RW |
206 | * bfin_pm_valid - Tell the PM core that we only support the standby sleep |
207 | * state | |
208 | * @state: suspend state we're checking. | |
1394f032 BW |
209 | * |
210 | */ | |
e6c5eb95 | 211 | static int bfin_pm_valid(suspend_state_t state) |
1394f032 | 212 | { |
1efc80b5 | 213 | return (state == PM_SUSPEND_STANDBY |
b89df504 | 214 | #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561)) |
1efc80b5 MH |
215 | /* |
216 | * On BF533/2/1: | |
217 | * If we enter Hibernate the SCKE Pin is driven Low, | |
218 | * so that the SDRAM enters Self Refresh Mode. | |
219 | * However when the reset sequence that follows hibernate | |
220 | * state is executed, SCKE is driven High, taking the | |
221 | * SDRAM out of Self Refresh. | |
222 | * | |
223 | * If you reconfigure and access the SDRAM "very quickly", | |
224 | * you are likely to avoid errors, otherwise the SDRAM | |
225 | * start losing its contents. | |
226 | * An external HW workaround is possible using logic gates. | |
227 | */ | |
228 | || state == PM_SUSPEND_MEM | |
229 | #endif | |
230 | ); | |
1394f032 BW |
231 | } |
232 | ||
233 | /* | |
234 | * bfin_pm_enter - Actually enter a sleep state. | |
235 | * @state: State we're entering. | |
236 | * | |
237 | */ | |
238 | static int bfin_pm_enter(suspend_state_t state) | |
239 | { | |
240 | switch (state) { | |
241 | case PM_SUSPEND_STANDBY: | |
242 | bfin_pm_suspend_standby_enter(); | |
243 | break; | |
9d7b6677 | 244 | case PM_SUSPEND_MEM: |
1efc80b5 MH |
245 | bfin_pm_suspend_mem_enter(); |
246 | break; | |
1394f032 BW |
247 | default: |
248 | return -EINVAL; | |
249 | } | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
72b099ed SZ |
254 | #ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH |
255 | void bfin_pm_end(void) | |
256 | { | |
257 | u32 cycle, cycle2; | |
258 | u64 usec64; | |
259 | u32 usec; | |
260 | ||
261 | __asm__ __volatile__ ( | |
262 | "1: %0 = CYCLES2\n" | |
263 | "%1 = CYCLES\n" | |
264 | "%2 = CYCLES2\n" | |
265 | "CC = %2 == %0\n" | |
266 | "if ! CC jump 1b\n" | |
267 | : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC" | |
268 | ); | |
269 | ||
270 | usec64 = ((u64)cycle2 << 32) + cycle; | |
271 | do_div(usec64, get_cclk() / USEC_PER_SEC); | |
272 | usec = usec64; | |
273 | if (usec == 0) | |
274 | usec = 1; | |
275 | ||
276 | pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n", | |
277 | usec / USEC_PER_MSEC, usec % USEC_PER_MSEC); | |
278 | } | |
279 | #endif | |
280 | ||
2f55ac07 | 281 | static const struct platform_suspend_ops bfin_pm_ops = { |
1394f032 | 282 | .enter = bfin_pm_enter, |
4bbd10fd | 283 | .valid = bfin_pm_valid, |
72b099ed SZ |
284 | #ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH |
285 | .end = bfin_pm_end, | |
286 | #endif | |
1394f032 BW |
287 | }; |
288 | ||
289 | static int __init bfin_pm_init(void) | |
290 | { | |
26398a70 | 291 | suspend_set_ops(&bfin_pm_ops); |
1394f032 BW |
292 | return 0; |
293 | } | |
294 | ||
295 | __initcall(bfin_pm_init); |