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1394f032 BW |
1 | /* |
2 | * File: arch/blackfin/mach-common/pm.c | |
3 | * Based on: arm/mach-omap/pm.c | |
4 | * Author: Cliff Brake <cbrake@accelent.com> Copyright (c) 2001 | |
5 | * | |
6 | * Created: 2001 | |
cfefe3c6 | 7 | * Description: Blackfin power management |
1394f032 BW |
8 | * |
9 | * Modified: Nicolas Pitre - PXA250 support | |
10 | * Copyright (c) 2002 Monta Vista Software, Inc. | |
11 | * David Singleton - OMAP1510 | |
12 | * Copyright (c) 2002 Monta Vista Software, Inc. | |
13 | * Dirk Behme <dirk.behme@de.bosch.com> - OMAP1510/1610 | |
14 | * Copyright 2004 | |
cfefe3c6 | 15 | * Copyright 2004-2008 Analog Devices Inc. |
1394f032 BW |
16 | * |
17 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or modify | |
20 | * it under the terms of the GNU General Public License as published by | |
21 | * the Free Software Foundation; either version 2 of the License, or | |
22 | * (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, see the file COPYING, or write | |
31 | * to the Free Software Foundation, Inc., | |
32 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
33 | */ | |
34 | ||
95d9ffbe | 35 | #include <linux/suspend.h> |
1394f032 BW |
36 | #include <linux/sched.h> |
37 | #include <linux/proc_fs.h> | |
1f83b8f1 MF |
38 | #include <linux/io.h> |
39 | #include <linux/irq.h> | |
1394f032 | 40 | |
eb7bd9c4 | 41 | #include <asm/cplb.h> |
fd92348e | 42 | #include <asm/gpio.h> |
1efc80b5 MH |
43 | #include <asm/dma.h> |
44 | #include <asm/dpmc.h> | |
1394f032 BW |
45 | |
46 | #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H | |
47 | #define WAKEUP_TYPE PM_WAKE_HIGH | |
48 | #endif | |
49 | ||
50 | #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_L | |
51 | #define WAKEUP_TYPE PM_WAKE_LOW | |
52 | #endif | |
53 | ||
54 | #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_F | |
55 | #define WAKEUP_TYPE PM_WAKE_FALLING | |
56 | #endif | |
57 | ||
58 | #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_R | |
59 | #define WAKEUP_TYPE PM_WAKE_RISING | |
60 | #endif | |
61 | ||
62 | #ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_B | |
63 | #define WAKEUP_TYPE PM_WAKE_BOTH_EDGES | |
64 | #endif | |
65 | ||
1efc80b5 | 66 | |
1394f032 BW |
67 | void bfin_pm_suspend_standby_enter(void) |
68 | { | |
1efc80b5 MH |
69 | unsigned long flags; |
70 | ||
1394f032 BW |
71 | #ifdef CONFIG_PM_WAKEUP_BY_GPIO |
72 | gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE); | |
73 | #endif | |
74 | ||
6a01f230 | 75 | local_irq_save_hw(flags); |
1efc80b5 | 76 | bfin_pm_standby_setup(); |
1394f032 | 77 | |
cfefe3c6 MH |
78 | #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER |
79 | sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); | |
fb5f0049 | 80 | #else |
cfefe3c6 | 81 | sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); |
fb5f0049 | 82 | #endif |
1394f032 | 83 | |
1efc80b5 | 84 | bfin_pm_standby_restore(); |
1394f032 | 85 | |
be1d8543 | 86 | #ifdef SIC_IWR0 |
56f5f590 | 87 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
be1d8543 | 88 | # ifdef SIC_IWR1 |
55546ac4 MH |
89 | /* BF52x system reset does not properly reset SIC_IWR1 which |
90 | * will screw up the bootrom as it relies on MDMA0/1 waking it | |
91 | * up from IDLE instructions. See this report for more info: | |
92 | * http://blackfin.uclinux.org/gf/tracker/4323 | |
93 | */ | |
b7e11293 MF |
94 | if (ANOMALY_05000435) |
95 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); | |
96 | else | |
97 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); | |
be1d8543 MF |
98 | # endif |
99 | # ifdef SIC_IWR2 | |
56f5f590 | 100 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); |
fb5f0049 | 101 | # endif |
cfefe3c6 | 102 | #else |
56f5f590 | 103 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
cfefe3c6 MH |
104 | #endif |
105 | ||
6a01f230 | 106 | local_irq_restore_hw(flags); |
1394f032 BW |
107 | } |
108 | ||
1efc80b5 MH |
109 | int bf53x_suspend_l1_mem(unsigned char *memptr) |
110 | { | |
111 | dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH); | |
112 | dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START, | |
113 | L1_DATA_A_LENGTH); | |
114 | dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH, | |
115 | (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH); | |
116 | memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH + | |
117 | L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START, | |
118 | L1_SCRATCH_LENGTH); | |
119 | ||
120 | return 0; | |
121 | } | |
122 | ||
123 | int bf53x_resume_l1_mem(unsigned char *memptr) | |
124 | { | |
125 | dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH); | |
126 | dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH, | |
127 | L1_DATA_A_LENGTH); | |
128 | dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH + | |
129 | L1_DATA_A_LENGTH, L1_DATA_B_LENGTH); | |
130 | memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH + | |
131 | L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH); | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
41ba653f | 136 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
1efc80b5 MH |
137 | static void flushinv_all_dcache(void) |
138 | { | |
139 | u32 way, bank, subbank, set; | |
140 | u32 status, addr; | |
141 | u32 dmem_ctl = bfin_read_DMEM_CONTROL(); | |
142 | ||
143 | for (bank = 0; bank < 2; ++bank) { | |
144 | if (!(dmem_ctl & (1 << (DMC1_P - bank)))) | |
145 | continue; | |
146 | ||
147 | for (way = 0; way < 2; ++way) | |
148 | for (subbank = 0; subbank < 4; ++subbank) | |
149 | for (set = 0; set < 64; ++set) { | |
150 | ||
151 | bfin_write_DTEST_COMMAND( | |
152 | way << 26 | | |
153 | bank << 23 | | |
154 | subbank << 16 | | |
155 | set << 5 | |
156 | ); | |
157 | CSYNC(); | |
158 | status = bfin_read_DTEST_DATA0(); | |
159 | ||
160 | /* only worry about valid/dirty entries */ | |
161 | if ((status & 0x3) != 0x3) | |
162 | continue; | |
163 | ||
164 | /* construct the address using the tag */ | |
165 | addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5); | |
166 | ||
167 | /* flush it */ | |
168 | __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr)); | |
169 | } | |
170 | } | |
171 | } | |
172 | #endif | |
173 | ||
1efc80b5 MH |
174 | int bfin_pm_suspend_mem_enter(void) |
175 | { | |
176 | unsigned long flags; | |
177 | int wakeup, ret; | |
178 | ||
179 | unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH | |
180 | + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH, | |
181 | GFP_KERNEL); | |
182 | ||
183 | if (memptr == NULL) { | |
184 | panic("bf53x_suspend_l1_mem malloc failed"); | |
185 | return -ENOMEM; | |
186 | } | |
187 | ||
188 | wakeup = bfin_read_VR_CTL() & ~FREQ; | |
189 | wakeup |= SCKELOW; | |
190 | ||
1efc80b5 MH |
191 | #ifdef CONFIG_PM_BFIN_WAKE_PH6 |
192 | wakeup |= PHYWE; | |
193 | #endif | |
1efc80b5 MH |
194 | #ifdef CONFIG_PM_BFIN_WAKE_GP |
195 | wakeup |= GPWE; | |
196 | #endif | |
1efc80b5 | 197 | |
6a01f230 | 198 | local_irq_save_hw(flags); |
1efc80b5 MH |
199 | |
200 | ret = blackfin_dma_suspend(); | |
201 | ||
202 | if (ret) { | |
6a01f230 | 203 | local_irq_restore_hw(flags); |
1efc80b5 MH |
204 | kfree(memptr); |
205 | return ret; | |
206 | } | |
207 | ||
208 | bfin_gpio_pm_hibernate_suspend(); | |
209 | ||
eb7bd9c4 YL |
210 | #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) |
211 | flushinv_all_dcache(); | |
212 | #endif | |
213 | _disable_dcplb(); | |
214 | _disable_icplb(); | |
1efc80b5 MH |
215 | bf53x_suspend_l1_mem(memptr); |
216 | ||
4a88d0ce | 217 | do_hibernate(wakeup | vr_wakeup); /* Goodbye */ |
1efc80b5 MH |
218 | |
219 | bf53x_resume_l1_mem(memptr); | |
220 | ||
eb7bd9c4 YL |
221 | _enable_icplb(); |
222 | _enable_dcplb(); | |
1efc80b5 MH |
223 | |
224 | bfin_gpio_pm_hibernate_restore(); | |
225 | blackfin_dma_resume(); | |
226 | ||
6a01f230 | 227 | local_irq_restore_hw(flags); |
1efc80b5 MH |
228 | kfree(memptr); |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
1394f032 | 233 | /* |
e6c5eb95 RW |
234 | * bfin_pm_valid - Tell the PM core that we only support the standby sleep |
235 | * state | |
236 | * @state: suspend state we're checking. | |
1394f032 BW |
237 | * |
238 | */ | |
e6c5eb95 | 239 | static int bfin_pm_valid(suspend_state_t state) |
1394f032 | 240 | { |
1efc80b5 | 241 | return (state == PM_SUSPEND_STANDBY |
b89df504 | 242 | #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561)) |
1efc80b5 MH |
243 | /* |
244 | * On BF533/2/1: | |
245 | * If we enter Hibernate the SCKE Pin is driven Low, | |
246 | * so that the SDRAM enters Self Refresh Mode. | |
247 | * However when the reset sequence that follows hibernate | |
248 | * state is executed, SCKE is driven High, taking the | |
249 | * SDRAM out of Self Refresh. | |
250 | * | |
251 | * If you reconfigure and access the SDRAM "very quickly", | |
252 | * you are likely to avoid errors, otherwise the SDRAM | |
253 | * start losing its contents. | |
254 | * An external HW workaround is possible using logic gates. | |
255 | */ | |
256 | || state == PM_SUSPEND_MEM | |
257 | #endif | |
258 | ); | |
1394f032 BW |
259 | } |
260 | ||
261 | /* | |
262 | * bfin_pm_enter - Actually enter a sleep state. | |
263 | * @state: State we're entering. | |
264 | * | |
265 | */ | |
266 | static int bfin_pm_enter(suspend_state_t state) | |
267 | { | |
268 | switch (state) { | |
269 | case PM_SUSPEND_STANDBY: | |
270 | bfin_pm_suspend_standby_enter(); | |
271 | break; | |
9d7b6677 | 272 | case PM_SUSPEND_MEM: |
1efc80b5 MH |
273 | bfin_pm_suspend_mem_enter(); |
274 | break; | |
1394f032 BW |
275 | default: |
276 | return -EINVAL; | |
277 | } | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
26398a70 | 282 | struct platform_suspend_ops bfin_pm_ops = { |
1394f032 | 283 | .enter = bfin_pm_enter, |
4bbd10fd | 284 | .valid = bfin_pm_valid, |
1394f032 BW |
285 | }; |
286 | ||
287 | static int __init bfin_pm_init(void) | |
288 | { | |
26398a70 | 289 | suspend_set_ops(&bfin_pm_ops); |
1394f032 BW |
290 | return 0; |
291 | } | |
292 | ||
293 | __initcall(bfin_pm_init); |