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51533b61 MS |
1 | #ifndef __ASM_ARCH_SPINLOCK_H |
2 | #define __ASM_ARCH_SPINLOCK_H | |
3 | ||
de1c1419 | 4 | #include <linux/spinlock_types.h> |
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5 | |
6 | #define RW_LOCK_BIAS 0x01000000 | |
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7 | |
8 | extern void cris_spin_unlock(void *l, int val); | |
9 | extern void cris_spin_lock(void *l); | |
de1c1419 | 10 | extern int cris_spin_trylock(void *l); |
51533b61 | 11 | |
445c8951 | 12 | static inline int __raw_spin_is_locked(arch_spinlock_t *x) |
de1c1419 JN |
13 | { |
14 | return *(volatile signed char *)(&(x)->slock) <= 0; | |
15 | } | |
16 | ||
445c8951 | 17 | static inline void __raw_spin_unlock(arch_spinlock_t *lock) |
51533b61 MS |
18 | { |
19 | __asm__ volatile ("move.d %1,%0" \ | |
de1c1419 | 20 | : "=m" (lock->slock) \ |
51533b61 MS |
21 | : "r" (1) \ |
22 | : "memory"); | |
23 | } | |
24 | ||
445c8951 | 25 | static inline void __raw_spin_unlock_wait(arch_spinlock_t *lock) |
de1c1419 JN |
26 | { |
27 | while (__raw_spin_is_locked(lock)) | |
28 | cpu_relax(); | |
29 | } | |
30 | ||
445c8951 | 31 | static inline int __raw_spin_trylock(arch_spinlock_t *lock) |
51533b61 | 32 | { |
de1c1419 | 33 | return cris_spin_trylock((void *)&lock->slock); |
51533b61 MS |
34 | } |
35 | ||
445c8951 | 36 | static inline void __raw_spin_lock(arch_spinlock_t *lock) |
51533b61 | 37 | { |
de1c1419 | 38 | cris_spin_lock((void *)&lock->slock); |
51533b61 MS |
39 | } |
40 | ||
de1c1419 | 41 | static inline void |
445c8951 | 42 | __raw_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags) |
51533b61 | 43 | { |
de1c1419 | 44 | __raw_spin_lock(lock); |
51533b61 MS |
45 | } |
46 | ||
47 | /* | |
48 | * Read-write spinlocks, allowing multiple readers | |
49 | * but only one writer. | |
50 | * | |
51 | * NOTE! it is quite common to have readers in interrupts | |
52 | * but no interrupt writers. For those circumstances we | |
53 | * can "mix" irq-safe locks - any writer needs to get a | |
54 | * irq-safe write-lock, but readers can get non-irqsafe | |
55 | * read-locks. | |
de1c1419 | 56 | * |
51533b61 | 57 | */ |
51533b61 | 58 | |
de1c1419 | 59 | static inline int __raw_read_can_lock(raw_rwlock_t *x) |
51533b61 | 60 | { |
de1c1419 | 61 | return (int)(x)->lock > 0; |
51533b61 MS |
62 | } |
63 | ||
de1c1419 | 64 | static inline int __raw_write_can_lock(raw_rwlock_t *x) |
51533b61 | 65 | { |
de1c1419 | 66 | return (x)->lock == RW_LOCK_BIAS; |
51533b61 MS |
67 | } |
68 | ||
de1c1419 | 69 | static inline void __raw_read_lock(raw_rwlock_t *rw) |
51533b61 | 70 | { |
de1c1419 JN |
71 | __raw_spin_lock(&rw->slock); |
72 | while (rw->lock == 0); | |
73 | rw->lock--; | |
74 | __raw_spin_unlock(&rw->slock); | |
51533b61 MS |
75 | } |
76 | ||
de1c1419 | 77 | static inline void __raw_write_lock(raw_rwlock_t *rw) |
51533b61 | 78 | { |
de1c1419 JN |
79 | __raw_spin_lock(&rw->slock); |
80 | while (rw->lock != RW_LOCK_BIAS); | |
b0903ee8 | 81 | rw->lock = 0; |
de1c1419 | 82 | __raw_spin_unlock(&rw->slock); |
51533b61 MS |
83 | } |
84 | ||
de1c1419 | 85 | static inline void __raw_read_unlock(raw_rwlock_t *rw) |
51533b61 | 86 | { |
de1c1419 JN |
87 | __raw_spin_lock(&rw->slock); |
88 | rw->lock++; | |
89 | __raw_spin_unlock(&rw->slock); | |
90 | } | |
51533b61 | 91 | |
de1c1419 JN |
92 | static inline void __raw_write_unlock(raw_rwlock_t *rw) |
93 | { | |
94 | __raw_spin_lock(&rw->slock); | |
95 | while (rw->lock != RW_LOCK_BIAS); | |
b0903ee8 | 96 | rw->lock = RW_LOCK_BIAS; |
de1c1419 | 97 | __raw_spin_unlock(&rw->slock); |
51533b61 MS |
98 | } |
99 | ||
de1c1419 | 100 | static inline int __raw_read_trylock(raw_rwlock_t *rw) |
51533b61 | 101 | { |
de1c1419 JN |
102 | int ret = 0; |
103 | __raw_spin_lock(&rw->slock); | |
104 | if (rw->lock != 0) { | |
105 | rw->lock--; | |
106 | ret = 1; | |
107 | } | |
108 | __raw_spin_unlock(&rw->slock); | |
109 | return ret; | |
51533b61 MS |
110 | } |
111 | ||
de1c1419 | 112 | static inline int __raw_write_trylock(raw_rwlock_t *rw) |
51533b61 | 113 | { |
de1c1419 JN |
114 | int ret = 0; |
115 | __raw_spin_lock(&rw->slock); | |
116 | if (rw->lock == RW_LOCK_BIAS) { | |
b0903ee8 | 117 | rw->lock = 0; |
de1c1419 JN |
118 | ret = 1; |
119 | } | |
120 | __raw_spin_unlock(&rw->slock); | |
121 | return 1; | |
51533b61 MS |
122 | } |
123 | ||
f5f7eac4 RH |
124 | #define _raw_read_lock_flags(lock, flags) _raw_read_lock(lock) |
125 | #define _raw_write_lock_flags(lock, flags) _raw_write_lock(lock) | |
de1c1419 | 126 | |
ef6edc97 MS |
127 | #define _raw_spin_relax(lock) cpu_relax() |
128 | #define _raw_read_relax(lock) cpu_relax() | |
129 | #define _raw_write_relax(lock) cpu_relax() | |
130 | ||
51533b61 | 131 | #endif /* __ASM_ARCH_SPINLOCK_H */ |