[PATCH] x86-64: Speed and clean up cache flushing in change_page_attr
[deliverable/linux.git] / arch / i386 / kernel / cpu / proc.c
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1da177e4
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1#include <linux/smp.h>
2#include <linux/timex.h>
3#include <linux/string.h>
4#include <asm/semaphore.h>
5#include <linux/seq_file.h>
95235ca2 6#include <linux/cpufreq.h>
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7
8/*
9 * Get CPU information for use by the procfs.
10 */
11static int show_cpuinfo(struct seq_file *m, void *v)
12{
13 /*
14 * These flag bits must match the definitions in <asm/cpufeature.h>.
15 * NULL means this bit is undefined or reserved; either way it doesn't
16 * have meaning as far as Linux is concerned. Note that it's important
17 * to realize there is a difference between this table and CPUID -- if
18 * applications want to get the raw CPUID data, they should access
19 * /dev/cpu/<cpu_nr>/cpuid instead.
20 */
7f35bf92 21 static const char * const x86_cap_flags[] = {
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22 /* Intel-defined */
23 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
24 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
25 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
26 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
27
28 /* AMD-defined */
3c3b73b6 29 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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30 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
31 NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL,
3f98bc49 32 NULL, "fxsr_opt", "rdtscp", NULL, NULL, "lm", "3dnowext", "3dnow",
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33
34 /* Transmeta-defined */
35 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
36 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
37 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
38 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
39
40 /* Other (Linux-defined) */
41 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
42 NULL, NULL, NULL, NULL,
9a0b5817 43 "constant_tsc", "up", NULL, NULL, NULL, NULL, NULL, NULL,
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44 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
45 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
46
47 /* Intel-defined (#2) */
9d95dd84 48 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
dcf10307
DJ
49 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
50 NULL, NULL, "dca", NULL, NULL, NULL, NULL, NULL,
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51 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
52
53 /* VIA/Cyrix/Centaur-defined */
54 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
224f611c 55 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
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56 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
57 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
58
59 /* AMD-defined (#2) */
3f98bc49 60 "lahf_lm", "cmp_legacy", "svm", NULL, "cr8legacy", NULL, NULL, NULL,
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61 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
62 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
63 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
64 };
7f35bf92 65 static const char * const x86_power_flags[] = {
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66 "ts", /* temperature sensor */
67 "fid", /* frequency id control */
68 "vid", /* voltage id control */
69 "ttp", /* thermal trip */
70 "tm",
71 "stc",
72 NULL,
73 /* nothing */ /* constant_tsc - moved to flags */
74 };
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75 struct cpuinfo_x86 *c = v;
76 int i, n = c - cpu_data;
77 int fpu_exception;
78
79#ifdef CONFIG_SMP
80 if (!cpu_online(n))
81 return 0;
82#endif
83 seq_printf(m, "processor\t: %d\n"
84 "vendor_id\t: %s\n"
85 "cpu family\t: %d\n"
86 "model\t\t: %d\n"
87 "model name\t: %s\n",
88 n,
89 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
90 c->x86,
91 c->x86_model,
92 c->x86_model_id[0] ? c->x86_model_id : "unknown");
93
94 if (c->x86_mask || c->cpuid_level >= 0)
95 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
96 else
97 seq_printf(m, "stepping\t: unknown\n");
98
99 if ( cpu_has(c, X86_FEATURE_TSC) ) {
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100 unsigned int freq = cpufreq_quick_get(n);
101 if (!freq)
102 freq = cpu_khz;
a3a255e7 103 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
95235ca2 104 freq / 1000, (freq % 1000));
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105 }
106
107 /* Cache size */
108 if (c->x86_cache_size >= 0)
109 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
110#ifdef CONFIG_X86_HT
94605eff 111 if (c->x86_max_cores * smp_num_siblings > 1) {
4b89aff9 112 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
94605eff 113 seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[n]));
4b89aff9 114 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
94605eff 115 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
db468681 116 }
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117#endif
118
119 /* We use exception 16 if we have hardware math and we've either seen it or the CPU claims it is internal */
120 fpu_exception = c->hard_math && (ignore_fpu_irq || cpu_has_fpu);
121 seq_printf(m, "fdiv_bug\t: %s\n"
122 "hlt_bug\t\t: %s\n"
123 "f00f_bug\t: %s\n"
124 "coma_bug\t: %s\n"
125 "fpu\t\t: %s\n"
126 "fpu_exception\t: %s\n"
127 "cpuid level\t: %d\n"
128 "wp\t\t: %s\n"
129 "flags\t\t:",
130 c->fdiv_bug ? "yes" : "no",
131 c->hlt_works_ok ? "no" : "yes",
132 c->f00f_bug ? "yes" : "no",
133 c->coma_bug ? "yes" : "no",
134 c->hard_math ? "yes" : "no",
135 fpu_exception ? "yes" : "no",
136 c->cpuid_level,
137 c->wp_works_ok ? "yes" : "no");
138
139 for ( i = 0 ; i < 32*NCAPINTS ; i++ )
140 if ( test_bit(i, c->x86_capability) &&
141 x86_cap_flags[i] != NULL )
142 seq_printf(m, " %s", x86_cap_flags[i]);
143
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144 for (i = 0; i < 32; i++)
145 if (c->x86_power & (1 << i)) {
146 if (i < ARRAY_SIZE(x86_power_flags) &&
147 x86_power_flags[i])
148 seq_printf(m, "%s%s",
149 x86_power_flags[i][0]?" ":"",
150 x86_power_flags[i]);
151 else
152 seq_printf(m, " [%d]", i);
153 }
154
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155 seq_printf(m, "\nbogomips\t: %lu.%02lu\n\n",
156 c->loops_per_jiffy/(500000/HZ),
157 (c->loops_per_jiffy/(5000/HZ)) % 100);
3dd9d514 158
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159 return 0;
160}
161
162static void *c_start(struct seq_file *m, loff_t *pos)
163{
164 return *pos < NR_CPUS ? cpu_data + *pos : NULL;
165}
166static void *c_next(struct seq_file *m, void *v, loff_t *pos)
167{
168 ++*pos;
169 return c_start(m, pos);
170}
171static void c_stop(struct seq_file *m, void *v)
172{
173}
174struct seq_operations cpuinfo_op = {
175 .start = c_start,
176 .next = c_next,
177 .stop = c_stop,
178 .show = show_cpuinfo,
179};
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