Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/i386/kernel/head.S -- the 32-bit startup code. | |
3 | * | |
4 | * Copyright (C) 1991, 1992 Linus Torvalds | |
5 | * | |
6 | * Enhanced CPU detection and feature setting code by Mike Jagdis | |
7 | * and Martin Mares, November 1997. | |
8 | */ | |
9 | ||
10 | .text | |
11 | #include <linux/config.h> | |
12 | #include <linux/threads.h> | |
13 | #include <linux/linkage.h> | |
14 | #include <asm/segment.h> | |
15 | #include <asm/page.h> | |
16 | #include <asm/pgtable.h> | |
17 | #include <asm/desc.h> | |
18 | #include <asm/cache.h> | |
19 | #include <asm/thread_info.h> | |
86feeaa8 | 20 | #include <asm/asm-offsets.h> |
1da177e4 LT |
21 | #include <asm/setup.h> |
22 | ||
23 | /* | |
24 | * References to members of the new_cpu_data structure. | |
25 | */ | |
26 | ||
27 | #define X86 new_cpu_data+CPUINFO_x86 | |
28 | #define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor | |
29 | #define X86_MODEL new_cpu_data+CPUINFO_x86_model | |
30 | #define X86_MASK new_cpu_data+CPUINFO_x86_mask | |
31 | #define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math | |
32 | #define X86_CPUID new_cpu_data+CPUINFO_cpuid_level | |
33 | #define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability | |
34 | #define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id | |
35 | ||
36 | /* | |
37 | * This is how much memory *in addition to the memory covered up to | |
38 | * and including _end* we need mapped initially. We need one bit for | |
39 | * each possible page, but only in low memory, which means | |
40 | * 2^32/4096/8 = 128K worst case (4G/4G split.) | |
41 | * | |
42 | * Modulo rounding, each megabyte assigned here requires a kilobyte of | |
43 | * memory, which is currently unreclaimed. | |
44 | * | |
45 | * This should be a multiple of a page. | |
46 | */ | |
47 | #define INIT_MAP_BEYOND_END (128*1024) | |
48 | ||
49 | ||
50 | /* | |
51 | * 32-bit kernel entrypoint; only used by the boot CPU. On entry, | |
52 | * %esi points to the real-mode code as a 32-bit pointer. | |
53 | * CS and DS must be 4 GB flat segments, but we don't depend on | |
54 | * any particular GDT layout, because we load our own as soon as we | |
55 | * can. | |
56 | */ | |
57 | ENTRY(startup_32) | |
58 | ||
59 | /* | |
60 | * Set segments to known values. | |
61 | */ | |
62 | cld | |
63 | lgdt boot_gdt_descr - __PAGE_OFFSET | |
64 | movl $(__BOOT_DS),%eax | |
65 | movl %eax,%ds | |
66 | movl %eax,%es | |
67 | movl %eax,%fs | |
68 | movl %eax,%gs | |
69 | ||
70 | /* | |
71 | * Clear BSS first so that there are no surprises... | |
72 | * No need to cld as DF is already clear from cld above... | |
73 | */ | |
74 | xorl %eax,%eax | |
75 | movl $__bss_start - __PAGE_OFFSET,%edi | |
76 | movl $__bss_stop - __PAGE_OFFSET,%ecx | |
77 | subl %edi,%ecx | |
78 | shrl $2,%ecx | |
79 | rep ; stosl | |
484b90c4 VG |
80 | /* |
81 | * Copy bootup parameters out of the way. | |
82 | * Note: %esi still has the pointer to the real-mode data. | |
83 | * With the kexec as boot loader, parameter segment might be loaded beyond | |
84 | * kernel image and might not even be addressable by early boot page tables. | |
85 | * (kexec on panic case). Hence copy out the parameters before initializing | |
86 | * page tables. | |
87 | */ | |
88 | movl $(boot_params - __PAGE_OFFSET),%edi | |
89 | movl $(PARAM_SIZE/4),%ecx | |
90 | cld | |
91 | rep | |
92 | movsl | |
93 | movl boot_params - __PAGE_OFFSET + NEW_CL_POINTER,%esi | |
94 | andl %esi,%esi | |
95 | jnz 2f # New command line protocol | |
96 | cmpw $(OLD_CL_MAGIC),OLD_CL_MAGIC_ADDR | |
97 | jne 1f | |
98 | movzwl OLD_CL_OFFSET,%esi | |
99 | addl $(OLD_CL_BASE_ADDR),%esi | |
100 | 2: | |
101 | movl $(saved_command_line - __PAGE_OFFSET),%edi | |
102 | movl $(COMMAND_LINE_SIZE/4),%ecx | |
103 | rep | |
104 | movsl | |
105 | 1: | |
1da177e4 LT |
106 | |
107 | /* | |
108 | * Initialize page tables. This creates a PDE and a set of page | |
109 | * tables, which are located immediately beyond _end. The variable | |
110 | * init_pg_tables_end is set up to point to the first "safe" location. | |
111 | * Mappings are created both at virtual address 0 (identity mapping) | |
112 | * and PAGE_OFFSET for up to _end+sizeof(page tables)+INIT_MAP_BEYOND_END. | |
113 | * | |
114 | * Warning: don't use %esi or the stack in this code. However, %esp | |
115 | * can be used as a GPR if you really need it... | |
116 | */ | |
117 | page_pde_offset = (__PAGE_OFFSET >> 20); | |
118 | ||
119 | movl $(pg0 - __PAGE_OFFSET), %edi | |
120 | movl $(swapper_pg_dir - __PAGE_OFFSET), %edx | |
121 | movl $0x007, %eax /* 0x007 = PRESENT+RW+USER */ | |
122 | 10: | |
123 | leal 0x007(%edi),%ecx /* Create PDE entry */ | |
124 | movl %ecx,(%edx) /* Store identity PDE entry */ | |
125 | movl %ecx,page_pde_offset(%edx) /* Store kernel PDE entry */ | |
126 | addl $4,%edx | |
127 | movl $1024, %ecx | |
128 | 11: | |
129 | stosl | |
130 | addl $0x1000,%eax | |
131 | loop 11b | |
132 | /* End condition: we must map up to and including INIT_MAP_BEYOND_END */ | |
133 | /* bytes beyond the end of our own page tables; the +0x007 is the attribute bits */ | |
134 | leal (INIT_MAP_BEYOND_END+0x007)(%edi),%ebp | |
135 | cmpl %ebp,%eax | |
136 | jb 10b | |
137 | movl %edi,(init_pg_tables_end - __PAGE_OFFSET) | |
138 | ||
139 | #ifdef CONFIG_SMP | |
140 | xorl %ebx,%ebx /* This is the boot CPU (BSP) */ | |
141 | jmp 3f | |
142 | ||
143 | /* | |
144 | * Non-boot CPU entry point; entered from trampoline.S | |
145 | * We can't lgdt here, because lgdt itself uses a data segment, but | |
146 | * we know the trampoline has already loaded the boot_gdt_table GDT | |
147 | * for us. | |
148 | */ | |
149 | ENTRY(startup_32_smp) | |
150 | cld | |
151 | movl $(__BOOT_DS),%eax | |
152 | movl %eax,%ds | |
153 | movl %eax,%es | |
154 | movl %eax,%fs | |
155 | movl %eax,%gs | |
156 | ||
157 | /* | |
158 | * New page tables may be in 4Mbyte page mode and may | |
159 | * be using the global pages. | |
160 | * | |
161 | * NOTE! If we are on a 486 we may have no cr4 at all! | |
162 | * So we do not try to touch it unless we really have | |
163 | * some bits in it to set. This won't work if the BSP | |
164 | * implements cr4 but this AP does not -- very unlikely | |
165 | * but be warned! The same applies to the pse feature | |
166 | * if not equally supported. --macro | |
167 | * | |
168 | * NOTE! We have to correct for the fact that we're | |
169 | * not yet offset PAGE_OFFSET.. | |
170 | */ | |
171 | #define cr4_bits mmu_cr4_features-__PAGE_OFFSET | |
172 | movl cr4_bits,%edx | |
173 | andl %edx,%edx | |
174 | jz 6f | |
175 | movl %cr4,%eax # Turn on paging options (PSE,PAE,..) | |
176 | orl %edx,%eax | |
177 | movl %eax,%cr4 | |
178 | ||
179 | btl $5, %eax # check if PAE is enabled | |
180 | jnc 6f | |
181 | ||
182 | /* Check if extended functions are implemented */ | |
183 | movl $0x80000000, %eax | |
184 | cpuid | |
185 | cmpl $0x80000000, %eax | |
186 | jbe 6f | |
187 | mov $0x80000001, %eax | |
188 | cpuid | |
189 | /* Execute Disable bit supported? */ | |
190 | btl $20, %edx | |
191 | jnc 6f | |
192 | ||
193 | /* Setup EFER (Extended Feature Enable Register) */ | |
194 | movl $0xc0000080, %ecx | |
195 | rdmsr | |
196 | ||
197 | btsl $11, %eax | |
198 | /* Make changes effective */ | |
199 | wrmsr | |
200 | ||
201 | 6: | |
202 | /* This is a secondary processor (AP) */ | |
203 | xorl %ebx,%ebx | |
204 | incl %ebx | |
205 | ||
206 | 3: | |
207 | #endif /* CONFIG_SMP */ | |
208 | ||
209 | /* | |
210 | * Enable paging | |
211 | */ | |
212 | movl $swapper_pg_dir-__PAGE_OFFSET,%eax | |
213 | movl %eax,%cr3 /* set the page table pointer.. */ | |
214 | movl %cr0,%eax | |
215 | orl $0x80000000,%eax | |
216 | movl %eax,%cr0 /* ..and set paging (PG) bit */ | |
217 | ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */ | |
218 | 1: | |
219 | /* Set up the stack pointer */ | |
220 | lss stack_start,%esp | |
221 | ||
222 | /* | |
223 | * Initialize eflags. Some BIOS's leave bits like NT set. This would | |
224 | * confuse the debugger if this code is traced. | |
225 | * XXX - best to initialize before switching to protected mode. | |
226 | */ | |
227 | pushl $0 | |
228 | popfl | |
229 | ||
230 | #ifdef CONFIG_SMP | |
231 | andl %ebx,%ebx | |
232 | jz 1f /* Initial CPU cleans BSS */ | |
233 | jmp checkCPUtype | |
234 | 1: | |
235 | #endif /* CONFIG_SMP */ | |
236 | ||
237 | /* | |
238 | * start system 32-bit setup. We need to re-do some of the things done | |
239 | * in 16-bit mode for the "real" operations. | |
240 | */ | |
241 | call setup_idt | |
242 | ||
1da177e4 LT |
243 | checkCPUtype: |
244 | ||
245 | movl $-1,X86_CPUID # -1 for no CPUID initially | |
246 | ||
247 | /* check if it is 486 or 386. */ | |
248 | /* | |
249 | * XXX - this does a lot of unnecessary setup. Alignment checks don't | |
250 | * apply at our cpl of 0 and the stack ought to be aligned already, and | |
251 | * we don't need to preserve eflags. | |
252 | */ | |
253 | ||
254 | movb $3,X86 # at least 386 | |
255 | pushfl # push EFLAGS | |
256 | popl %eax # get EFLAGS | |
257 | movl %eax,%ecx # save original EFLAGS | |
258 | xorl $0x240000,%eax # flip AC and ID bits in EFLAGS | |
259 | pushl %eax # copy to EFLAGS | |
260 | popfl # set EFLAGS | |
261 | pushfl # get new EFLAGS | |
262 | popl %eax # put it in eax | |
263 | xorl %ecx,%eax # change in flags | |
264 | pushl %ecx # restore original EFLAGS | |
265 | popfl | |
266 | testl $0x40000,%eax # check if AC bit changed | |
267 | je is386 | |
268 | ||
269 | movb $4,X86 # at least 486 | |
270 | testl $0x200000,%eax # check if ID bit changed | |
271 | je is486 | |
272 | ||
273 | /* get vendor info */ | |
274 | xorl %eax,%eax # call CPUID with 0 -> return vendor ID | |
275 | cpuid | |
276 | movl %eax,X86_CPUID # save CPUID level | |
277 | movl %ebx,X86_VENDOR_ID # lo 4 chars | |
278 | movl %edx,X86_VENDOR_ID+4 # next 4 chars | |
279 | movl %ecx,X86_VENDOR_ID+8 # last 4 chars | |
280 | ||
281 | orl %eax,%eax # do we have processor info as well? | |
282 | je is486 | |
283 | ||
284 | movl $1,%eax # Use the CPUID instruction to get CPU type | |
285 | cpuid | |
286 | movb %al,%cl # save reg for future use | |
287 | andb $0x0f,%ah # mask processor family | |
288 | movb %ah,X86 | |
289 | andb $0xf0,%al # mask model | |
290 | shrb $4,%al | |
291 | movb %al,X86_MODEL | |
292 | andb $0x0f,%cl # mask mask revision | |
293 | movb %cl,X86_MASK | |
294 | movl %edx,X86_CAPABILITY | |
295 | ||
296 | is486: movl $0x50022,%ecx # set AM, WP, NE and MP | |
297 | jmp 2f | |
298 | ||
299 | is386: movl $2,%ecx # set MP | |
300 | 2: movl %cr0,%eax | |
301 | andl $0x80000011,%eax # Save PG,PE,ET | |
302 | orl %ecx,%eax | |
303 | movl %eax,%cr0 | |
304 | ||
305 | call check_x87 | |
1da177e4 LT |
306 | lgdt cpu_gdt_descr |
307 | lidt idt_descr | |
308 | ljmp $(__KERNEL_CS),$1f | |
309 | 1: movl $(__KERNEL_DS),%eax # reload all the segment registers | |
310 | movl %eax,%ss # after changing gdt. | |
311 | ||
312 | movl $(__USER_DS),%eax # DS/ES contains default USER segment | |
313 | movl %eax,%ds | |
314 | movl %eax,%es | |
315 | ||
316 | xorl %eax,%eax # Clear FS/GS and LDT | |
317 | movl %eax,%fs | |
318 | movl %eax,%gs | |
319 | lldt %ax | |
320 | cld # gcc2 wants the direction flag cleared at all times | |
321 | #ifdef CONFIG_SMP | |
d92de65c SL |
322 | movb ready, %cl |
323 | movb $1, ready | |
324 | cmpb $0,%cl | |
1da177e4 LT |
325 | je 1f # the first CPU calls start_kernel |
326 | # all other CPUs call initialize_secondary | |
327 | call initialize_secondary | |
328 | jmp L6 | |
329 | 1: | |
330 | #endif /* CONFIG_SMP */ | |
331 | call start_kernel | |
332 | L6: | |
333 | jmp L6 # main should never return here, but | |
334 | # just in case, we know what happens. | |
335 | ||
336 | /* | |
337 | * We depend on ET to be correct. This checks for 287/387. | |
338 | */ | |
339 | check_x87: | |
340 | movb $0,X86_HARD_MATH | |
341 | clts | |
342 | fninit | |
343 | fstsw %ax | |
344 | cmpb $0,%al | |
345 | je 1f | |
346 | movl %cr0,%eax /* no coprocessor: have to set bits */ | |
347 | xorl $4,%eax /* set EM */ | |
348 | movl %eax,%cr0 | |
349 | ret | |
350 | ALIGN | |
351 | 1: movb $1,X86_HARD_MATH | |
352 | .byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */ | |
353 | ret | |
354 | ||
355 | /* | |
356 | * setup_idt | |
357 | * | |
358 | * sets up a idt with 256 entries pointing to | |
359 | * ignore_int, interrupt gates. It doesn't actually load | |
360 | * idt - that can be done only after paging has been enabled | |
361 | * and the kernel moved to PAGE_OFFSET. Interrupts | |
362 | * are enabled elsewhere, when we can be relatively | |
363 | * sure everything is ok. | |
364 | * | |
365 | * Warning: %esi is live across this function. | |
366 | */ | |
367 | setup_idt: | |
368 | lea ignore_int,%edx | |
369 | movl $(__KERNEL_CS << 16),%eax | |
370 | movw %dx,%ax /* selector = 0x0010 = cs */ | |
371 | movw $0x8E00,%dx /* interrupt gate - dpl=0, present */ | |
372 | ||
373 | lea idt_table,%edi | |
374 | mov $256,%ecx | |
375 | rp_sidt: | |
376 | movl %eax,(%edi) | |
377 | movl %edx,4(%edi) | |
378 | addl $8,%edi | |
379 | dec %ecx | |
380 | jne rp_sidt | |
381 | ret | |
382 | ||
383 | /* This is the default interrupt "handler" :-) */ | |
384 | ALIGN | |
385 | ignore_int: | |
386 | cld | |
d59745ce | 387 | #ifdef CONFIG_PRINTK |
1da177e4 LT |
388 | pushl %eax |
389 | pushl %ecx | |
390 | pushl %edx | |
391 | pushl %es | |
392 | pushl %ds | |
393 | movl $(__KERNEL_DS),%eax | |
394 | movl %eax,%ds | |
395 | movl %eax,%es | |
396 | pushl 16(%esp) | |
397 | pushl 24(%esp) | |
398 | pushl 32(%esp) | |
399 | pushl 40(%esp) | |
400 | pushl $int_msg | |
401 | call printk | |
402 | addl $(5*4),%esp | |
403 | popl %ds | |
404 | popl %es | |
405 | popl %edx | |
406 | popl %ecx | |
407 | popl %eax | |
d59745ce | 408 | #endif |
1da177e4 LT |
409 | iret |
410 | ||
411 | /* | |
412 | * Real beginning of normal "text" segment | |
413 | */ | |
414 | ENTRY(stext) | |
415 | ENTRY(_stext) | |
416 | ||
417 | /* | |
418 | * BSS section | |
419 | */ | |
420 | .section ".bss.page_aligned","w" | |
421 | ENTRY(swapper_pg_dir) | |
422 | .fill 1024,4,0 | |
423 | ENTRY(empty_zero_page) | |
424 | .fill 4096,1,0 | |
425 | ||
426 | /* | |
427 | * This starts the data section. | |
428 | */ | |
429 | .data | |
430 | ||
431 | ENTRY(stack_start) | |
432 | .long init_thread_union+THREAD_SIZE | |
433 | .long __BOOT_DS | |
434 | ||
435 | ready: .byte 0 | |
436 | ||
437 | int_msg: | |
438 | .asciz "Unknown interrupt or fault at EIP %p %p %p\n" | |
439 | ||
440 | /* | |
441 | * The IDT and GDT 'descriptors' are a strange 48-bit object | |
442 | * only used by the lidt and lgdt instructions. They are not | |
443 | * like usual segment descriptors - they consist of a 16-bit | |
444 | * segment size, and 32-bit linear address value: | |
445 | */ | |
446 | ||
447 | .globl boot_gdt_descr | |
448 | .globl idt_descr | |
449 | .globl cpu_gdt_descr | |
450 | ||
451 | ALIGN | |
452 | # early boot GDT descriptor (must use 1:1 address mapping) | |
453 | .word 0 # 32 bit align gdt_desc.address | |
454 | boot_gdt_descr: | |
455 | .word __BOOT_DS+7 | |
456 | .long boot_gdt_table - __PAGE_OFFSET | |
457 | ||
458 | .word 0 # 32-bit align idt_desc.address | |
459 | idt_descr: | |
460 | .word IDT_ENTRIES*8-1 # idt contains 256 entries | |
461 | .long idt_table | |
462 | ||
463 | # boot GDT descriptor (later on used by CPU#0): | |
464 | .word 0 # 32 bit align gdt_desc.address | |
465 | cpu_gdt_descr: | |
466 | .word GDT_ENTRIES*8-1 | |
467 | .long cpu_gdt_table | |
468 | ||
469 | .fill NR_CPUS-1,8,0 # space for the other GDT descriptors | |
470 | ||
471 | /* | |
472 | * The boot_gdt_table must mirror the equivalent in setup.S and is | |
473 | * used only for booting. | |
474 | */ | |
475 | .align L1_CACHE_BYTES | |
476 | ENTRY(boot_gdt_table) | |
477 | .fill GDT_ENTRY_BOOT_CS,8,0 | |
478 | .quad 0x00cf9a000000ffff /* kernel 4GB code at 0x00000000 */ | |
479 | .quad 0x00cf92000000ffff /* kernel 4GB data at 0x00000000 */ | |
480 | ||
481 | /* | |
482 | * The Global Descriptor Table contains 28 quadwords, per-CPU. | |
483 | */ | |
484 | .align PAGE_SIZE_asm | |
485 | ENTRY(cpu_gdt_table) | |
486 | .quad 0x0000000000000000 /* NULL descriptor */ | |
487 | .quad 0x0000000000000000 /* 0x0b reserved */ | |
488 | .quad 0x0000000000000000 /* 0x13 reserved */ | |
489 | .quad 0x0000000000000000 /* 0x1b reserved */ | |
490 | .quad 0x0000000000000000 /* 0x20 unused */ | |
491 | .quad 0x0000000000000000 /* 0x28 unused */ | |
492 | .quad 0x0000000000000000 /* 0x33 TLS entry 1 */ | |
493 | .quad 0x0000000000000000 /* 0x3b TLS entry 2 */ | |
494 | .quad 0x0000000000000000 /* 0x43 TLS entry 3 */ | |
495 | .quad 0x0000000000000000 /* 0x4b reserved */ | |
496 | .quad 0x0000000000000000 /* 0x53 reserved */ | |
497 | .quad 0x0000000000000000 /* 0x5b reserved */ | |
498 | ||
499 | .quad 0x00cf9a000000ffff /* 0x60 kernel 4GB code at 0x00000000 */ | |
500 | .quad 0x00cf92000000ffff /* 0x68 kernel 4GB data at 0x00000000 */ | |
501 | .quad 0x00cffa000000ffff /* 0x73 user 4GB code at 0x00000000 */ | |
502 | .quad 0x00cff2000000ffff /* 0x7b user 4GB data at 0x00000000 */ | |
503 | ||
504 | .quad 0x0000000000000000 /* 0x80 TSS descriptor */ | |
505 | .quad 0x0000000000000000 /* 0x88 LDT descriptor */ | |
506 | ||
e6a9918c ZA |
507 | /* |
508 | * Segments used for calling PnP BIOS have byte granularity. | |
509 | * They code segments and data segments have fixed 64k limits, | |
510 | * the transfer segment sizes are set at run time. | |
511 | */ | |
512 | .quad 0x00409a000000ffff /* 0x90 32-bit code */ | |
513 | .quad 0x00009a000000ffff /* 0x98 16-bit code */ | |
514 | .quad 0x000092000000ffff /* 0xa0 16-bit data */ | |
5fe9fe3c ZA |
515 | .quad 0x0000920000000000 /* 0xa8 16-bit data */ |
516 | .quad 0x0000920000000000 /* 0xb0 16-bit data */ | |
99022c46 | 517 | |
1da177e4 LT |
518 | /* |
519 | * The APM segments have byte granularity and their bases | |
99022c46 | 520 | * are set at run time. All have 64k limits. |
1da177e4 | 521 | */ |
99022c46 ZA |
522 | .quad 0x00409a000000ffff /* 0xb8 APM CS code */ |
523 | .quad 0x00009a000000ffff /* 0xc0 APM CS 16 code (16 bit) */ | |
524 | .quad 0x004092000000ffff /* 0xc8 APM DS data */ | |
1da177e4 LT |
525 | |
526 | .quad 0x0000920000000000 /* 0xd0 - ESPFIX 16-bit SS */ | |
527 | .quad 0x0000000000000000 /* 0xd8 - unused */ | |
528 | .quad 0x0000000000000000 /* 0xe0 - unused */ | |
529 | .quad 0x0000000000000000 /* 0xe8 - unused */ | |
530 | .quad 0x0000000000000000 /* 0xf0 - unused */ | |
531 | .quad 0x0000000000000000 /* 0xf8 - GDT entry 31: double-fault TSS */ | |
532 | ||
7c4cb60e ZA |
533 | /* Be sure this is zeroed to avoid false validations in Xen */ |
534 | .fill PAGE_SIZE_asm / 8 - GDT_ENTRIES,8,0 |