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[PATCH] menu: relocate DOUBLEFAULT option
[deliverable/linux.git] / arch / i386 / kernel / mpparse.c
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1da177e4
LT		 1/*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16#include <linux/mm.h>
1da177e4
LT		 17#include <linux/init.h>
18#include <linux/acpi.h>
19#include <linux/delay.h>
20#include <linux/config.h>
21#include <linux/bootmem.h>
22#include <linux/smp_lock.h>
23#include <linux/kernel_stat.h>
24#include <linux/mc146818rtc.h>
25#include <linux/bitops.h>
26
27#include <asm/smp.h>
28#include <asm/acpi.h>
29#include <asm/mtrr.h>
30#include <asm/mpspec.h>
31#include <asm/io_apic.h>
32
33#include <mach_apic.h>
34#include <mach_mpparse.h>
35#include <bios_ebda.h>
36
37/* Have we found an MP table */
38int smp_found_config;
39unsigned int __initdata maxcpus = NR_CPUS;
40
41/*
42 * Various Linux-internal data structures created from the
43 * MP-table.
44 */
45int apic_version [MAX_APICS];
46int mp_bus_id_to_type [MAX_MP_BUSSES];
47int mp_bus_id_to_node [MAX_MP_BUSSES];
48int mp_bus_id_to_local [MAX_MP_BUSSES];
49int quad_local_to_mp_bus_id [NR_CPUS/4][4];
50int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
51static int mp_current_pci_id;
52
53/* I/O APIC entries */
54struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
55
56/* # of MP IRQ source entries */
57struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
58
59/* MP IRQ source entries */
60int mp_irq_entries;
61
62int nr_ioapics;
63
64int pic_mode;
65unsigned long mp_lapic_addr;
66
911a62d4
VP		 67unsigned int def_to_bigsmp = 0;
68
1da177e4
LT		 69/* Processor that is doing the boot up */
70unsigned int boot_cpu_physical_apicid = -1U;
1da177e4 71/* Internal processor count */
9f40a72a 72static unsigned int __devinitdata num_processors;
1da177e4
LT		 73
74/* Bitmask of physically existing CPUs */
75physid_mask_t phys_cpu_present_map;
76
77u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
78
79/*
80 * Intel MP BIOS table parsing routines:
81 */
82
83
84/*
85 * Checksum an MP configuration block.
86 */
87
88static int __init mpf_checksum(unsigned char *mp, int len)
89{
90 int sum = 0;
91
92 while (len--)
93 sum += *mp++;
94
95 return sum & 0xFF;
96}
97
98/*
99 * Have to match translation table entries to main table entries by counter
100 * hence the mpc_record variable .... can't see a less disgusting way of
101 * doing this ....
102 */
103
104static int mpc_record;
105static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
106
9f40a72a 107static void __devinit MP_processor_info (struct mpc_config_processor *m)
1da177e4 108{
1299232b
AM		 109 int ver, apicid;
110 physid_mask_t phys_cpu;
1da177e4
LT		 111
112 if (!(m->mpc_cpuflag & CPU_ENABLED))
113 return;
114
115 apicid = mpc_apic_id(m, translation_table[mpc_record]);
116
117 if (m->mpc_featureflag&(1<<0))
118 Dprintk(" Floating point unit present.\n");
119 if (m->mpc_featureflag&(1<<7))
120 Dprintk(" Machine Exception supported.\n");
121 if (m->mpc_featureflag&(1<<8))
122 Dprintk(" 64 bit compare & exchange supported.\n");
123 if (m->mpc_featureflag&(1<<9))
124 Dprintk(" Internal APIC present.\n");
125 if (m->mpc_featureflag&(1<<11))
126 Dprintk(" SEP present.\n");
127 if (m->mpc_featureflag&(1<<12))
128 Dprintk(" MTRR present.\n");
129 if (m->mpc_featureflag&(1<<13))
130 Dprintk(" PGE present.\n");
131 if (m->mpc_featureflag&(1<<14))
132 Dprintk(" MCA present.\n");
133 if (m->mpc_featureflag&(1<<15))
134 Dprintk(" CMOV present.\n");
135 if (m->mpc_featureflag&(1<<16))
136 Dprintk(" PAT present.\n");
137 if (m->mpc_featureflag&(1<<17))
138 Dprintk(" PSE present.\n");
139 if (m->mpc_featureflag&(1<<18))
140 Dprintk(" PSN present.\n");
141 if (m->mpc_featureflag&(1<<19))
142 Dprintk(" Cache Line Flush Instruction present.\n");
143 /* 20 Reserved */
144 if (m->mpc_featureflag&(1<<21))
145 Dprintk(" Debug Trace and EMON Store present.\n");
146 if (m->mpc_featureflag&(1<<22))
147 Dprintk(" ACPI Thermal Throttle Registers present.\n");
148 if (m->mpc_featureflag&(1<<23))
149 Dprintk(" MMX present.\n");
150 if (m->mpc_featureflag&(1<<24))
151 Dprintk(" FXSR present.\n");
152 if (m->mpc_featureflag&(1<<25))
153 Dprintk(" XMM present.\n");
154 if (m->mpc_featureflag&(1<<26))
155 Dprintk(" Willamette New Instructions present.\n");
156 if (m->mpc_featureflag&(1<<27))
157 Dprintk(" Self Snoop present.\n");
158 if (m->mpc_featureflag&(1<<28))
159 Dprintk(" HT present.\n");
160 if (m->mpc_featureflag&(1<<29))
161 Dprintk(" Thermal Monitor present.\n");
162 /* 30, 31 Reserved */
163
164
165 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
166 Dprintk(" Bootup CPU\n");
167 boot_cpu_physical_apicid = m->mpc_apicid;
1da177e4
LT		 168 }
169
1da177e4
LT		 170 ver = m->mpc_apicver;
171
1da177e4
LT		 172 /*
173 * Validate version
174 */
175 if (ver == 0x0) {
1299232b
AM		 176 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
177 "fixing up to 0x10. (tell your hw vendor)\n",
178 m->mpc_apicid);
1da177e4
LT		 179 ver = 0x10;
180 }
181 apic_version[m->mpc_apicid] = ver;
6c180d94
EB		 182
183 phys_cpu = apicid_to_cpu_present(apicid);
184 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
185
186 if (num_processors >= NR_CPUS) {
187 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
188 " Processor ignored.\n", NR_CPUS);
189 return;
190 }
191
192 if (num_processors >= maxcpus) {
193 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
194 " Processor ignored.\n", maxcpus);
195 return;
196 }
197
198 cpu_set(num_processors, cpu_possible_map);
199 num_processors++;
200
6cf272ac
AR		 201 /*
202 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
203 * but we need to work other dependencies like SMP_SUSPEND etc
204 * before this can be done without some confusion.
205 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
206 * - Ashok Raj <ashok.raj@intel.com>
207 */
208 if (num_processors > 8) {
e72c8585
AR		 209 switch (boot_cpu_data.x86_vendor) {
210 case X86_VENDOR_INTEL:
211 if (!APIC_XAPIC(ver)) {
212 def_to_bigsmp = 0;
213 break;
214 }
215 /* If P4 and above fall through */
216 case X86_VENDOR_AMD:
217 def_to_bigsmp = 1;
218 }
219 }
1da177e4
LT		 220 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
221}
222
223static void __init MP_bus_info (struct mpc_config_bus *m)
224{
225 char str[7];
226
227 memcpy(str, m->mpc_bustype, 6);
228 str[6] = 0;
229
230 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
231
232 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
233 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
234 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
235 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
236 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
237 mpc_oem_pci_bus(m, translation_table[mpc_record]);
238 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
239 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
240 mp_current_pci_id++;
241 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
242 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
243 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
244 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
245 } else {
246 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
247 }
248}
249
250static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
251{
252 if (!(m->mpc_flags & MPC_APIC_USABLE))
253 return;
254
255 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
256 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
257 if (nr_ioapics >= MAX_IO_APICS) {
258 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
259 MAX_IO_APICS, nr_ioapics);
260 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
261 }
262 if (!m->mpc_apicaddr) {
263 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
264 " found in MP table, skipping!\n");
265 return;
266 }
267 mp_ioapics[nr_ioapics] = *m;
268 nr_ioapics++;
269}
270
271static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
272{
273 mp_irqs [mp_irq_entries] = *m;
274 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
275 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
276 m->mpc_irqtype, m->mpc_irqflag & 3,
277 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
278 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
279 if (++mp_irq_entries == MAX_IRQ_SOURCES)
280 panic("Max # of irq sources exceeded!!\n");
281}
282
283static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
284{
285 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
286 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
287 m->mpc_irqtype, m->mpc_irqflag & 3,
288 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
289 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
290 /*
291 * Well it seems all SMP boards in existence
292 * use ExtINT/LVT1 == LINT0 and
293 * NMI/LVT2 == LINT1 - the following check
294 * will show us if this assumptions is false.
295 * Until then we do not have to add baggage.
296 */
297 if ((m->mpc_irqtype == mp_ExtINT) &&
298 (m->mpc_destapiclint != 0))
299 BUG();
300 if ((m->mpc_irqtype == mp_NMI) &&
301 (m->mpc_destapiclint != 1))
302 BUG();
303}
304
305#ifdef CONFIG_X86_NUMAQ
306static void __init MP_translation_info (struct mpc_config_translation *m)
307{
308 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
309
310 if (mpc_record >= MAX_MPC_ENTRY)
311 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
312 else
313 translation_table[mpc_record] = m; /* stash this for later */
314 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
315 node_set_online(m->trans_quad);
316}
317
318/*
319 * Read/parse the MPC oem tables
320 */
321
322static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
323 unsigned short oemsize)
324{
325 int count = sizeof (*oemtable); /* the header size */
326 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
327
328 mpc_record = 0;
329 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
330 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
331 {
332 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
333 oemtable->oem_signature[0],
334 oemtable->oem_signature[1],
335 oemtable->oem_signature[2],
336 oemtable->oem_signature[3]);
337 return;
338 }
339 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
340 {
341 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
342 return;
343 }
344 while (count < oemtable->oem_length) {
345 switch (*oemptr) {
346 case MP_TRANSLATION:
347 {
348 struct mpc_config_translation *m=
349 (struct mpc_config_translation *)oemptr;
350 MP_translation_info(m);
351 oemptr += sizeof(*m);
352 count += sizeof(*m);
353 ++mpc_record;
354 break;
355 }
356 default:
357 {
358 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
359 return;
360 }
361 }
362 }
363}
364
365static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
366 char *productid)
367{
368 if (strncmp(oem, "IBM NUMA", 8))
369 printk("Warning! May not be a NUMA-Q system!\n");
370 if (mpc->mpc_oemptr)
371 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
372 mpc->mpc_oemsize);
373}
374#endif /* CONFIG_X86_NUMAQ */
375
376/*
377 * Read/parse the MPC
378 */
379
380static int __init smp_read_mpc(struct mp_config_table *mpc)
381{
382 char str[16];
383 char oem[10];
384 int count=sizeof(*mpc);
385 unsigned char *mpt=((unsigned char *)mpc)+count;
386
387 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
388 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
389 *(u32 *)mpc->mpc_signature);
390 return 0;
391 }
392 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
393 printk(KERN_ERR "SMP mptable: checksum error!\n");
394 return 0;
395 }
396 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
397 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
398 mpc->mpc_spec);
399 return 0;
400 }
401 if (!mpc->mpc_lapic) {
402 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
403 return 0;
404 }
405 memcpy(oem,mpc->mpc_oem,8);
406 oem[8]=0;
407 printk(KERN_INFO "OEM ID: %s ",oem);
408
409 memcpy(str,mpc->mpc_productid,12);
410 str[12]=0;
411 printk("Product ID: %s ",str);
412
413 mps_oem_check(mpc, oem, str);
414
415 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
416
417 /*
418 * Save the local APIC address (it might be non-default) -- but only
419 * if we're not using ACPI.
420 */
421 if (!acpi_lapic)
422 mp_lapic_addr = mpc->mpc_lapic;
423
424 /*
425 * Now process the configuration blocks.
426 */
427 mpc_record = 0;
428 while (count < mpc->mpc_length) {
429 switch(*mpt) {
430 case MP_PROCESSOR:
431 {
432 struct mpc_config_processor *m=
433 (struct mpc_config_processor *)mpt;
434 /* ACPI may have already provided this data */
435 if (!acpi_lapic)
436 MP_processor_info(m);
437 mpt += sizeof(*m);
438 count += sizeof(*m);
439 break;
440 }
441 case MP_BUS:
442 {
443 struct mpc_config_bus *m=
444 (struct mpc_config_bus *)mpt;
445 MP_bus_info(m);
446 mpt += sizeof(*m);
447 count += sizeof(*m);
448 break;
449 }
450 case MP_IOAPIC:
451 {
452 struct mpc_config_ioapic *m=
453 (struct mpc_config_ioapic *)mpt;
454 MP_ioapic_info(m);
455 mpt+=sizeof(*m);
456 count+=sizeof(*m);
457 break;
458 }
459 case MP_INTSRC:
460 {
461 struct mpc_config_intsrc *m=
462 (struct mpc_config_intsrc *)mpt;
463
464 MP_intsrc_info(m);
465 mpt+=sizeof(*m);
466 count+=sizeof(*m);
467 break;
468 }
469 case MP_LINTSRC:
470 {
471 struct mpc_config_lintsrc *m=
472 (struct mpc_config_lintsrc *)mpt;
473 MP_lintsrc_info(m);
474 mpt+=sizeof(*m);
475 count+=sizeof(*m);
476 break;
477 }
478 default:
479 {
480 count = mpc->mpc_length;
481 break;
482 }
483 }
484 ++mpc_record;
485 }
486 clustered_apic_check();
487 if (!num_processors)
488 printk(KERN_ERR "SMP mptable: no processors registered!\n");
489 return num_processors;
490}
491
492static int __init ELCR_trigger(unsigned int irq)
493{
494 unsigned int port;
495
496 port = 0x4d0 + (irq >> 3);
497 return (inb(port) >> (irq & 7)) & 1;
498}
499
500static void __init construct_default_ioirq_mptable(int mpc_default_type)
501{
502 struct mpc_config_intsrc intsrc;
503 int i;
504 int ELCR_fallback = 0;
505
506 intsrc.mpc_type = MP_INTSRC;
507 intsrc.mpc_irqflag = 0; /* conforming */
508 intsrc.mpc_srcbus = 0;
509 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
510
511 intsrc.mpc_irqtype = mp_INT;
512
513 /*
514 * If true, we have an ISA/PCI system with no IRQ entries
515 * in the MP table. To prevent the PCI interrupts from being set up
516 * incorrectly, we try to use the ELCR. The sanity check to see if
517 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
518 * never be level sensitive, so we simply see if the ELCR agrees.
519 * If it does, we assume it's valid.
520 */
521 if (mpc_default_type == 5) {
522 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
523
524 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
525 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
526 else {
527 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
528 ELCR_fallback = 1;
529 }
530 }
531
532 for (i = 0; i < 16; i++) {
533 switch (mpc_default_type) {
534 case 2:
535 if (i == 0 || i == 13)
536 continue; /* IRQ0 & IRQ13 not connected */
537 /* fall through */
538 default:
539 if (i == 2)
540 continue; /* IRQ2 is never connected */
541 }
542
543 if (ELCR_fallback) {
544 /*
545 * If the ELCR indicates a level-sensitive interrupt, we
546 * copy that information over to the MP table in the
547 * irqflag field (level sensitive, active high polarity).
548 */
549 if (ELCR_trigger(i))
550 intsrc.mpc_irqflag = 13;
551 else
552 intsrc.mpc_irqflag = 0;
553 }
554
555 intsrc.mpc_srcbusirq = i;
556 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
557 MP_intsrc_info(&intsrc);
558 }
559
560 intsrc.mpc_irqtype = mp_ExtINT;
561 intsrc.mpc_srcbusirq = 0;
562 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
563 MP_intsrc_info(&intsrc);
564}
565
566static inline void __init construct_default_ISA_mptable(int mpc_default_type)
567{
568 struct mpc_config_processor processor;
569 struct mpc_config_bus bus;
570 struct mpc_config_ioapic ioapic;
571 struct mpc_config_lintsrc lintsrc;
572 int linttypes[2] = { mp_ExtINT, mp_NMI };
573 int i;
574
575 /*
576 * local APIC has default address
577 */
578 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
579
580 /*
581 * 2 CPUs, numbered 0 & 1.
582 */
583 processor.mpc_type = MP_PROCESSOR;
584 /* Either an integrated APIC or a discrete 82489DX. */
585 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
586 processor.mpc_cpuflag = CPU_ENABLED;
587 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
588 (boot_cpu_data.x86_model << 4) |
589 boot_cpu_data.x86_mask;
590 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
591 processor.mpc_reserved[0] = 0;
592 processor.mpc_reserved[1] = 0;
593 for (i = 0; i < 2; i++) {
594 processor.mpc_apicid = i;
595 MP_processor_info(&processor);
596 }
597
598 bus.mpc_type = MP_BUS;
599 bus.mpc_busid = 0;
600 switch (mpc_default_type) {
601 default:
602 printk("???\n");
603 printk(KERN_ERR "Unknown standard configuration %d\n",
604 mpc_default_type);
605 /* fall through */
606 case 1:
607 case 5:
608 memcpy(bus.mpc_bustype, "ISA ", 6);
609 break;
610 case 2:
611 case 6:
612 case 3:
613 memcpy(bus.mpc_bustype, "EISA ", 6);
614 break;
615 case 4:
616 case 7:
617 memcpy(bus.mpc_bustype, "MCA ", 6);
618 }
619 MP_bus_info(&bus);
620 if (mpc_default_type > 4) {
621 bus.mpc_busid = 1;
622 memcpy(bus.mpc_bustype, "PCI ", 6);
623 MP_bus_info(&bus);
624 }
625
626 ioapic.mpc_type = MP_IOAPIC;
627 ioapic.mpc_apicid = 2;
628 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
629 ioapic.mpc_flags = MPC_APIC_USABLE;
630 ioapic.mpc_apicaddr = 0xFEC00000;
631 MP_ioapic_info(&ioapic);
632
633 /*
634 * We set up most of the low 16 IO-APIC pins according to MPS rules.
635 */
636 construct_default_ioirq_mptable(mpc_default_type);
637
638 lintsrc.mpc_type = MP_LINTSRC;
639 lintsrc.mpc_irqflag = 0; /* conforming */
640 lintsrc.mpc_srcbusid = 0;
641 lintsrc.mpc_srcbusirq = 0;
642 lintsrc.mpc_destapic = MP_APIC_ALL;
643 for (i = 0; i < 2; i++) {
644 lintsrc.mpc_irqtype = linttypes[i];
645 lintsrc.mpc_destapiclint = i;
646 MP_lintsrc_info(&lintsrc);
647 }
648}
649
650static struct intel_mp_floating *mpf_found;
651
652/*
653 * Scan the memory blocks for an SMP configuration block.
654 */
655void __init get_smp_config (void)
656{
657 struct intel_mp_floating *mpf = mpf_found;
658
659 /*
1da177e4
LT		 660 * ACPI supports both logical (e.g. Hyper-Threading) and physical
661 * processors, where MPS only supports physical.
662 */
663 if (acpi_lapic && acpi_ioapic) {
664 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
665 return;
666 }
667 else if (acpi_lapic)
668 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
669
670 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
671 if (mpf->mpf_feature2 & (1<<7)) {
672 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
673 pic_mode = 1;
674 } else {
675 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
676 pic_mode = 0;
677 }
678
679 /*
680 * Now see if we need to read further.
681 */
682 if (mpf->mpf_feature1 != 0) {
683
684 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
685 construct_default_ISA_mptable(mpf->mpf_feature1);
686
687 } else if (mpf->mpf_physptr) {
688
689 /*
690 * Read the physical hardware table. Anything here will
691 * override the defaults.
692 */
7d4c8e56 693 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
1da177e4
LT		 694 smp_found_config = 0;
695 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
696 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
697 return;
698 }
699 /*
700 * If there are no explicit MP IRQ entries, then we are
701 * broken. We set up most of the low 16 IO-APIC pins to
702 * ISA defaults and hope it will work.
703 */
704 if (!mp_irq_entries) {
705 struct mpc_config_bus bus;
706
707 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
708
709 bus.mpc_type = MP_BUS;
710 bus.mpc_busid = 0;
711 memcpy(bus.mpc_bustype, "ISA ", 6);
712 MP_bus_info(&bus);
713
714 construct_default_ioirq_mptable(0);
715 }
716
717 } else
718 BUG();
719
720 printk(KERN_INFO "Processors: %d\n", num_processors);
721 /*
722 * Only use the first configuration found.
723 */
724}
725
726static int __init smp_scan_config (unsigned long base, unsigned long length)
727{
728 unsigned long *bp = phys_to_virt(base);
729 struct intel_mp_floating *mpf;
730
731 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
732 if (sizeof(*mpf) != 16)
733 printk("Error: MPF size\n");
734
735 while (length > 0) {
736 mpf = (struct intel_mp_floating *)bp;
737 if ((*bp == SMP_MAGIC_IDENT) &&
738 (mpf->mpf_length == 1) &&
739 !mpf_checksum((unsigned char *)bp, 16) &&
740 ((mpf->mpf_specification == 1)
741 || (mpf->mpf_specification == 4)) ) {
742
743 smp_found_config = 1;
744 printk(KERN_INFO "found SMP MP-table at %08lx\n",
745 virt_to_phys(mpf));
746 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
747 if (mpf->mpf_physptr) {
748 /*
749 * We cannot access to MPC table to compute
750 * table size yet, as only few megabytes from
751 * the bottom is mapped now.
752 * PC-9800's MPC table places on the very last
753 * of physical memory; so that simply reserving
754 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
755 * in reserve_bootmem.
756 */
757 unsigned long size = PAGE_SIZE;
758 unsigned long end = max_low_pfn * PAGE_SIZE;
759 if (mpf->mpf_physptr + size > end)
760 size = end - mpf->mpf_physptr;
761 reserve_bootmem(mpf->mpf_physptr, size);
762 }
763
764 mpf_found = mpf;
765 return 1;
766 }
767 bp += 4;
768 length -= 16;
769 }
770 return 0;
771}
772
773void __init find_smp_config (void)
774{
775 unsigned int address;
776
777 /*
778 * FIXME: Linux assumes you have 640K of base ram..
779 * this continues the error...
780 *
781 * 1) Scan the bottom 1K for a signature
782 * 2) Scan the top 1K of base RAM
783 * 3) Scan the 64K of bios
784 */
785 if (smp_scan_config(0x0,0x400) ||
786 smp_scan_config(639*0x400,0x400) ||
787 smp_scan_config(0xF0000,0x10000))
788 return;
789 /*
790 * If it is an SMP machine we should know now, unless the
791 * configuration is in an EISA/MCA bus machine with an
792 * extended bios data area.
793 *
794 * there is a real-mode segmented pointer pointing to the
795 * 4K EBDA area at 0x40E, calculate and scan it here.
796 *
797 * NOTE! There are Linux loaders that will corrupt the EBDA
798 * area, and as such this kind of SMP config may be less
799 * trustworthy, simply because the SMP table may have been
800 * stomped on during early boot. These loaders are buggy and
801 * should be fixed.
802 *
803 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
804 */
805
806 address = get_bios_ebda();
807 if (address)
808 smp_scan_config(address, 0x400);
809}
810
e5428ede
NP		 811int es7000_plat;
812
1da177e4
LT		 813/* --------------------------------------------------------------------------
814 ACPI-based MP Configuration
815 -------------------------------------------------------------------------- */
816
888ba6c6 817#ifdef CONFIG_ACPI
1da177e4
LT		 818
819void __init mp_register_lapic_address (
820 u64 address)
821{
822 mp_lapic_addr = (unsigned long) address;
823
824 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
825
826 if (boot_cpu_physical_apicid == -1U)
827 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
828
829 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
830}
831
832
9f40a72a 833void __devinit mp_register_lapic (
1da177e4
LT		 834 u8 id,
835 u8 enabled)
836{
837 struct mpc_config_processor processor;
838 int boot_cpu = 0;
839
840 if (MAX_APICS - id <= 0) {
841 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
842 id, MAX_APICS);
843 return;
844 }
845
846 if (id == boot_cpu_physical_apicid)
847 boot_cpu = 1;
848
849 processor.mpc_type = MP_PROCESSOR;
850 processor.mpc_apicid = id;
851 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
852 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
853 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
854 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
855 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
856 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
857 processor.mpc_reserved[0] = 0;
858 processor.mpc_reserved[1] = 0;
859
860 MP_processor_info(&processor);
861}
862
8466361a 863#ifdef CONFIG_X86_IO_APIC
1da177e4
LT		 864
865#define MP_ISA_BUS 0
866#define MP_MAX_IOAPIC_PIN 127
867
868static struct mp_ioapic_routing {
869 int apic_id;
870 int gsi_base;
871 int gsi_end;
872 u32 pin_programmed[4];
873} mp_ioapic_routing[MAX_IO_APICS];
874
875
876static int mp_find_ioapic (
877 int gsi)
878{
879 int i = 0;
880
881 /* Find the IOAPIC that manages this GSI. */
882 for (i = 0; i < nr_ioapics; i++) {
883 if ((gsi >= mp_ioapic_routing[i].gsi_base)
884 && (gsi <= mp_ioapic_routing[i].gsi_end))
885 return i;
886 }
887
888 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
889
890 return -1;
891}
892
893
894void __init mp_register_ioapic (
895 u8 id,
896 u32 address,
897 u32 gsi_base)
898{
899 int idx = 0;
6070f9ec 900 int tmpid;
1da177e4
LT		 901
902 if (nr_ioapics >= MAX_IO_APICS) {
903 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
904 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
905 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
906 }
907 if (!address) {
908 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
909 " found in MADT table, skipping!\n");
910 return;
911 }
912
913 idx = nr_ioapics++;
914
915 mp_ioapics[idx].mpc_type = MP_IOAPIC;
916 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
917 mp_ioapics[idx].mpc_apicaddr = address;
918
919 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
7c5c1e42
SL		 920 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
921 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
6070f9ec 922 tmpid = io_apic_get_unique_id(idx, id);
ca05fea6 923 else
6070f9ec
AD		 924 tmpid = id;
925 if (tmpid == -1) {
926 nr_ioapics--;
927 return;
928 }
929 mp_ioapics[idx].mpc_apicid = tmpid;
1da177e4
LT		 930 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
931
932 /*
933 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
934 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
935 */
936 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
937 mp_ioapic_routing[idx].gsi_base = gsi_base;
938 mp_ioapic_routing[idx].gsi_end = gsi_base +
939 io_apic_get_redir_entries(idx);
940
941 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
942 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
943 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
944 mp_ioapic_routing[idx].gsi_base,
945 mp_ioapic_routing[idx].gsi_end);
946
947 return;
948}
949
950
951void __init mp_override_legacy_irq (
952 u8 bus_irq,
953 u8 polarity,
954 u8 trigger,
955 u32 gsi)
956{
957 struct mpc_config_intsrc intsrc;
958 int ioapic = -1;
959 int pin = -1;
960
961 /*
962 * Convert 'gsi' to 'ioapic.pin'.
963 */
964 ioapic = mp_find_ioapic(gsi);
965 if (ioapic < 0)
966 return;
967 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
968
969 /*
970 * TBD: This check is for faulty timer entries, where the override
971 * erroneously sets the trigger to level, resulting in a HUGE
972 * increase of timer interrupts!
973 */
974 if ((bus_irq == 0) && (trigger == 3))
975 trigger = 1;
976
977 intsrc.mpc_type = MP_INTSRC;
978 intsrc.mpc_irqtype = mp_INT;
979 intsrc.mpc_irqflag = (trigger << 2) | polarity;
980 intsrc.mpc_srcbus = MP_ISA_BUS;
981 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
982 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
983 intsrc.mpc_dstirq = pin; /* INTIN# */
984
985 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
986 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
987 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
988 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
989
990 mp_irqs[mp_irq_entries] = intsrc;
991 if (++mp_irq_entries == MAX_IRQ_SOURCES)
992 panic("Max # of irq sources exceeded!\n");
993
994 return;
995}
996
1da177e4
LT		 997void __init mp_config_acpi_legacy_irqs (void)
998{
999 struct mpc_config_intsrc intsrc;
1000 int i = 0;
1001 int ioapic = -1;
1002
1003 /*
1004 * Fabricate the legacy ISA bus (bus #31).
1005 */
1006 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1007 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1008
1009 /*
1010 * Older generations of ES7000 have no legacy identity mappings
1011 */
1012 if (es7000_plat == 1)
1013 return;
1014
1015 /*
1016 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1017 */
1018 ioapic = mp_find_ioapic(0);
1019 if (ioapic < 0)
1020 return;
1021
1022 intsrc.mpc_type = MP_INTSRC;
1023 intsrc.mpc_irqflag = 0; /* Conforming */
1024 intsrc.mpc_srcbus = MP_ISA_BUS;
1025 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1026
1027 /*
1028 * Use the default configuration for the IRQs 0-15. Unless
1029 * overriden by (MADT) interrupt source override entries.
1030 */
1031 for (i = 0; i < 16; i++) {
1032 int idx;
1033
1034 for (idx = 0; idx < mp_irq_entries; idx++) {
1035 struct mpc_config_intsrc *irq = mp_irqs + idx;
1036
1037 /* Do we already have a mapping for this ISA IRQ? */
1038 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1039 break;
1040
1041 /* Do we already have a mapping for this IOAPIC pin */
1042 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1043 (irq->mpc_dstirq == i))
1044 break;
1045 }
1046
1047 if (idx != mp_irq_entries) {
1048 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1049 continue; /* IRQ already used */
1050 }
1051
1052 intsrc.mpc_irqtype = mp_INT;
1053 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1054 intsrc.mpc_dstirq = i;
1055
1056 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1057 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1058 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1059 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1060 intsrc.mpc_dstirq);
1061
1062 mp_irqs[mp_irq_entries] = intsrc;
1063 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1064 panic("Max # of irq sources exceeded!\n");
1065 }
1066}
1067
c434b7a6
NP		 1068#define MAX_GSI_NUM 4096
1069
cb654695 1070int mp_register_gsi (u32 gsi, int triggering, int polarity)
1da177e4
LT		 1071{
1072 int ioapic = -1;
1073 int ioapic_pin = 0;
1074 int idx, bit = 0;
c434b7a6
NP		 1075 static int pci_irq = 16;
1076 /*
1077 * Mapping between Global System Interrups, which
1078 * represent all possible interrupts, and IRQs
1079 * assigned to actual devices.
1080 */
1081 static int gsi_to_irq[MAX_GSI_NUM];
1da177e4 1082
1da177e4
LT		 1083 /* Don't set up the ACPI SCI because it's already set up */
1084 if (acpi_fadt.sci_int == gsi)
1085 return gsi;
1da177e4
LT		 1086
1087 ioapic = mp_find_ioapic(gsi);
1088 if (ioapic < 0) {
1089 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1090 return gsi;
1091 }
1092
1093 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1094
1095 if (ioapic_renumber_irq)
1096 gsi = ioapic_renumber_irq(ioapic, gsi);
1097
1098 /*
1099 * Avoid pin reprogramming. PRTs typically include entries
1100 * with redundant pin->gsi mappings (but unique PCI devices);
1101 * we only program the IOAPIC on the first.
1102 */
1103 bit = ioapic_pin % 32;
1104 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1105 if (idx > 3) {
1106 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1107 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1108 ioapic_pin);
1109 return gsi;
1110 }
1111 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1112 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1113 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
c434b7a6 1114 return gsi_to_irq[gsi];
1da177e4
LT		 1115 }
1116
1117 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1118
cb654695 1119 if (triggering == ACPI_LEVEL_SENSITIVE) {
c434b7a6
NP		 1120 /*
1121 * For PCI devices assign IRQs in order, avoiding gaps
1122 * due to unused I/O APIC pins.
1123 */
1124 int irq = gsi;
1125 if (gsi < MAX_GSI_NUM) {
e1afc3f5
NP		 1126 if (gsi > 15)
1127 gsi = pci_irq++;
e1afc3f5
NP		 1128 /*
1129 * Don't assign IRQ used by ACPI SCI
1130 */
1131 if (gsi == acpi_fadt.sci_int)
1132 gsi = pci_irq++;
c434b7a6
NP		 1133 gsi_to_irq[irq] = gsi;
1134 } else {
1135 printk(KERN_ERR "GSI %u is too high\n", gsi);
1136 return gsi;
1137 }
1138 }
1139
1da177e4 1140 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
cb654695
LB		 1141 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1142 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1da177e4
LT		 1143 return gsi;
1144}
1145
8466361a 1146#endif /* CONFIG_X86_IO_APIC */
888ba6c6 1147#endif /* CONFIG_ACPI */
Linux kernel - Deliverables
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