[deliverable/linux.git] / arch / i386 / kernel / smp.c

/*
 *	Intel SMP support routines.
 *
 *	(c) 1995 Alan Cox, Building #3 <alan@redhat.com>
 *	(c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
 *
 *	This code is released under the GNU General Public License version 2 or
 *	later.
 */

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/kernel_stat.h>
#include <linux/mc146818rtc.h>
#include <linux/cache.h>
#include <linux/interrupt.h>
#include <linux/cpu.h>
#include <linux/module.h>

#include <asm/mtrr.h>
#include <asm/tlbflush.h>
#include <mach_apic.h>

/*
 *	Some notes on x86 processor bugs affecting SMP operation:
 *
 *	Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
 *	The Linux implications for SMP are handled as follows:
 *
 *	Pentium III / [Xeon]
 *		None of the E1AP-E3AP errata are visible to the user.
 *
 *	E1AP.	see PII A1AP
 *	E2AP.	see PII A2AP
 *	E3AP.	see PII A3AP
 *
 *	Pentium II / [Xeon]
 *		None of the A1AP-A3AP errata are visible to the user.
 *
 *	A1AP.	see PPro 1AP
 *	A2AP.	see PPro 2AP
 *	A3AP.	see PPro 7AP
 *
 *	Pentium Pro
 *		None of 1AP-9AP errata are visible to the normal user,
 *	except occasional delivery of 'spurious interrupt' as trap #15.
 *	This is very rare and a non-problem.
 *
 *	1AP.	Linux maps APIC as non-cacheable
 *	2AP.	worked around in hardware
 *	3AP.	fixed in C0 and above steppings microcode update.
 *		Linux does not use excessive STARTUP_IPIs.
 *	4AP.	worked around in hardware
 *	5AP.	symmetric IO mode (normal Linux operation) not affected.
 *		'noapic' mode has vector 0xf filled out properly.
 *	6AP.	'noapic' mode might be affected - fixed in later steppings
 *	7AP.	We do not assume writes to the LVT deassering IRQs
 *	8AP.	We do not enable low power mode (deep sleep) during MP bootup
 *	9AP.	We do not use mixed mode
 *
 *	Pentium
 *		There is a marginal case where REP MOVS on 100MHz SMP
 *	machines with B stepping processors can fail. XXX should provide
 *	an L1cache=Writethrough or L1cache=off option.
 *
 *		B stepping CPUs may hang. There are hardware work arounds
 *	for this. We warn about it in case your board doesn't have the work
 *	arounds. Basically thats so I can tell anyone with a B stepping
 *	CPU and SMP problems "tough".
 *
 *	Specific items [From Pentium Processor Specification Update]
 *
 *	1AP.	Linux doesn't use remote read
 *	2AP.	Linux doesn't trust APIC errors
 *	3AP.	We work around this
 *	4AP.	Linux never generated 3 interrupts of the same priority
 *		to cause a lost local interrupt.
 *	5AP.	Remote read is never used
 *	6AP.	not affected - worked around in hardware
 *	7AP.	not affected - worked around in hardware
 *	8AP.	worked around in hardware - we get explicit CS errors if not
 *	9AP.	only 'noapic' mode affected. Might generate spurious
 *		interrupts, we log only the first one and count the
 *		rest silently.
 *	10AP.	not affected - worked around in hardware
 *	11AP.	Linux reads the APIC between writes to avoid this, as per
 *		the documentation. Make sure you preserve this as it affects
 *		the C stepping chips too.
 *	12AP.	not affected - worked around in hardware
 *	13AP.	not affected - worked around in hardware
 *	14AP.	we always deassert INIT during bootup
 *	15AP.	not affected - worked around in hardware
 *	16AP.	not affected - worked around in hardware
 *	17AP.	not affected - worked around in hardware
 *	18AP.	not affected - worked around in hardware
 *	19AP.	not affected - worked around in BIOS
 *
 *	If this sounds worrying believe me these bugs are either ___RARE___,
 *	or are signal timing bugs worked around in hardware and there's
 *	about nothing of note with C stepping upwards.
 */

DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0, };

/*
 * the following functions deal with sending IPIs between CPUs.
 *
 * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
 */

static inline int __prepare_ICR (unsigned int shortcut, int vector)
{
	unsigned int icr = shortcut | APIC_DEST_LOGICAL;

	switch (vector) {
	default:
		icr |= APIC_DM_FIXED | vector;
		break;
	case NMI_VECTOR:
		icr |= APIC_DM_NMI;
		break;
	}
	return icr;
}

static inline int __prepare_ICR2 (unsigned int mask)
{
	return SET_APIC_DEST_FIELD(mask);
}

void __send_IPI_shortcut(unsigned int shortcut, int vector)
{
	/*
	 * Subtle. In the case of the 'never do double writes' workaround
	 * we have to lock out interrupts to be safe.  As we don't care
	 * of the value read we use an atomic rmw access to avoid costly
	 * cli/sti.  Otherwise we use an even cheaper single atomic write
	 * to the APIC.
	 */
	unsigned int cfg;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	/*
	 * No need to touch the target chip field
	 */
	cfg = __prepare_ICR(shortcut, vector);

	/*
	 * Send the IPI. The write to APIC_ICR fires this off.
	 */
	apic_write_around(APIC_ICR, cfg);
}

void fastcall send_IPI_self(int vector)
{
	__send_IPI_shortcut(APIC_DEST_SELF, vector);
}

/*
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Intel SMP support routines.
	3	*
	4	* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
	5	* (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
	6	*
	7	* This code is released under the GNU General Public License version 2 or
	8	* later.
	9	*/
	10
	11	#include <linux/init.h>
	12
	13	#include <linux/mm.h>
1da177e4 LT	14	#include <linux/delay.h>
1da177e4 LT	15	#include <linux/spinlock.h>
1da177e4 LT	16	#include <linux/kernel_stat.h>
	17	#include <linux/mc146818rtc.h>
	18	#include <linux/cache.h>
	19	#include <linux/interrupt.h>
f3705136	20	#include <linux/cpu.h>
129f6946	21	#include <linux/module.h>
1da177e4 LT	22
	23	#include <asm/mtrr.h>
	24	#include <asm/tlbflush.h>
	25	#include <mach_apic.h>
	26
	27	/*
	28	* Some notes on x86 processor bugs affecting SMP operation:
	29	*
	30	* Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
	31	* The Linux implications for SMP are handled as follows:
	32	*
	33	* Pentium III / [Xeon]
	34	* None of the E1AP-E3AP errata are visible to the user.
	35	*
	36	* E1AP. see PII A1AP
	37	* E2AP. see PII A2AP
	38	* E3AP. see PII A3AP
	39	*
	40	* Pentium II / [Xeon]
	41	* None of the A1AP-A3AP errata are visible to the user.
	42	*
	43	* A1AP. see PPro 1AP
	44	* A2AP. see PPro 2AP
	45	* A3AP. see PPro 7AP
	46	*
	47	* Pentium Pro
	48	* None of 1AP-9AP errata are visible to the normal user,
	49	* except occasional delivery of 'spurious interrupt' as trap #15.
	50	* This is very rare and a non-problem.
	51	*
	52	* 1AP. Linux maps APIC as non-cacheable
	53	* 2AP. worked around in hardware
	54	* 3AP. fixed in C0 and above steppings microcode update.
	55	* Linux does not use excessive STARTUP_IPIs.
	56	* 4AP. worked around in hardware
	57	* 5AP. symmetric IO mode (normal Linux operation) not affected.
	58	* 'noapic' mode has vector 0xf filled out properly.
	59	* 6AP. 'noapic' mode might be affected - fixed in later steppings
	60	* 7AP. We do not assume writes to the LVT deassering IRQs
	61	* 8AP. We do not enable low power mode (deep sleep) during MP bootup
	62	* 9AP. We do not use mixed mode
	63	*
	64	* Pentium
	65	* There is a marginal case where REP MOVS on 100MHz SMP
	66	* machines with B stepping processors can fail. XXX should provide
	67	* an L1cache=Writethrough or L1cache=off option.
	68	*
	69	* B stepping CPUs may hang. There are hardware work arounds
	70	* for this. We warn about it in case your board doesn't have the work
	71	* arounds. Basically thats so I can tell anyone with a B stepping
	72	* CPU and SMP problems "tough".
	73	*
	74	* Specific items [From Pentium Processor Specification Update]
	75	*
	76	* 1AP. Linux doesn't use remote read
	77	* 2AP. Linux doesn't trust APIC errors
	78	* 3AP. We work around this
	79	* 4AP. Linux never generated 3 interrupts of the same priority
	80	* to cause a lost local interrupt.
	81	* 5AP. Remote read is never used
	82	* 6AP. not affected - worked around in hardware
	83	* 7AP. not affected - worked around in hardware
	84	* 8AP. worked around in hardware - we get explicit CS errors if not
	85	* 9AP. only 'noapic' mode affected. Might generate spurious
86	* interrupts, we log only the first one and count the
87	* rest silently.
88	* 10AP. not affected - worked around in hardware
89	* 11AP. Linux reads the APIC between writes to avoid this, as per
90	* the documentation. Make sure you preserve this as it affects
91	* the C stepping chips too.
92	* 12AP. not affected - worked around in hardware
93	* 13AP. not affected - worked around in hardware
94	* 14AP. we always deassert INIT during bootup
95	* 15AP. not affected - worked around in hardware
96	* 16AP. not affected - worked around in hardware
97	* 17AP. not affected - worked around in hardware
98	* 18AP. not affected - worked around in hardware
99	* 19AP. not affected - worked around in BIOS
100	*
101	* If this sounds worrying believe me these bugs are either ___RARE___,
102	* or are signal timing bugs worked around in hardware and there's
103	* about nothing of note with C stepping upwards.
104	*/
105
106	DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0, };
107
108	/*
109	* the following functions deal with sending IPIs between CPUs.
110	*
111	* We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
112	*/
113
114	static inline int __prepare_ICR (unsigned int shortcut, int vector)
115	{
45486f81 KO	116	unsigned int icr = shortcut \| APIC_DEST_LOGICAL;
	117
	118	switch (vector) {
	119	default:
	120	icr \|= APIC_DM_FIXED \| vector;
	121	break;
	122	case NMI_VECTOR:
	123	icr \|= APIC_DM_NMI;
	124	break;
	125	}
	126	return icr;
1da177e4 LT	127	}
	128
	129	static inline int __prepare_ICR2 (unsigned int mask)
	130	{
	131	return SET_APIC_DEST_FIELD(mask);
	132	}
	133
	134	void __send_IPI_shortcut(unsigned int shortcut, int vector)
	135	{
	136	/*
	137	* Subtle. In the case of the 'never do double writes' workaround
	138	* we have to lock out interrupts to be safe. As we don't care
	139	* of the value read we use an atomic rmw access to avoid costly
	140	* cli/sti. Otherwise we use an even cheaper single atomic write
	141	* to the APIC.
	142	*/
	143	unsigned int cfg;
	144
	145	/*
	146	* Wait for idle.
	147	*/
	148	apic_wait_icr_idle();
	149
	150	/*
	151	* No need to touch the target chip field
	152	*/
	153	cfg = __prepare_ICR(shortcut, vector);
	154
	155	/*
	156	* Send the IPI. The write to APIC_ICR fires this off.
	157	*/
	158	apic_write_around(APIC_ICR, cfg);
	159	}
	160
	161	void fastcall send_IPI_self(int vector)
	162	{
	163	__send_IPI_shortcut(APIC_DEST_SELF, vector);
	164	}
	165
	166	/*