Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * | |
7 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
8 | * whom a great many thanks are extended. | |
9 | * | |
10 | * Thanks to Intel for making available several different Pentium, | |
11 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
12 | * Original development of Linux SMP code supported by Caldera. | |
13 | * | |
14 | * This code is released under the GNU General Public License version 2 or | |
15 | * later. | |
16 | * | |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. */ | |
35 | ||
36 | #include <linux/module.h> | |
1da177e4 LT |
37 | #include <linux/init.h> |
38 | #include <linux/kernel.h> | |
39 | ||
40 | #include <linux/mm.h> | |
41 | #include <linux/sched.h> | |
42 | #include <linux/kernel_stat.h> | |
43 | #include <linux/smp_lock.h> | |
1da177e4 | 44 | #include <linux/bootmem.h> |
f3705136 ZM |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpu.h> | |
47 | #include <linux/percpu.h> | |
1da177e4 LT |
48 | |
49 | #include <linux/delay.h> | |
50 | #include <linux/mc146818rtc.h> | |
51 | #include <asm/tlbflush.h> | |
52 | #include <asm/desc.h> | |
53 | #include <asm/arch_hooks.h> | |
3e4ff115 | 54 | #include <asm/nmi.h> |
1da177e4 LT |
55 | |
56 | #include <mach_apic.h> | |
57 | #include <mach_wakecpu.h> | |
58 | #include <smpboot_hooks.h> | |
59 | ||
60 | /* Set if we find a B stepping CPU */ | |
0bb3184d | 61 | static int __devinitdata smp_b_stepping; |
1da177e4 LT |
62 | |
63 | /* Number of siblings per CPU package */ | |
64 | int smp_num_siblings = 1; | |
129f6946 AD |
65 | #ifdef CONFIG_X86_HT |
66 | EXPORT_SYMBOL(smp_num_siblings); | |
67 | #endif | |
d720803a | 68 | |
1e9f28fa SS |
69 | /* Last level cache ID of each logical CPU */ |
70 | int cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID}; | |
71 | ||
94605eff | 72 | /* representing HT siblings of each logical CPU */ |
6c036527 | 73 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
d720803a LS |
74 | EXPORT_SYMBOL(cpu_sibling_map); |
75 | ||
94605eff | 76 | /* representing HT and core siblings of each logical CPU */ |
6c036527 | 77 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; |
d720803a LS |
78 | EXPORT_SYMBOL(cpu_core_map); |
79 | ||
1da177e4 | 80 | /* bitmap of online cpus */ |
6c036527 | 81 | cpumask_t cpu_online_map __read_mostly; |
129f6946 | 82 | EXPORT_SYMBOL(cpu_online_map); |
1da177e4 LT |
83 | |
84 | cpumask_t cpu_callin_map; | |
85 | cpumask_t cpu_callout_map; | |
129f6946 | 86 | EXPORT_SYMBOL(cpu_callout_map); |
4ad8d383 ZM |
87 | cpumask_t cpu_possible_map; |
88 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
89 | static cpumask_t smp_commenced_mask; |
90 | ||
e1367daf LS |
91 | /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there |
92 | * is no way to resync one AP against BP. TBD: for prescott and above, we | |
93 | * should use IA64's algorithm | |
94 | */ | |
95 | static int __devinitdata tsc_sync_disabled; | |
96 | ||
1da177e4 LT |
97 | /* Per CPU bogomips and other parameters */ |
98 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
129f6946 | 99 | EXPORT_SYMBOL(cpu_data); |
1da177e4 | 100 | |
6c036527 | 101 | u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly = |
1da177e4 LT |
102 | { [0 ... NR_CPUS-1] = 0xff }; |
103 | EXPORT_SYMBOL(x86_cpu_to_apicid); | |
104 | ||
105 | /* | |
106 | * Trampoline 80x86 program as an array. | |
107 | */ | |
108 | ||
109 | extern unsigned char trampoline_data []; | |
110 | extern unsigned char trampoline_end []; | |
111 | static unsigned char *trampoline_base; | |
112 | static int trampoline_exec; | |
113 | ||
114 | static void map_cpu_to_logical_apicid(void); | |
115 | ||
f3705136 ZM |
116 | /* State of each CPU. */ |
117 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
118 | ||
1da177e4 LT |
119 | /* |
120 | * Currently trivial. Write the real->protected mode | |
121 | * bootstrap into the page concerned. The caller | |
122 | * has made sure it's suitably aligned. | |
123 | */ | |
124 | ||
0bb3184d | 125 | static unsigned long __devinit setup_trampoline(void) |
1da177e4 LT |
126 | { |
127 | memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data); | |
128 | return virt_to_phys(trampoline_base); | |
129 | } | |
130 | ||
131 | /* | |
132 | * We are called very early to get the low memory for the | |
133 | * SMP bootup trampoline page. | |
134 | */ | |
135 | void __init smp_alloc_memory(void) | |
136 | { | |
137 | trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE); | |
138 | /* | |
139 | * Has to be in very low memory so we can execute | |
140 | * real-mode AP code. | |
141 | */ | |
142 | if (__pa(trampoline_base) >= 0x9F000) | |
143 | BUG(); | |
144 | /* | |
145 | * Make the SMP trampoline executable: | |
146 | */ | |
147 | trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1); | |
148 | } | |
149 | ||
150 | /* | |
151 | * The bootstrap kernel entry code has set these up. Save them for | |
152 | * a given CPU | |
153 | */ | |
154 | ||
0bb3184d | 155 | static void __devinit smp_store_cpu_info(int id) |
1da177e4 LT |
156 | { |
157 | struct cpuinfo_x86 *c = cpu_data + id; | |
158 | ||
159 | *c = boot_cpu_data; | |
160 | if (id!=0) | |
161 | identify_cpu(c); | |
162 | /* | |
163 | * Mask B, Pentium, but not Pentium MMX | |
164 | */ | |
165 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
166 | c->x86 == 5 && | |
167 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
168 | c->x86_model <= 3) | |
169 | /* | |
170 | * Remember we have B step Pentia with bugs | |
171 | */ | |
172 | smp_b_stepping = 1; | |
173 | ||
174 | /* | |
175 | * Certain Athlons might work (for various values of 'work') in SMP | |
176 | * but they are not certified as MP capable. | |
177 | */ | |
178 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
179 | ||
3ca113ea DJ |
180 | if (num_possible_cpus() == 1) |
181 | goto valid_k7; | |
182 | ||
1da177e4 LT |
183 | /* Athlon 660/661 is valid. */ |
184 | if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1))) | |
185 | goto valid_k7; | |
186 | ||
187 | /* Duron 670 is valid */ | |
188 | if ((c->x86_model==7) && (c->x86_mask==0)) | |
189 | goto valid_k7; | |
190 | ||
191 | /* | |
192 | * Athlon 662, Duron 671, and Athlon >model 7 have capability bit. | |
193 | * It's worth noting that the A5 stepping (662) of some Athlon XP's | |
194 | * have the MP bit set. | |
195 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more. | |
196 | */ | |
197 | if (((c->x86_model==6) && (c->x86_mask>=2)) || | |
198 | ((c->x86_model==7) && (c->x86_mask>=1)) || | |
199 | (c->x86_model> 7)) | |
200 | if (cpu_has_mp) | |
201 | goto valid_k7; | |
202 | ||
203 | /* If we get here, it's not a certified SMP capable AMD system. */ | |
9f158333 | 204 | add_taint(TAINT_UNSAFE_SMP); |
1da177e4 LT |
205 | } |
206 | ||
207 | valid_k7: | |
208 | ; | |
209 | } | |
210 | ||
211 | /* | |
212 | * TSC synchronization. | |
213 | * | |
214 | * We first check whether all CPUs have their TSC's synchronized, | |
215 | * then we print a warning if not, and always resync. | |
216 | */ | |
217 | ||
c35a7261 AM |
218 | static struct { |
219 | atomic_t start_flag; | |
220 | atomic_t count_start; | |
221 | atomic_t count_stop; | |
222 | unsigned long long values[NR_CPUS]; | |
223 | } tsc __initdata = { | |
224 | .start_flag = ATOMIC_INIT(0), | |
225 | .count_start = ATOMIC_INIT(0), | |
226 | .count_stop = ATOMIC_INIT(0), | |
227 | }; | |
1da177e4 LT |
228 | |
229 | #define NR_LOOPS 5 | |
230 | ||
c35a7261 | 231 | static void __init synchronize_tsc_bp(void) |
1da177e4 LT |
232 | { |
233 | int i; | |
234 | unsigned long long t0; | |
235 | unsigned long long sum, avg; | |
236 | long long delta; | |
a3a255e7 | 237 | unsigned int one_usec; |
1da177e4 LT |
238 | int buggy = 0; |
239 | ||
240 | printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus()); | |
241 | ||
242 | /* convert from kcyc/sec to cyc/usec */ | |
243 | one_usec = cpu_khz / 1000; | |
244 | ||
c35a7261 | 245 | atomic_set(&tsc.start_flag, 1); |
1da177e4 LT |
246 | wmb(); |
247 | ||
248 | /* | |
249 | * We loop a few times to get a primed instruction cache, | |
250 | * then the last pass is more or less synchronized and | |
251 | * the BP and APs set their cycle counters to zero all at | |
252 | * once. This reduces the chance of having random offsets | |
253 | * between the processors, and guarantees that the maximum | |
254 | * delay between the cycle counters is never bigger than | |
255 | * the latency of information-passing (cachelines) between | |
256 | * two CPUs. | |
257 | */ | |
258 | for (i = 0; i < NR_LOOPS; i++) { | |
259 | /* | |
260 | * all APs synchronize but they loop on '== num_cpus' | |
261 | */ | |
c35a7261 | 262 | while (atomic_read(&tsc.count_start) != num_booting_cpus()-1) |
18698917 | 263 | cpu_relax(); |
c35a7261 | 264 | atomic_set(&tsc.count_stop, 0); |
1da177e4 LT |
265 | wmb(); |
266 | /* | |
267 | * this lets the APs save their current TSC: | |
268 | */ | |
c35a7261 | 269 | atomic_inc(&tsc.count_start); |
1da177e4 | 270 | |
c35a7261 | 271 | rdtscll(tsc.values[smp_processor_id()]); |
1da177e4 LT |
272 | /* |
273 | * We clear the TSC in the last loop: | |
274 | */ | |
275 | if (i == NR_LOOPS-1) | |
276 | write_tsc(0, 0); | |
277 | ||
278 | /* | |
279 | * Wait for all APs to leave the synchronization point: | |
280 | */ | |
c35a7261 | 281 | while (atomic_read(&tsc.count_stop) != num_booting_cpus()-1) |
18698917 | 282 | cpu_relax(); |
c35a7261 | 283 | atomic_set(&tsc.count_start, 0); |
1da177e4 | 284 | wmb(); |
c35a7261 | 285 | atomic_inc(&tsc.count_stop); |
1da177e4 LT |
286 | } |
287 | ||
288 | sum = 0; | |
289 | for (i = 0; i < NR_CPUS; i++) { | |
290 | if (cpu_isset(i, cpu_callout_map)) { | |
c35a7261 | 291 | t0 = tsc.values[i]; |
1da177e4 LT |
292 | sum += t0; |
293 | } | |
294 | } | |
295 | avg = sum; | |
296 | do_div(avg, num_booting_cpus()); | |
297 | ||
1da177e4 LT |
298 | for (i = 0; i < NR_CPUS; i++) { |
299 | if (!cpu_isset(i, cpu_callout_map)) | |
300 | continue; | |
c35a7261 | 301 | delta = tsc.values[i] - avg; |
1da177e4 LT |
302 | if (delta < 0) |
303 | delta = -delta; | |
304 | /* | |
305 | * We report bigger than 2 microseconds clock differences. | |
306 | */ | |
307 | if (delta > 2*one_usec) { | |
c35a7261 AM |
308 | long long realdelta; |
309 | ||
1da177e4 LT |
310 | if (!buggy) { |
311 | buggy = 1; | |
312 | printk("\n"); | |
313 | } | |
314 | realdelta = delta; | |
315 | do_div(realdelta, one_usec); | |
c35a7261 | 316 | if (tsc.values[i] < avg) |
1da177e4 LT |
317 | realdelta = -realdelta; |
318 | ||
c35a7261 AM |
319 | if (realdelta) |
320 | printk(KERN_INFO "CPU#%d had %Ld usecs TSC " | |
7f5910ec | 321 | "skew, fixed it up.\n", i, realdelta); |
1da177e4 | 322 | } |
1da177e4 LT |
323 | } |
324 | if (!buggy) | |
325 | printk("passed.\n"); | |
326 | } | |
327 | ||
c35a7261 | 328 | static void __init synchronize_tsc_ap(void) |
1da177e4 LT |
329 | { |
330 | int i; | |
331 | ||
332 | /* | |
333 | * Not every cpu is online at the time | |
334 | * this gets called, so we first wait for the BP to | |
335 | * finish SMP initialization: | |
336 | */ | |
c35a7261 | 337 | while (!atomic_read(&tsc.start_flag)) |
18698917 | 338 | cpu_relax(); |
1da177e4 LT |
339 | |
340 | for (i = 0; i < NR_LOOPS; i++) { | |
c35a7261 AM |
341 | atomic_inc(&tsc.count_start); |
342 | while (atomic_read(&tsc.count_start) != num_booting_cpus()) | |
18698917 | 343 | cpu_relax(); |
1da177e4 | 344 | |
c35a7261 | 345 | rdtscll(tsc.values[smp_processor_id()]); |
1da177e4 LT |
346 | if (i == NR_LOOPS-1) |
347 | write_tsc(0, 0); | |
348 | ||
c35a7261 AM |
349 | atomic_inc(&tsc.count_stop); |
350 | while (atomic_read(&tsc.count_stop) != num_booting_cpus()) | |
18698917 | 351 | cpu_relax(); |
1da177e4 LT |
352 | } |
353 | } | |
354 | #undef NR_LOOPS | |
355 | ||
356 | extern void calibrate_delay(void); | |
357 | ||
358 | static atomic_t init_deasserted; | |
359 | ||
0bb3184d | 360 | static void __devinit smp_callin(void) |
1da177e4 LT |
361 | { |
362 | int cpuid, phys_id; | |
363 | unsigned long timeout; | |
364 | ||
365 | /* | |
366 | * If waken up by an INIT in an 82489DX configuration | |
367 | * we may get here before an INIT-deassert IPI reaches | |
368 | * our local APIC. We have to wait for the IPI or we'll | |
369 | * lock up on an APIC access. | |
370 | */ | |
371 | wait_for_init_deassert(&init_deasserted); | |
372 | ||
373 | /* | |
374 | * (This works even if the APIC is not enabled.) | |
375 | */ | |
376 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
377 | cpuid = smp_processor_id(); | |
378 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
379 | printk("huh, phys CPU#%d, CPU#%d already present??\n", | |
380 | phys_id, cpuid); | |
381 | BUG(); | |
382 | } | |
383 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
384 | ||
385 | /* | |
386 | * STARTUP IPIs are fragile beasts as they might sometimes | |
387 | * trigger some glue motherboard logic. Complete APIC bus | |
388 | * silence for 1 second, this overestimates the time the | |
389 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
390 | * by a factor of two. This should be enough. | |
391 | */ | |
392 | ||
393 | /* | |
394 | * Waiting 2s total for startup (udelay is not yet working) | |
395 | */ | |
396 | timeout = jiffies + 2*HZ; | |
397 | while (time_before(jiffies, timeout)) { | |
398 | /* | |
399 | * Has the boot CPU finished it's STARTUP sequence? | |
400 | */ | |
401 | if (cpu_isset(cpuid, cpu_callout_map)) | |
402 | break; | |
403 | rep_nop(); | |
404 | } | |
405 | ||
406 | if (!time_before(jiffies, timeout)) { | |
407 | printk("BUG: CPU%d started up but did not get a callout!\n", | |
408 | cpuid); | |
409 | BUG(); | |
410 | } | |
411 | ||
412 | /* | |
413 | * the boot CPU has finished the init stage and is spinning | |
414 | * on callin_map until we finish. We are free to set up this | |
415 | * CPU, first the APIC. (this is probably redundant on most | |
416 | * boards) | |
417 | */ | |
418 | ||
419 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
420 | smp_callin_clear_local_apic(); | |
421 | setup_local_APIC(); | |
422 | map_cpu_to_logical_apicid(); | |
423 | ||
424 | /* | |
425 | * Get our bogomips. | |
426 | */ | |
427 | calibrate_delay(); | |
428 | Dprintk("Stack at about %p\n",&cpuid); | |
429 | ||
430 | /* | |
431 | * Save our processor parameters | |
432 | */ | |
433 | smp_store_cpu_info(cpuid); | |
434 | ||
435 | disable_APIC_timer(); | |
436 | ||
437 | /* | |
438 | * Allow the master to continue. | |
439 | */ | |
440 | cpu_set(cpuid, cpu_callin_map); | |
441 | ||
442 | /* | |
443 | * Synchronize the TSC with the BP | |
444 | */ | |
e1367daf | 445 | if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled) |
1da177e4 LT |
446 | synchronize_tsc_ap(); |
447 | } | |
448 | ||
449 | static int cpucount; | |
450 | ||
1e9f28fa SS |
451 | /* maps the cpu to the sched domain representing multi-core */ |
452 | cpumask_t cpu_coregroup_map(int cpu) | |
453 | { | |
454 | struct cpuinfo_x86 *c = cpu_data + cpu; | |
455 | /* | |
456 | * For perf, we return last level cache shared map. | |
5c45bf27 | 457 | * And for power savings, we return cpu_core_map |
1e9f28fa | 458 | */ |
5c45bf27 SS |
459 | if (sched_mc_power_savings || sched_smt_power_savings) |
460 | return cpu_core_map[cpu]; | |
461 | else | |
462 | return c->llc_shared_map; | |
1e9f28fa SS |
463 | } |
464 | ||
94605eff SS |
465 | /* representing cpus for which sibling maps can be computed */ |
466 | static cpumask_t cpu_sibling_setup_map; | |
467 | ||
d720803a LS |
468 | static inline void |
469 | set_cpu_sibling_map(int cpu) | |
470 | { | |
471 | int i; | |
94605eff SS |
472 | struct cpuinfo_x86 *c = cpu_data; |
473 | ||
474 | cpu_set(cpu, cpu_sibling_setup_map); | |
d720803a LS |
475 | |
476 | if (smp_num_siblings > 1) { | |
94605eff | 477 | for_each_cpu_mask(i, cpu_sibling_setup_map) { |
4b89aff9 RS |
478 | if (c[cpu].phys_proc_id == c[i].phys_proc_id && |
479 | c[cpu].cpu_core_id == c[i].cpu_core_id) { | |
d720803a LS |
480 | cpu_set(i, cpu_sibling_map[cpu]); |
481 | cpu_set(cpu, cpu_sibling_map[i]); | |
94605eff SS |
482 | cpu_set(i, cpu_core_map[cpu]); |
483 | cpu_set(cpu, cpu_core_map[i]); | |
1e9f28fa SS |
484 | cpu_set(i, c[cpu].llc_shared_map); |
485 | cpu_set(cpu, c[i].llc_shared_map); | |
d720803a LS |
486 | } |
487 | } | |
488 | } else { | |
489 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
490 | } | |
491 | ||
1e9f28fa SS |
492 | cpu_set(cpu, c[cpu].llc_shared_map); |
493 | ||
94605eff | 494 | if (current_cpu_data.x86_max_cores == 1) { |
d720803a | 495 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; |
94605eff SS |
496 | c[cpu].booted_cores = 1; |
497 | return; | |
498 | } | |
499 | ||
500 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
1e9f28fa SS |
501 | if (cpu_llc_id[cpu] != BAD_APICID && |
502 | cpu_llc_id[cpu] == cpu_llc_id[i]) { | |
503 | cpu_set(i, c[cpu].llc_shared_map); | |
504 | cpu_set(cpu, c[i].llc_shared_map); | |
505 | } | |
4b89aff9 | 506 | if (c[cpu].phys_proc_id == c[i].phys_proc_id) { |
94605eff SS |
507 | cpu_set(i, cpu_core_map[cpu]); |
508 | cpu_set(cpu, cpu_core_map[i]); | |
509 | /* | |
510 | * Does this new cpu bringup a new core? | |
511 | */ | |
512 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) { | |
513 | /* | |
514 | * for each core in package, increment | |
515 | * the booted_cores for this new cpu | |
516 | */ | |
517 | if (first_cpu(cpu_sibling_map[i]) == i) | |
518 | c[cpu].booted_cores++; | |
519 | /* | |
520 | * increment the core count for all | |
521 | * the other cpus in this package | |
522 | */ | |
523 | if (i != cpu) | |
524 | c[i].booted_cores++; | |
525 | } else if (i != cpu && !c[cpu].booted_cores) | |
526 | c[cpu].booted_cores = c[i].booted_cores; | |
527 | } | |
d720803a LS |
528 | } |
529 | } | |
530 | ||
1da177e4 LT |
531 | /* |
532 | * Activate a secondary processor. | |
533 | */ | |
0bb3184d | 534 | static void __devinit start_secondary(void *unused) |
1da177e4 LT |
535 | { |
536 | /* | |
537 | * Dont put anything before smp_callin(), SMP | |
538 | * booting is too fragile that we want to limit the | |
539 | * things done here to the most necessary things. | |
540 | */ | |
541 | cpu_init(); | |
5bfb5d69 | 542 | preempt_disable(); |
1da177e4 LT |
543 | smp_callin(); |
544 | while (!cpu_isset(smp_processor_id(), smp_commenced_mask)) | |
545 | rep_nop(); | |
546 | setup_secondary_APIC_clock(); | |
547 | if (nmi_watchdog == NMI_IO_APIC) { | |
548 | disable_8259A_irq(0); | |
549 | enable_NMI_through_LVT0(NULL); | |
550 | enable_8259A_irq(0); | |
551 | } | |
552 | enable_APIC_timer(); | |
553 | /* | |
554 | * low-memory mappings have been cleared, flush them from | |
555 | * the local TLBs too. | |
556 | */ | |
557 | local_flush_tlb(); | |
6fe940d6 | 558 | |
d720803a LS |
559 | /* This must be done before setting cpu_online_map */ |
560 | set_cpu_sibling_map(raw_smp_processor_id()); | |
561 | wmb(); | |
562 | ||
6fe940d6 LS |
563 | /* |
564 | * We need to hold call_lock, so there is no inconsistency | |
565 | * between the time smp_call_function() determines number of | |
566 | * IPI receipients, and the time when the determination is made | |
567 | * for which cpus receive the IPI. Holding this | |
568 | * lock helps us to not include this cpu in a currently in progress | |
569 | * smp_call_function(). | |
570 | */ | |
571 | lock_ipi_call_lock(); | |
1da177e4 | 572 | cpu_set(smp_processor_id(), cpu_online_map); |
6fe940d6 | 573 | unlock_ipi_call_lock(); |
e1367daf | 574 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
575 | |
576 | /* We can take interrupts now: we're officially "up". */ | |
577 | local_irq_enable(); | |
578 | ||
579 | wmb(); | |
580 | cpu_idle(); | |
581 | } | |
582 | ||
583 | /* | |
584 | * Everything has been set up for the secondary | |
585 | * CPUs - they just need to reload everything | |
586 | * from the task structure | |
587 | * This function must not return. | |
588 | */ | |
0bb3184d | 589 | void __devinit initialize_secondary(void) |
1da177e4 LT |
590 | { |
591 | /* | |
592 | * We don't actually need to load the full TSS, | |
593 | * basically just the stack pointer and the eip. | |
594 | */ | |
595 | ||
596 | asm volatile( | |
597 | "movl %0,%%esp\n\t" | |
598 | "jmp *%1" | |
599 | : | |
600 | :"r" (current->thread.esp),"r" (current->thread.eip)); | |
601 | } | |
602 | ||
603 | extern struct { | |
604 | void * esp; | |
605 | unsigned short ss; | |
606 | } stack_start; | |
607 | ||
608 | #ifdef CONFIG_NUMA | |
609 | ||
610 | /* which logical CPUs are on which nodes */ | |
6c036527 | 611 | cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly = |
1da177e4 LT |
612 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; |
613 | /* which node each logical CPU is on */ | |
6c036527 | 614 | int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; |
1da177e4 LT |
615 | EXPORT_SYMBOL(cpu_2_node); |
616 | ||
617 | /* set up a mapping between cpu and node. */ | |
618 | static inline void map_cpu_to_node(int cpu, int node) | |
619 | { | |
620 | printk("Mapping cpu %d to node %d\n", cpu, node); | |
621 | cpu_set(cpu, node_2_cpu_mask[node]); | |
622 | cpu_2_node[cpu] = node; | |
623 | } | |
624 | ||
625 | /* undo a mapping between cpu and node. */ | |
626 | static inline void unmap_cpu_to_node(int cpu) | |
627 | { | |
628 | int node; | |
629 | ||
630 | printk("Unmapping cpu %d from all nodes\n", cpu); | |
631 | for (node = 0; node < MAX_NUMNODES; node ++) | |
632 | cpu_clear(cpu, node_2_cpu_mask[node]); | |
633 | cpu_2_node[cpu] = 0; | |
634 | } | |
635 | #else /* !CONFIG_NUMA */ | |
636 | ||
637 | #define map_cpu_to_node(cpu, node) ({}) | |
638 | #define unmap_cpu_to_node(cpu) ({}) | |
639 | ||
640 | #endif /* CONFIG_NUMA */ | |
641 | ||
6c036527 | 642 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; |
1da177e4 LT |
643 | |
644 | static void map_cpu_to_logical_apicid(void) | |
645 | { | |
646 | int cpu = smp_processor_id(); | |
647 | int apicid = logical_smp_processor_id(); | |
bfa0e9a0 | 648 | int node = apicid_to_node(apicid); |
649 | ||
650 | if (!node_online(node)) | |
651 | node = first_online_node; | |
1da177e4 LT |
652 | |
653 | cpu_2_logical_apicid[cpu] = apicid; | |
bfa0e9a0 | 654 | map_cpu_to_node(cpu, node); |
1da177e4 LT |
655 | } |
656 | ||
657 | static void unmap_cpu_to_logical_apicid(int cpu) | |
658 | { | |
659 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
660 | unmap_cpu_to_node(cpu); | |
661 | } | |
662 | ||
663 | #if APIC_DEBUG | |
664 | static inline void __inquire_remote_apic(int apicid) | |
665 | { | |
666 | int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
667 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
668 | int timeout, status; | |
669 | ||
670 | printk("Inquiring remote APIC #%d...\n", apicid); | |
671 | ||
38e548ee | 672 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
1da177e4 LT |
673 | printk("... APIC #%d %s: ", apicid, names[i]); |
674 | ||
675 | /* | |
676 | * Wait for idle. | |
677 | */ | |
678 | apic_wait_icr_idle(); | |
679 | ||
680 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
681 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
682 | ||
683 | timeout = 0; | |
684 | do { | |
685 | udelay(100); | |
686 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
687 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
688 | ||
689 | switch (status) { | |
690 | case APIC_ICR_RR_VALID: | |
691 | status = apic_read(APIC_RRR); | |
692 | printk("%08x\n", status); | |
693 | break; | |
694 | default: | |
695 | printk("failed\n"); | |
696 | } | |
697 | } | |
698 | } | |
699 | #endif | |
700 | ||
701 | #ifdef WAKE_SECONDARY_VIA_NMI | |
702 | /* | |
703 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
704 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
705 | * won't ... remember to clear down the APIC, etc later. | |
706 | */ | |
0bb3184d | 707 | static int __devinit |
1da177e4 LT |
708 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) |
709 | { | |
710 | unsigned long send_status = 0, accept_status = 0; | |
711 | int timeout, maxlvt; | |
712 | ||
713 | /* Target chip */ | |
714 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
715 | ||
716 | /* Boot on the stack */ | |
717 | /* Kick the second */ | |
718 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
719 | ||
720 | Dprintk("Waiting for send to finish...\n"); | |
721 | timeout = 0; | |
722 | do { | |
723 | Dprintk("+"); | |
724 | udelay(100); | |
725 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
726 | } while (send_status && (timeout++ < 1000)); | |
727 | ||
728 | /* | |
729 | * Give the other CPU some time to accept the IPI. | |
730 | */ | |
731 | udelay(200); | |
732 | /* | |
733 | * Due to the Pentium erratum 3AP. | |
734 | */ | |
735 | maxlvt = get_maxlvt(); | |
736 | if (maxlvt > 3) { | |
737 | apic_read_around(APIC_SPIV); | |
738 | apic_write(APIC_ESR, 0); | |
739 | } | |
740 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
741 | Dprintk("NMI sent.\n"); | |
742 | ||
743 | if (send_status) | |
744 | printk("APIC never delivered???\n"); | |
745 | if (accept_status) | |
746 | printk("APIC delivery error (%lx).\n", accept_status); | |
747 | ||
748 | return (send_status | accept_status); | |
749 | } | |
750 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
751 | ||
752 | #ifdef WAKE_SECONDARY_VIA_INIT | |
0bb3184d | 753 | static int __devinit |
1da177e4 LT |
754 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) |
755 | { | |
756 | unsigned long send_status = 0, accept_status = 0; | |
757 | int maxlvt, timeout, num_starts, j; | |
758 | ||
759 | /* | |
760 | * Be paranoid about clearing APIC errors. | |
761 | */ | |
762 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
763 | apic_read_around(APIC_SPIV); | |
764 | apic_write(APIC_ESR, 0); | |
765 | apic_read(APIC_ESR); | |
766 | } | |
767 | ||
768 | Dprintk("Asserting INIT.\n"); | |
769 | ||
770 | /* | |
771 | * Turn INIT on target chip | |
772 | */ | |
773 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
774 | ||
775 | /* | |
776 | * Send IPI | |
777 | */ | |
778 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
779 | | APIC_DM_INIT); | |
780 | ||
781 | Dprintk("Waiting for send to finish...\n"); | |
782 | timeout = 0; | |
783 | do { | |
784 | Dprintk("+"); | |
785 | udelay(100); | |
786 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
787 | } while (send_status && (timeout++ < 1000)); | |
788 | ||
789 | mdelay(10); | |
790 | ||
791 | Dprintk("Deasserting INIT.\n"); | |
792 | ||
793 | /* Target chip */ | |
794 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
795 | ||
796 | /* Send IPI */ | |
797 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
798 | ||
799 | Dprintk("Waiting for send to finish...\n"); | |
800 | timeout = 0; | |
801 | do { | |
802 | Dprintk("+"); | |
803 | udelay(100); | |
804 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
805 | } while (send_status && (timeout++ < 1000)); | |
806 | ||
807 | atomic_set(&init_deasserted, 1); | |
808 | ||
809 | /* | |
810 | * Should we send STARTUP IPIs ? | |
811 | * | |
812 | * Determine this based on the APIC version. | |
813 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
814 | */ | |
815 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
816 | num_starts = 2; | |
817 | else | |
818 | num_starts = 0; | |
819 | ||
820 | /* | |
821 | * Run STARTUP IPI loop. | |
822 | */ | |
823 | Dprintk("#startup loops: %d.\n", num_starts); | |
824 | ||
825 | maxlvt = get_maxlvt(); | |
826 | ||
827 | for (j = 1; j <= num_starts; j++) { | |
828 | Dprintk("Sending STARTUP #%d.\n",j); | |
829 | apic_read_around(APIC_SPIV); | |
830 | apic_write(APIC_ESR, 0); | |
831 | apic_read(APIC_ESR); | |
832 | Dprintk("After apic_write.\n"); | |
833 | ||
834 | /* | |
835 | * STARTUP IPI | |
836 | */ | |
837 | ||
838 | /* Target chip */ | |
839 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
840 | ||
841 | /* Boot on the stack */ | |
842 | /* Kick the second */ | |
843 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
844 | | (start_eip >> 12)); | |
845 | ||
846 | /* | |
847 | * Give the other CPU some time to accept the IPI. | |
848 | */ | |
849 | udelay(300); | |
850 | ||
851 | Dprintk("Startup point 1.\n"); | |
852 | ||
853 | Dprintk("Waiting for send to finish...\n"); | |
854 | timeout = 0; | |
855 | do { | |
856 | Dprintk("+"); | |
857 | udelay(100); | |
858 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
859 | } while (send_status && (timeout++ < 1000)); | |
860 | ||
861 | /* | |
862 | * Give the other CPU some time to accept the IPI. | |
863 | */ | |
864 | udelay(200); | |
865 | /* | |
866 | * Due to the Pentium erratum 3AP. | |
867 | */ | |
868 | if (maxlvt > 3) { | |
869 | apic_read_around(APIC_SPIV); | |
870 | apic_write(APIC_ESR, 0); | |
871 | } | |
872 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
873 | if (send_status || accept_status) | |
874 | break; | |
875 | } | |
876 | Dprintk("After Startup.\n"); | |
877 | ||
878 | if (send_status) | |
879 | printk("APIC never delivered???\n"); | |
880 | if (accept_status) | |
881 | printk("APIC delivery error (%lx).\n", accept_status); | |
882 | ||
883 | return (send_status | accept_status); | |
884 | } | |
885 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
886 | ||
887 | extern cpumask_t cpu_initialized; | |
e1367daf LS |
888 | static inline int alloc_cpu_id(void) |
889 | { | |
890 | cpumask_t tmp_map; | |
891 | int cpu; | |
892 | cpus_complement(tmp_map, cpu_present_map); | |
893 | cpu = first_cpu(tmp_map); | |
894 | if (cpu >= NR_CPUS) | |
895 | return -ENODEV; | |
896 | return cpu; | |
897 | } | |
898 | ||
899 | #ifdef CONFIG_HOTPLUG_CPU | |
900 | static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS]; | |
901 | static inline struct task_struct * alloc_idle_task(int cpu) | |
902 | { | |
903 | struct task_struct *idle; | |
904 | ||
905 | if ((idle = cpu_idle_tasks[cpu]) != NULL) { | |
906 | /* initialize thread_struct. we really want to avoid destroy | |
907 | * idle tread | |
908 | */ | |
07b047fc | 909 | idle->thread.esp = (unsigned long)task_pt_regs(idle); |
e1367daf LS |
910 | init_idle(idle, cpu); |
911 | return idle; | |
912 | } | |
913 | idle = fork_idle(cpu); | |
914 | ||
915 | if (!IS_ERR(idle)) | |
916 | cpu_idle_tasks[cpu] = idle; | |
917 | return idle; | |
918 | } | |
919 | #else | |
920 | #define alloc_idle_task(cpu) fork_idle(cpu) | |
921 | #endif | |
1da177e4 | 922 | |
e1367daf | 923 | static int __devinit do_boot_cpu(int apicid, int cpu) |
1da177e4 LT |
924 | /* |
925 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
926 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
927 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
928 | */ | |
929 | { | |
930 | struct task_struct *idle; | |
931 | unsigned long boot_error; | |
e1367daf | 932 | int timeout; |
1da177e4 LT |
933 | unsigned long start_eip; |
934 | unsigned short nmi_high = 0, nmi_low = 0; | |
935 | ||
e1367daf | 936 | ++cpucount; |
9a0b5817 | 937 | alternatives_smp_switch(1); |
e1367daf | 938 | |
1da177e4 LT |
939 | /* |
940 | * We can't use kernel_thread since we must avoid to | |
941 | * reschedule the child. | |
942 | */ | |
e1367daf | 943 | idle = alloc_idle_task(cpu); |
1da177e4 LT |
944 | if (IS_ERR(idle)) |
945 | panic("failed fork for CPU %d", cpu); | |
946 | idle->thread.eip = (unsigned long) start_secondary; | |
947 | /* start_eip had better be page-aligned! */ | |
948 | start_eip = setup_trampoline(); | |
949 | ||
950 | /* So we see what's up */ | |
951 | printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip); | |
952 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
953 | stack_start.esp = (void *) idle->thread.esp; | |
954 | ||
955 | irq_ctx_init(cpu); | |
956 | ||
957 | /* | |
958 | * This grunge runs the startup process for | |
959 | * the targeted processor. | |
960 | */ | |
961 | ||
962 | atomic_set(&init_deasserted, 0); | |
963 | ||
964 | Dprintk("Setting warm reset code and vector.\n"); | |
965 | ||
966 | store_NMI_vector(&nmi_high, &nmi_low); | |
967 | ||
968 | smpboot_setup_warm_reset_vector(start_eip); | |
969 | ||
970 | /* | |
971 | * Starting actual IPI sequence... | |
972 | */ | |
973 | boot_error = wakeup_secondary_cpu(apicid, start_eip); | |
974 | ||
975 | if (!boot_error) { | |
976 | /* | |
977 | * allow APs to start initializing. | |
978 | */ | |
979 | Dprintk("Before Callout %d.\n", cpu); | |
980 | cpu_set(cpu, cpu_callout_map); | |
981 | Dprintk("After Callout %d.\n", cpu); | |
982 | ||
983 | /* | |
984 | * Wait 5s total for a response | |
985 | */ | |
986 | for (timeout = 0; timeout < 50000; timeout++) { | |
987 | if (cpu_isset(cpu, cpu_callin_map)) | |
988 | break; /* It has booted */ | |
989 | udelay(100); | |
990 | } | |
991 | ||
992 | if (cpu_isset(cpu, cpu_callin_map)) { | |
993 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
994 | Dprintk("OK.\n"); | |
995 | printk("CPU%d: ", cpu); | |
996 | print_cpu_info(&cpu_data[cpu]); | |
997 | Dprintk("CPU has booted.\n"); | |
998 | } else { | |
999 | boot_error= 1; | |
1000 | if (*((volatile unsigned char *)trampoline_base) | |
1001 | == 0xA5) | |
1002 | /* trampoline started but...? */ | |
1003 | printk("Stuck ??\n"); | |
1004 | else | |
1005 | /* trampoline code not run */ | |
1006 | printk("Not responding.\n"); | |
1007 | inquire_remote_apic(apicid); | |
1008 | } | |
1009 | } | |
e1367daf | 1010 | |
1da177e4 LT |
1011 | if (boot_error) { |
1012 | /* Try to put things back the way they were before ... */ | |
1013 | unmap_cpu_to_logical_apicid(cpu); | |
1014 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
1015 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
1016 | cpucount--; | |
e1367daf LS |
1017 | } else { |
1018 | x86_cpu_to_apicid[cpu] = apicid; | |
1019 | cpu_set(cpu, cpu_present_map); | |
1da177e4 LT |
1020 | } |
1021 | ||
1022 | /* mark "stuck" area as not stuck */ | |
1023 | *((volatile unsigned long *)trampoline_base) = 0; | |
1024 | ||
1025 | return boot_error; | |
1026 | } | |
1027 | ||
e1367daf LS |
1028 | #ifdef CONFIG_HOTPLUG_CPU |
1029 | void cpu_exit_clear(void) | |
1030 | { | |
1031 | int cpu = raw_smp_processor_id(); | |
1032 | ||
1033 | idle_task_exit(); | |
1034 | ||
1035 | cpucount --; | |
1036 | cpu_uninit(); | |
1037 | irq_ctx_exit(cpu); | |
1038 | ||
1039 | cpu_clear(cpu, cpu_callout_map); | |
1040 | cpu_clear(cpu, cpu_callin_map); | |
e1367daf LS |
1041 | |
1042 | cpu_clear(cpu, smp_commenced_mask); | |
1043 | unmap_cpu_to_logical_apicid(cpu); | |
1044 | } | |
1045 | ||
1046 | struct warm_boot_cpu_info { | |
1047 | struct completion *complete; | |
1048 | int apicid; | |
1049 | int cpu; | |
1050 | }; | |
1051 | ||
34f361ad | 1052 | static void __cpuinit do_warm_boot_cpu(void *p) |
e1367daf LS |
1053 | { |
1054 | struct warm_boot_cpu_info *info = p; | |
1055 | do_boot_cpu(info->apicid, info->cpu); | |
1056 | complete(info->complete); | |
1057 | } | |
1058 | ||
34f361ad | 1059 | static int __cpuinit __smp_prepare_cpu(int cpu) |
e1367daf LS |
1060 | { |
1061 | DECLARE_COMPLETION(done); | |
1062 | struct warm_boot_cpu_info info; | |
1063 | struct work_struct task; | |
1064 | int apicid, ret; | |
bd9e0b74 | 1065 | struct Xgt_desc_struct *cpu_gdt_descr = &per_cpu(cpu_gdt_descr, cpu); |
e1367daf | 1066 | |
e1367daf LS |
1067 | apicid = x86_cpu_to_apicid[cpu]; |
1068 | if (apicid == BAD_APICID) { | |
1069 | ret = -ENODEV; | |
1070 | goto exit; | |
1071 | } | |
1072 | ||
bd9e0b74 SL |
1073 | /* |
1074 | * the CPU isn't initialized at boot time, allocate gdt table here. | |
1075 | * cpu_init will initialize it | |
1076 | */ | |
1077 | if (!cpu_gdt_descr->address) { | |
1078 | cpu_gdt_descr->address = get_zeroed_page(GFP_KERNEL); | |
1079 | if (!cpu_gdt_descr->address) | |
1080 | printk(KERN_CRIT "CPU%d failed to allocate GDT\n", cpu); | |
1081 | ret = -ENOMEM; | |
1082 | goto exit; | |
1083 | } | |
1084 | ||
e1367daf LS |
1085 | info.complete = &done; |
1086 | info.apicid = apicid; | |
1087 | info.cpu = cpu; | |
1088 | INIT_WORK(&task, do_warm_boot_cpu, &info); | |
1089 | ||
1090 | tsc_sync_disabled = 1; | |
1091 | ||
1092 | /* init low mem mapping */ | |
d7271b14 ZA |
1093 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS, |
1094 | KERNEL_PGD_PTRS); | |
e1367daf LS |
1095 | flush_tlb_all(); |
1096 | schedule_work(&task); | |
1097 | wait_for_completion(&done); | |
1098 | ||
1099 | tsc_sync_disabled = 0; | |
1100 | zap_low_mappings(); | |
1101 | ret = 0; | |
1102 | exit: | |
e1367daf LS |
1103 | return ret; |
1104 | } | |
1105 | #endif | |
1106 | ||
1da177e4 LT |
1107 | static void smp_tune_scheduling (void) |
1108 | { | |
1109 | unsigned long cachesize; /* kB */ | |
1110 | unsigned long bandwidth = 350; /* MB/s */ | |
1111 | /* | |
1112 | * Rough estimation for SMP scheduling, this is the number of | |
1113 | * cycles it takes for a fully memory-limited process to flush | |
1114 | * the SMP-local cache. | |
1115 | * | |
1116 | * (For a P5 this pretty much means we will choose another idle | |
1117 | * CPU almost always at wakeup time (this is due to the small | |
1118 | * L1 cache), on PIIs it's around 50-100 usecs, depending on | |
1119 | * the cache size) | |
1120 | */ | |
1121 | ||
1122 | if (!cpu_khz) { | |
1123 | /* | |
1124 | * this basically disables processor-affinity | |
1125 | * scheduling on SMP without a TSC. | |
1126 | */ | |
1127 | return; | |
1128 | } else { | |
1129 | cachesize = boot_cpu_data.x86_cache_size; | |
1130 | if (cachesize == -1) { | |
1131 | cachesize = 16; /* Pentiums, 2x8kB cache */ | |
1132 | bandwidth = 100; | |
1133 | } | |
198e2f18 | 1134 | max_cache_size = cachesize * 1024; |
1da177e4 LT |
1135 | } |
1136 | } | |
1137 | ||
1138 | /* | |
1139 | * Cycle through the processors sending APIC IPIs to boot each. | |
1140 | */ | |
1141 | ||
1142 | static int boot_cpu_logical_apicid; | |
1143 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ | |
1144 | void *xquad_portio; | |
129f6946 AD |
1145 | #ifdef CONFIG_X86_NUMAQ |
1146 | EXPORT_SYMBOL(xquad_portio); | |
1147 | #endif | |
1da177e4 | 1148 | |
1da177e4 LT |
1149 | static void __init smp_boot_cpus(unsigned int max_cpus) |
1150 | { | |
1151 | int apicid, cpu, bit, kicked; | |
1152 | unsigned long bogosum = 0; | |
1153 | ||
1154 | /* | |
1155 | * Setup boot CPU information | |
1156 | */ | |
1157 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1158 | printk("CPU%d: ", 0); | |
1159 | print_cpu_info(&cpu_data[0]); | |
1160 | ||
1e4c85f9 | 1161 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
1162 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1163 | x86_cpu_to_apicid[0] = boot_cpu_physical_apicid; | |
1164 | ||
1165 | current_thread_info()->cpu = 0; | |
1166 | smp_tune_scheduling(); | |
1da177e4 | 1167 | |
94605eff | 1168 | set_cpu_sibling_map(0); |
3dd9d514 | 1169 | |
1da177e4 LT |
1170 | /* |
1171 | * If we couldn't find an SMP configuration at boot time, | |
1172 | * get out of here now! | |
1173 | */ | |
1174 | if (!smp_found_config && !acpi_lapic) { | |
1175 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
1e4c85f9 LT |
1176 | smpboot_clear_io_apic_irqs(); |
1177 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1178 | if (APIC_init_uniprocessor()) | |
1179 | printk(KERN_NOTICE "Local APIC not detected." | |
1180 | " Using dummy APIC emulation.\n"); | |
1181 | map_cpu_to_logical_apicid(); | |
1182 | cpu_set(0, cpu_sibling_map[0]); | |
1183 | cpu_set(0, cpu_core_map[0]); | |
1184 | return; | |
1185 | } | |
1186 | ||
1187 | /* | |
1188 | * Should not be necessary because the MP table should list the boot | |
1189 | * CPU too, but we do it for the sake of robustness anyway. | |
1190 | * Makes no sense to do this check in clustered apic mode, so skip it | |
1191 | */ | |
1192 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1193 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1194 | boot_cpu_physical_apicid); | |
1195 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1196 | } | |
1197 | ||
1198 | /* | |
1199 | * If we couldn't find a local APIC, then get out of here now! | |
1200 | */ | |
1201 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) { | |
1202 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1203 | boot_cpu_physical_apicid); | |
1204 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
1205 | smpboot_clear_io_apic_irqs(); | |
1206 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1207 | cpu_set(0, cpu_sibling_map[0]); | |
1208 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1209 | return; |
1210 | } | |
1211 | ||
1e4c85f9 LT |
1212 | verify_local_APIC(); |
1213 | ||
1da177e4 LT |
1214 | /* |
1215 | * If SMP should be disabled, then really disable it! | |
1216 | */ | |
1e4c85f9 LT |
1217 | if (!max_cpus) { |
1218 | smp_found_config = 0; | |
1219 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); | |
1220 | smpboot_clear_io_apic_irqs(); | |
1221 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1222 | cpu_set(0, cpu_sibling_map[0]); | |
1223 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1224 | return; |
1225 | } | |
1226 | ||
1e4c85f9 LT |
1227 | connect_bsp_APIC(); |
1228 | setup_local_APIC(); | |
1229 | map_cpu_to_logical_apicid(); | |
1230 | ||
1231 | ||
1da177e4 LT |
1232 | setup_portio_remap(); |
1233 | ||
1234 | /* | |
1235 | * Scan the CPU present map and fire up the other CPUs via do_boot_cpu | |
1236 | * | |
1237 | * In clustered apic mode, phys_cpu_present_map is a constructed thus: | |
1238 | * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the | |
1239 | * clustered apic ID. | |
1240 | */ | |
1241 | Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map)); | |
1242 | ||
1243 | kicked = 1; | |
1244 | for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) { | |
1245 | apicid = cpu_present_to_apicid(bit); | |
1246 | /* | |
1247 | * Don't even attempt to start the boot CPU! | |
1248 | */ | |
1249 | if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID)) | |
1250 | continue; | |
1251 | ||
1252 | if (!check_apicid_present(bit)) | |
1253 | continue; | |
1254 | if (max_cpus <= cpucount+1) | |
1255 | continue; | |
1256 | ||
e1367daf | 1257 | if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu)) |
1da177e4 LT |
1258 | printk("CPU #%d not responding - cannot use it.\n", |
1259 | apicid); | |
1260 | else | |
1261 | ++kicked; | |
1262 | } | |
1263 | ||
1264 | /* | |
1265 | * Cleanup possible dangling ends... | |
1266 | */ | |
1267 | smpboot_restore_warm_reset_vector(); | |
1268 | ||
1269 | /* | |
1270 | * Allow the user to impress friends. | |
1271 | */ | |
1272 | Dprintk("Before bogomips.\n"); | |
1273 | for (cpu = 0; cpu < NR_CPUS; cpu++) | |
1274 | if (cpu_isset(cpu, cpu_callout_map)) | |
1275 | bogosum += cpu_data[cpu].loops_per_jiffy; | |
1276 | printk(KERN_INFO | |
1277 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
1278 | cpucount+1, | |
1279 | bogosum/(500000/HZ), | |
1280 | (bogosum/(5000/HZ))%100); | |
1281 | ||
1282 | Dprintk("Before bogocount - setting activated=1.\n"); | |
1283 | ||
1284 | if (smp_b_stepping) | |
1285 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n"); | |
1286 | ||
1287 | /* | |
1288 | * Don't taint if we are running SMP kernel on a single non-MP | |
1289 | * approved Athlon | |
1290 | */ | |
1291 | if (tainted & TAINT_UNSAFE_SMP) { | |
1292 | if (cpucount) | |
1293 | printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n"); | |
1294 | else | |
1295 | tainted &= ~TAINT_UNSAFE_SMP; | |
1296 | } | |
1297 | ||
1298 | Dprintk("Boot done.\n"); | |
1299 | ||
1300 | /* | |
1301 | * construct cpu_sibling_map[], so that we can tell sibling CPUs | |
1302 | * efficiently. | |
1303 | */ | |
3dd9d514 | 1304 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
1da177e4 | 1305 | cpus_clear(cpu_sibling_map[cpu]); |
3dd9d514 AK |
1306 | cpus_clear(cpu_core_map[cpu]); |
1307 | } | |
1da177e4 | 1308 | |
d720803a LS |
1309 | cpu_set(0, cpu_sibling_map[0]); |
1310 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 | 1311 | |
1e4c85f9 LT |
1312 | smpboot_setup_io_apic(); |
1313 | ||
1314 | setup_boot_APIC_clock(); | |
1315 | ||
1da177e4 LT |
1316 | /* |
1317 | * Synchronize the TSC with the AP | |
1318 | */ | |
1319 | if (cpu_has_tsc && cpucount && cpu_khz) | |
1320 | synchronize_tsc_bp(); | |
1321 | } | |
1322 | ||
1323 | /* These are wrappers to interface to the new boot process. Someone | |
1324 | who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */ | |
1325 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
1326 | { | |
f3705136 ZM |
1327 | smp_commenced_mask = cpumask_of_cpu(0); |
1328 | cpu_callin_map = cpumask_of_cpu(0); | |
1329 | mb(); | |
1da177e4 LT |
1330 | smp_boot_cpus(max_cpus); |
1331 | } | |
1332 | ||
1333 | void __devinit smp_prepare_boot_cpu(void) | |
1334 | { | |
1335 | cpu_set(smp_processor_id(), cpu_online_map); | |
1336 | cpu_set(smp_processor_id(), cpu_callout_map); | |
e1367daf | 1337 | cpu_set(smp_processor_id(), cpu_present_map); |
4ad8d383 | 1338 | cpu_set(smp_processor_id(), cpu_possible_map); |
e1367daf | 1339 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
1da177e4 LT |
1340 | } |
1341 | ||
f3705136 | 1342 | #ifdef CONFIG_HOTPLUG_CPU |
e1367daf LS |
1343 | static void |
1344 | remove_siblinginfo(int cpu) | |
1da177e4 | 1345 | { |
e1367daf | 1346 | int sibling; |
94605eff | 1347 | struct cpuinfo_x86 *c = cpu_data; |
e1367daf | 1348 | |
94605eff SS |
1349 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) { |
1350 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1351 | /* | |
1352 | * last thread sibling in this cpu core going down | |
1353 | */ | |
1354 | if (cpus_weight(cpu_sibling_map[cpu]) == 1) | |
1355 | c[sibling].booted_cores--; | |
1356 | } | |
1357 | ||
e1367daf LS |
1358 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) |
1359 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
e1367daf LS |
1360 | cpus_clear(cpu_sibling_map[cpu]); |
1361 | cpus_clear(cpu_core_map[cpu]); | |
4b89aff9 RS |
1362 | c[cpu].phys_proc_id = 0; |
1363 | c[cpu].cpu_core_id = 0; | |
94605eff | 1364 | cpu_clear(cpu, cpu_sibling_setup_map); |
f3705136 ZM |
1365 | } |
1366 | ||
1367 | int __cpu_disable(void) | |
1368 | { | |
1369 | cpumask_t map = cpu_online_map; | |
1370 | int cpu = smp_processor_id(); | |
1371 | ||
1372 | /* | |
1373 | * Perhaps use cpufreq to drop frequency, but that could go | |
1374 | * into generic code. | |
1375 | * | |
1376 | * We won't take down the boot processor on i386 due to some | |
1377 | * interrupts only being able to be serviced by the BSP. | |
1378 | * Especially so if we're not using an IOAPIC -zwane | |
1379 | */ | |
1380 | if (cpu == 0) | |
1381 | return -EBUSY; | |
4038f901 SL |
1382 | if (nmi_watchdog == NMI_LOCAL_APIC) |
1383 | stop_apic_nmi_watchdog(NULL); | |
5e9ef02e | 1384 | clear_local_APIC(); |
f3705136 ZM |
1385 | /* Allow any queued timer interrupts to get serviced */ |
1386 | local_irq_enable(); | |
1387 | mdelay(1); | |
1388 | local_irq_disable(); | |
1389 | ||
e1367daf LS |
1390 | remove_siblinginfo(cpu); |
1391 | ||
f3705136 ZM |
1392 | cpu_clear(cpu, map); |
1393 | fixup_irqs(map); | |
1394 | /* It's now safe to remove this processor from the online map */ | |
1395 | cpu_clear(cpu, cpu_online_map); | |
1396 | return 0; | |
1397 | } | |
1398 | ||
1399 | void __cpu_die(unsigned int cpu) | |
1400 | { | |
1401 | /* We don't do anything here: idle task is faking death itself. */ | |
1402 | unsigned int i; | |
1403 | ||
1404 | for (i = 0; i < 10; i++) { | |
1405 | /* They ack this in play_dead by setting CPU_DEAD */ | |
e1367daf LS |
1406 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1407 | printk ("CPU %d is now offline\n", cpu); | |
9a0b5817 GH |
1408 | if (1 == num_online_cpus()) |
1409 | alternatives_smp_switch(0); | |
f3705136 | 1410 | return; |
e1367daf | 1411 | } |
aeb8397b | 1412 | msleep(100); |
1da177e4 | 1413 | } |
f3705136 ZM |
1414 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1415 | } | |
1416 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1417 | int __cpu_disable(void) | |
1418 | { | |
1419 | return -ENOSYS; | |
1420 | } | |
1da177e4 | 1421 | |
f3705136 ZM |
1422 | void __cpu_die(unsigned int cpu) |
1423 | { | |
1424 | /* We said "no" in __cpu_disable */ | |
1425 | BUG(); | |
1426 | } | |
1427 | #endif /* CONFIG_HOTPLUG_CPU */ | |
1428 | ||
1429 | int __devinit __cpu_up(unsigned int cpu) | |
1430 | { | |
34f361ad AR |
1431 | #ifdef CONFIG_HOTPLUG_CPU |
1432 | int ret=0; | |
1433 | ||
1434 | /* | |
1435 | * We do warm boot only on cpus that had booted earlier | |
1436 | * Otherwise cold boot is all handled from smp_boot_cpus(). | |
1437 | * cpu_callin_map is set during AP kickstart process. Its reset | |
1438 | * when a cpu is taken offline from cpu_exit_clear(). | |
1439 | */ | |
1440 | if (!cpu_isset(cpu, cpu_callin_map)) | |
1441 | ret = __smp_prepare_cpu(cpu); | |
1442 | ||
1443 | if (ret) | |
1444 | return -EIO; | |
1445 | #endif | |
1446 | ||
1da177e4 LT |
1447 | /* In case one didn't come up */ |
1448 | if (!cpu_isset(cpu, cpu_callin_map)) { | |
f3705136 | 1449 | printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu); |
1da177e4 LT |
1450 | local_irq_enable(); |
1451 | return -EIO; | |
1452 | } | |
1453 | ||
1454 | local_irq_enable(); | |
e1367daf | 1455 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
1da177e4 LT |
1456 | /* Unleash the CPU! */ |
1457 | cpu_set(cpu, smp_commenced_mask); | |
1458 | while (!cpu_isset(cpu, cpu_online_map)) | |
18698917 | 1459 | cpu_relax(); |
1da177e4 LT |
1460 | return 0; |
1461 | } | |
1462 | ||
1463 | void __init smp_cpus_done(unsigned int max_cpus) | |
1464 | { | |
1465 | #ifdef CONFIG_X86_IO_APIC | |
1466 | setup_ioapic_dest(); | |
1467 | #endif | |
1468 | zap_low_mappings(); | |
e1367daf | 1469 | #ifndef CONFIG_HOTPLUG_CPU |
1da177e4 LT |
1470 | /* |
1471 | * Disable executability of the SMP trampoline: | |
1472 | */ | |
1473 | set_kernel_exec((unsigned long)trampoline_base, trampoline_exec); | |
e1367daf | 1474 | #endif |
1da177e4 LT |
1475 | } |
1476 | ||
1477 | void __init smp_intr_init(void) | |
1478 | { | |
1479 | /* | |
1480 | * IRQ0 must be given a fixed assignment and initialized, | |
1481 | * because it's used before the IO-APIC is set up. | |
1482 | */ | |
1483 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1484 | ||
1485 | /* | |
1486 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1487 | * IPI, driven by wakeup. | |
1488 | */ | |
1489 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
1490 | ||
1491 | /* IPI for invalidation */ | |
1492 | set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); | |
1493 | ||
1494 | /* IPI for generic function call */ | |
1495 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
1496 | } | |
1a3f239d RR |
1497 | |
1498 | /* | |
1499 | * If the BIOS enumerates physical processors before logical, | |
1500 | * maxcpus=N at enumeration-time can be used to disable HT. | |
1501 | */ | |
1502 | static int __init parse_maxcpus(char *arg) | |
1503 | { | |
1504 | extern unsigned int maxcpus; | |
1505 | ||
1506 | maxcpus = simple_strtoul(arg, NULL, 0); | |
1507 | return 0; | |
1508 | } | |
1509 | early_param("maxcpus", parse_maxcpus); |