Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * | |
7 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
8 | * whom a great many thanks are extended. | |
9 | * | |
10 | * Thanks to Intel for making available several different Pentium, | |
11 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
12 | * Original development of Linux SMP code supported by Caldera. | |
13 | * | |
14 | * This code is released under the GNU General Public License version 2 or | |
15 | * later. | |
16 | * | |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. */ | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/config.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/kernel.h> | |
40 | ||
41 | #include <linux/mm.h> | |
42 | #include <linux/sched.h> | |
43 | #include <linux/kernel_stat.h> | |
44 | #include <linux/smp_lock.h> | |
45 | #include <linux/irq.h> | |
46 | #include <linux/bootmem.h> | |
f3705136 ZM |
47 | #include <linux/notifier.h> |
48 | #include <linux/cpu.h> | |
49 | #include <linux/percpu.h> | |
1da177e4 LT |
50 | |
51 | #include <linux/delay.h> | |
52 | #include <linux/mc146818rtc.h> | |
53 | #include <asm/tlbflush.h> | |
54 | #include <asm/desc.h> | |
55 | #include <asm/arch_hooks.h> | |
56 | ||
57 | #include <mach_apic.h> | |
58 | #include <mach_wakecpu.h> | |
59 | #include <smpboot_hooks.h> | |
60 | ||
61 | /* Set if we find a B stepping CPU */ | |
62 | static int __initdata smp_b_stepping; | |
63 | ||
64 | /* Number of siblings per CPU package */ | |
65 | int smp_num_siblings = 1; | |
129f6946 AD |
66 | #ifdef CONFIG_X86_HT |
67 | EXPORT_SYMBOL(smp_num_siblings); | |
68 | #endif | |
1da177e4 LT |
69 | int phys_proc_id[NR_CPUS]; /* Package ID of each logical CPU */ |
70 | EXPORT_SYMBOL(phys_proc_id); | |
3dd9d514 AK |
71 | int cpu_core_id[NR_CPUS]; /* Core ID of each logical CPU */ |
72 | EXPORT_SYMBOL(cpu_core_id); | |
1da177e4 LT |
73 | |
74 | /* bitmap of online cpus */ | |
75 | cpumask_t cpu_online_map; | |
129f6946 | 76 | EXPORT_SYMBOL(cpu_online_map); |
1da177e4 LT |
77 | |
78 | cpumask_t cpu_callin_map; | |
79 | cpumask_t cpu_callout_map; | |
129f6946 | 80 | EXPORT_SYMBOL(cpu_callout_map); |
1da177e4 LT |
81 | static cpumask_t smp_commenced_mask; |
82 | ||
83 | /* Per CPU bogomips and other parameters */ | |
84 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
129f6946 | 85 | EXPORT_SYMBOL(cpu_data); |
1da177e4 LT |
86 | |
87 | u8 x86_cpu_to_apicid[NR_CPUS] = | |
88 | { [0 ... NR_CPUS-1] = 0xff }; | |
89 | EXPORT_SYMBOL(x86_cpu_to_apicid); | |
90 | ||
91 | /* | |
92 | * Trampoline 80x86 program as an array. | |
93 | */ | |
94 | ||
95 | extern unsigned char trampoline_data []; | |
96 | extern unsigned char trampoline_end []; | |
97 | static unsigned char *trampoline_base; | |
98 | static int trampoline_exec; | |
99 | ||
100 | static void map_cpu_to_logical_apicid(void); | |
101 | ||
f3705136 ZM |
102 | /* State of each CPU. */ |
103 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
104 | ||
1da177e4 LT |
105 | /* |
106 | * Currently trivial. Write the real->protected mode | |
107 | * bootstrap into the page concerned. The caller | |
108 | * has made sure it's suitably aligned. | |
109 | */ | |
110 | ||
111 | static unsigned long __init setup_trampoline(void) | |
112 | { | |
113 | memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data); | |
114 | return virt_to_phys(trampoline_base); | |
115 | } | |
116 | ||
117 | /* | |
118 | * We are called very early to get the low memory for the | |
119 | * SMP bootup trampoline page. | |
120 | */ | |
121 | void __init smp_alloc_memory(void) | |
122 | { | |
123 | trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE); | |
124 | /* | |
125 | * Has to be in very low memory so we can execute | |
126 | * real-mode AP code. | |
127 | */ | |
128 | if (__pa(trampoline_base) >= 0x9F000) | |
129 | BUG(); | |
130 | /* | |
131 | * Make the SMP trampoline executable: | |
132 | */ | |
133 | trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1); | |
134 | } | |
135 | ||
136 | /* | |
137 | * The bootstrap kernel entry code has set these up. Save them for | |
138 | * a given CPU | |
139 | */ | |
140 | ||
141 | static void __init smp_store_cpu_info(int id) | |
142 | { | |
143 | struct cpuinfo_x86 *c = cpu_data + id; | |
144 | ||
145 | *c = boot_cpu_data; | |
146 | if (id!=0) | |
147 | identify_cpu(c); | |
148 | /* | |
149 | * Mask B, Pentium, but not Pentium MMX | |
150 | */ | |
151 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
152 | c->x86 == 5 && | |
153 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
154 | c->x86_model <= 3) | |
155 | /* | |
156 | * Remember we have B step Pentia with bugs | |
157 | */ | |
158 | smp_b_stepping = 1; | |
159 | ||
160 | /* | |
161 | * Certain Athlons might work (for various values of 'work') in SMP | |
162 | * but they are not certified as MP capable. | |
163 | */ | |
164 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
165 | ||
166 | /* Athlon 660/661 is valid. */ | |
167 | if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1))) | |
168 | goto valid_k7; | |
169 | ||
170 | /* Duron 670 is valid */ | |
171 | if ((c->x86_model==7) && (c->x86_mask==0)) | |
172 | goto valid_k7; | |
173 | ||
174 | /* | |
175 | * Athlon 662, Duron 671, and Athlon >model 7 have capability bit. | |
176 | * It's worth noting that the A5 stepping (662) of some Athlon XP's | |
177 | * have the MP bit set. | |
178 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more. | |
179 | */ | |
180 | if (((c->x86_model==6) && (c->x86_mask>=2)) || | |
181 | ((c->x86_model==7) && (c->x86_mask>=1)) || | |
182 | (c->x86_model> 7)) | |
183 | if (cpu_has_mp) | |
184 | goto valid_k7; | |
185 | ||
186 | /* If we get here, it's not a certified SMP capable AMD system. */ | |
187 | tainted |= TAINT_UNSAFE_SMP; | |
188 | } | |
189 | ||
190 | valid_k7: | |
191 | ; | |
192 | } | |
193 | ||
194 | /* | |
195 | * TSC synchronization. | |
196 | * | |
197 | * We first check whether all CPUs have their TSC's synchronized, | |
198 | * then we print a warning if not, and always resync. | |
199 | */ | |
200 | ||
201 | static atomic_t tsc_start_flag = ATOMIC_INIT(0); | |
202 | static atomic_t tsc_count_start = ATOMIC_INIT(0); | |
203 | static atomic_t tsc_count_stop = ATOMIC_INIT(0); | |
204 | static unsigned long long tsc_values[NR_CPUS]; | |
205 | ||
206 | #define NR_LOOPS 5 | |
207 | ||
208 | static void __init synchronize_tsc_bp (void) | |
209 | { | |
210 | int i; | |
211 | unsigned long long t0; | |
212 | unsigned long long sum, avg; | |
213 | long long delta; | |
a3a255e7 | 214 | unsigned int one_usec; |
1da177e4 LT |
215 | int buggy = 0; |
216 | ||
217 | printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus()); | |
218 | ||
219 | /* convert from kcyc/sec to cyc/usec */ | |
220 | one_usec = cpu_khz / 1000; | |
221 | ||
222 | atomic_set(&tsc_start_flag, 1); | |
223 | wmb(); | |
224 | ||
225 | /* | |
226 | * We loop a few times to get a primed instruction cache, | |
227 | * then the last pass is more or less synchronized and | |
228 | * the BP and APs set their cycle counters to zero all at | |
229 | * once. This reduces the chance of having random offsets | |
230 | * between the processors, and guarantees that the maximum | |
231 | * delay between the cycle counters is never bigger than | |
232 | * the latency of information-passing (cachelines) between | |
233 | * two CPUs. | |
234 | */ | |
235 | for (i = 0; i < NR_LOOPS; i++) { | |
236 | /* | |
237 | * all APs synchronize but they loop on '== num_cpus' | |
238 | */ | |
239 | while (atomic_read(&tsc_count_start) != num_booting_cpus()-1) | |
240 | mb(); | |
241 | atomic_set(&tsc_count_stop, 0); | |
242 | wmb(); | |
243 | /* | |
244 | * this lets the APs save their current TSC: | |
245 | */ | |
246 | atomic_inc(&tsc_count_start); | |
247 | ||
248 | rdtscll(tsc_values[smp_processor_id()]); | |
249 | /* | |
250 | * We clear the TSC in the last loop: | |
251 | */ | |
252 | if (i == NR_LOOPS-1) | |
253 | write_tsc(0, 0); | |
254 | ||
255 | /* | |
256 | * Wait for all APs to leave the synchronization point: | |
257 | */ | |
258 | while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1) | |
259 | mb(); | |
260 | atomic_set(&tsc_count_start, 0); | |
261 | wmb(); | |
262 | atomic_inc(&tsc_count_stop); | |
263 | } | |
264 | ||
265 | sum = 0; | |
266 | for (i = 0; i < NR_CPUS; i++) { | |
267 | if (cpu_isset(i, cpu_callout_map)) { | |
268 | t0 = tsc_values[i]; | |
269 | sum += t0; | |
270 | } | |
271 | } | |
272 | avg = sum; | |
273 | do_div(avg, num_booting_cpus()); | |
274 | ||
275 | sum = 0; | |
276 | for (i = 0; i < NR_CPUS; i++) { | |
277 | if (!cpu_isset(i, cpu_callout_map)) | |
278 | continue; | |
279 | delta = tsc_values[i] - avg; | |
280 | if (delta < 0) | |
281 | delta = -delta; | |
282 | /* | |
283 | * We report bigger than 2 microseconds clock differences. | |
284 | */ | |
285 | if (delta > 2*one_usec) { | |
286 | long realdelta; | |
287 | if (!buggy) { | |
288 | buggy = 1; | |
289 | printk("\n"); | |
290 | } | |
291 | realdelta = delta; | |
292 | do_div(realdelta, one_usec); | |
293 | if (tsc_values[i] < avg) | |
294 | realdelta = -realdelta; | |
295 | ||
296 | printk(KERN_INFO "CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta); | |
297 | } | |
298 | ||
299 | sum += delta; | |
300 | } | |
301 | if (!buggy) | |
302 | printk("passed.\n"); | |
303 | } | |
304 | ||
305 | static void __init synchronize_tsc_ap (void) | |
306 | { | |
307 | int i; | |
308 | ||
309 | /* | |
310 | * Not every cpu is online at the time | |
311 | * this gets called, so we first wait for the BP to | |
312 | * finish SMP initialization: | |
313 | */ | |
314 | while (!atomic_read(&tsc_start_flag)) mb(); | |
315 | ||
316 | for (i = 0; i < NR_LOOPS; i++) { | |
317 | atomic_inc(&tsc_count_start); | |
318 | while (atomic_read(&tsc_count_start) != num_booting_cpus()) | |
319 | mb(); | |
320 | ||
321 | rdtscll(tsc_values[smp_processor_id()]); | |
322 | if (i == NR_LOOPS-1) | |
323 | write_tsc(0, 0); | |
324 | ||
325 | atomic_inc(&tsc_count_stop); | |
326 | while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb(); | |
327 | } | |
328 | } | |
329 | #undef NR_LOOPS | |
330 | ||
331 | extern void calibrate_delay(void); | |
332 | ||
333 | static atomic_t init_deasserted; | |
334 | ||
335 | static void __init smp_callin(void) | |
336 | { | |
337 | int cpuid, phys_id; | |
338 | unsigned long timeout; | |
339 | ||
340 | /* | |
341 | * If waken up by an INIT in an 82489DX configuration | |
342 | * we may get here before an INIT-deassert IPI reaches | |
343 | * our local APIC. We have to wait for the IPI or we'll | |
344 | * lock up on an APIC access. | |
345 | */ | |
346 | wait_for_init_deassert(&init_deasserted); | |
347 | ||
348 | /* | |
349 | * (This works even if the APIC is not enabled.) | |
350 | */ | |
351 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
352 | cpuid = smp_processor_id(); | |
353 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
354 | printk("huh, phys CPU#%d, CPU#%d already present??\n", | |
355 | phys_id, cpuid); | |
356 | BUG(); | |
357 | } | |
358 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
359 | ||
360 | /* | |
361 | * STARTUP IPIs are fragile beasts as they might sometimes | |
362 | * trigger some glue motherboard logic. Complete APIC bus | |
363 | * silence for 1 second, this overestimates the time the | |
364 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
365 | * by a factor of two. This should be enough. | |
366 | */ | |
367 | ||
368 | /* | |
369 | * Waiting 2s total for startup (udelay is not yet working) | |
370 | */ | |
371 | timeout = jiffies + 2*HZ; | |
372 | while (time_before(jiffies, timeout)) { | |
373 | /* | |
374 | * Has the boot CPU finished it's STARTUP sequence? | |
375 | */ | |
376 | if (cpu_isset(cpuid, cpu_callout_map)) | |
377 | break; | |
378 | rep_nop(); | |
379 | } | |
380 | ||
381 | if (!time_before(jiffies, timeout)) { | |
382 | printk("BUG: CPU%d started up but did not get a callout!\n", | |
383 | cpuid); | |
384 | BUG(); | |
385 | } | |
386 | ||
387 | /* | |
388 | * the boot CPU has finished the init stage and is spinning | |
389 | * on callin_map until we finish. We are free to set up this | |
390 | * CPU, first the APIC. (this is probably redundant on most | |
391 | * boards) | |
392 | */ | |
393 | ||
394 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
395 | smp_callin_clear_local_apic(); | |
396 | setup_local_APIC(); | |
397 | map_cpu_to_logical_apicid(); | |
398 | ||
399 | /* | |
400 | * Get our bogomips. | |
401 | */ | |
402 | calibrate_delay(); | |
403 | Dprintk("Stack at about %p\n",&cpuid); | |
404 | ||
405 | /* | |
406 | * Save our processor parameters | |
407 | */ | |
408 | smp_store_cpu_info(cpuid); | |
409 | ||
410 | disable_APIC_timer(); | |
411 | ||
412 | /* | |
413 | * Allow the master to continue. | |
414 | */ | |
415 | cpu_set(cpuid, cpu_callin_map); | |
416 | ||
417 | /* | |
418 | * Synchronize the TSC with the BP | |
419 | */ | |
420 | if (cpu_has_tsc && cpu_khz) | |
421 | synchronize_tsc_ap(); | |
422 | } | |
423 | ||
424 | static int cpucount; | |
425 | ||
426 | /* | |
427 | * Activate a secondary processor. | |
428 | */ | |
429 | static void __init start_secondary(void *unused) | |
430 | { | |
431 | /* | |
432 | * Dont put anything before smp_callin(), SMP | |
433 | * booting is too fragile that we want to limit the | |
434 | * things done here to the most necessary things. | |
435 | */ | |
436 | cpu_init(); | |
437 | smp_callin(); | |
438 | while (!cpu_isset(smp_processor_id(), smp_commenced_mask)) | |
439 | rep_nop(); | |
440 | setup_secondary_APIC_clock(); | |
441 | if (nmi_watchdog == NMI_IO_APIC) { | |
442 | disable_8259A_irq(0); | |
443 | enable_NMI_through_LVT0(NULL); | |
444 | enable_8259A_irq(0); | |
445 | } | |
446 | enable_APIC_timer(); | |
447 | /* | |
448 | * low-memory mappings have been cleared, flush them from | |
449 | * the local TLBs too. | |
450 | */ | |
451 | local_flush_tlb(); | |
6fe940d6 LS |
452 | |
453 | /* | |
454 | * We need to hold call_lock, so there is no inconsistency | |
455 | * between the time smp_call_function() determines number of | |
456 | * IPI receipients, and the time when the determination is made | |
457 | * for which cpus receive the IPI. Holding this | |
458 | * lock helps us to not include this cpu in a currently in progress | |
459 | * smp_call_function(). | |
460 | */ | |
461 | lock_ipi_call_lock(); | |
1da177e4 | 462 | cpu_set(smp_processor_id(), cpu_online_map); |
6fe940d6 | 463 | unlock_ipi_call_lock(); |
1da177e4 LT |
464 | |
465 | /* We can take interrupts now: we're officially "up". */ | |
466 | local_irq_enable(); | |
467 | ||
468 | wmb(); | |
469 | cpu_idle(); | |
470 | } | |
471 | ||
472 | /* | |
473 | * Everything has been set up for the secondary | |
474 | * CPUs - they just need to reload everything | |
475 | * from the task structure | |
476 | * This function must not return. | |
477 | */ | |
478 | void __init initialize_secondary(void) | |
479 | { | |
480 | /* | |
481 | * We don't actually need to load the full TSS, | |
482 | * basically just the stack pointer and the eip. | |
483 | */ | |
484 | ||
485 | asm volatile( | |
486 | "movl %0,%%esp\n\t" | |
487 | "jmp *%1" | |
488 | : | |
489 | :"r" (current->thread.esp),"r" (current->thread.eip)); | |
490 | } | |
491 | ||
492 | extern struct { | |
493 | void * esp; | |
494 | unsigned short ss; | |
495 | } stack_start; | |
496 | ||
497 | #ifdef CONFIG_NUMA | |
498 | ||
499 | /* which logical CPUs are on which nodes */ | |
500 | cpumask_t node_2_cpu_mask[MAX_NUMNODES] = | |
501 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; | |
502 | /* which node each logical CPU is on */ | |
503 | int cpu_2_node[NR_CPUS] = { [0 ... NR_CPUS-1] = 0 }; | |
504 | EXPORT_SYMBOL(cpu_2_node); | |
505 | ||
506 | /* set up a mapping between cpu and node. */ | |
507 | static inline void map_cpu_to_node(int cpu, int node) | |
508 | { | |
509 | printk("Mapping cpu %d to node %d\n", cpu, node); | |
510 | cpu_set(cpu, node_2_cpu_mask[node]); | |
511 | cpu_2_node[cpu] = node; | |
512 | } | |
513 | ||
514 | /* undo a mapping between cpu and node. */ | |
515 | static inline void unmap_cpu_to_node(int cpu) | |
516 | { | |
517 | int node; | |
518 | ||
519 | printk("Unmapping cpu %d from all nodes\n", cpu); | |
520 | for (node = 0; node < MAX_NUMNODES; node ++) | |
521 | cpu_clear(cpu, node_2_cpu_mask[node]); | |
522 | cpu_2_node[cpu] = 0; | |
523 | } | |
524 | #else /* !CONFIG_NUMA */ | |
525 | ||
526 | #define map_cpu_to_node(cpu, node) ({}) | |
527 | #define unmap_cpu_to_node(cpu) ({}) | |
528 | ||
529 | #endif /* CONFIG_NUMA */ | |
530 | ||
531 | u8 cpu_2_logical_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID }; | |
532 | ||
533 | static void map_cpu_to_logical_apicid(void) | |
534 | { | |
535 | int cpu = smp_processor_id(); | |
536 | int apicid = logical_smp_processor_id(); | |
537 | ||
538 | cpu_2_logical_apicid[cpu] = apicid; | |
539 | map_cpu_to_node(cpu, apicid_to_node(apicid)); | |
540 | } | |
541 | ||
542 | static void unmap_cpu_to_logical_apicid(int cpu) | |
543 | { | |
544 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
545 | unmap_cpu_to_node(cpu); | |
546 | } | |
547 | ||
548 | #if APIC_DEBUG | |
549 | static inline void __inquire_remote_apic(int apicid) | |
550 | { | |
551 | int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
552 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
553 | int timeout, status; | |
554 | ||
555 | printk("Inquiring remote APIC #%d...\n", apicid); | |
556 | ||
557 | for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) { | |
558 | printk("... APIC #%d %s: ", apicid, names[i]); | |
559 | ||
560 | /* | |
561 | * Wait for idle. | |
562 | */ | |
563 | apic_wait_icr_idle(); | |
564 | ||
565 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
566 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
567 | ||
568 | timeout = 0; | |
569 | do { | |
570 | udelay(100); | |
571 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
572 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
573 | ||
574 | switch (status) { | |
575 | case APIC_ICR_RR_VALID: | |
576 | status = apic_read(APIC_RRR); | |
577 | printk("%08x\n", status); | |
578 | break; | |
579 | default: | |
580 | printk("failed\n"); | |
581 | } | |
582 | } | |
583 | } | |
584 | #endif | |
585 | ||
586 | #ifdef WAKE_SECONDARY_VIA_NMI | |
587 | /* | |
588 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
589 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
590 | * won't ... remember to clear down the APIC, etc later. | |
591 | */ | |
592 | static int __init | |
593 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) | |
594 | { | |
595 | unsigned long send_status = 0, accept_status = 0; | |
596 | int timeout, maxlvt; | |
597 | ||
598 | /* Target chip */ | |
599 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
600 | ||
601 | /* Boot on the stack */ | |
602 | /* Kick the second */ | |
603 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
604 | ||
605 | Dprintk("Waiting for send to finish...\n"); | |
606 | timeout = 0; | |
607 | do { | |
608 | Dprintk("+"); | |
609 | udelay(100); | |
610 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
611 | } while (send_status && (timeout++ < 1000)); | |
612 | ||
613 | /* | |
614 | * Give the other CPU some time to accept the IPI. | |
615 | */ | |
616 | udelay(200); | |
617 | /* | |
618 | * Due to the Pentium erratum 3AP. | |
619 | */ | |
620 | maxlvt = get_maxlvt(); | |
621 | if (maxlvt > 3) { | |
622 | apic_read_around(APIC_SPIV); | |
623 | apic_write(APIC_ESR, 0); | |
624 | } | |
625 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
626 | Dprintk("NMI sent.\n"); | |
627 | ||
628 | if (send_status) | |
629 | printk("APIC never delivered???\n"); | |
630 | if (accept_status) | |
631 | printk("APIC delivery error (%lx).\n", accept_status); | |
632 | ||
633 | return (send_status | accept_status); | |
634 | } | |
635 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
636 | ||
637 | #ifdef WAKE_SECONDARY_VIA_INIT | |
638 | static int __init | |
639 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) | |
640 | { | |
641 | unsigned long send_status = 0, accept_status = 0; | |
642 | int maxlvt, timeout, num_starts, j; | |
643 | ||
644 | /* | |
645 | * Be paranoid about clearing APIC errors. | |
646 | */ | |
647 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
648 | apic_read_around(APIC_SPIV); | |
649 | apic_write(APIC_ESR, 0); | |
650 | apic_read(APIC_ESR); | |
651 | } | |
652 | ||
653 | Dprintk("Asserting INIT.\n"); | |
654 | ||
655 | /* | |
656 | * Turn INIT on target chip | |
657 | */ | |
658 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
659 | ||
660 | /* | |
661 | * Send IPI | |
662 | */ | |
663 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
664 | | APIC_DM_INIT); | |
665 | ||
666 | Dprintk("Waiting for send to finish...\n"); | |
667 | timeout = 0; | |
668 | do { | |
669 | Dprintk("+"); | |
670 | udelay(100); | |
671 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
672 | } while (send_status && (timeout++ < 1000)); | |
673 | ||
674 | mdelay(10); | |
675 | ||
676 | Dprintk("Deasserting INIT.\n"); | |
677 | ||
678 | /* Target chip */ | |
679 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
680 | ||
681 | /* Send IPI */ | |
682 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
683 | ||
684 | Dprintk("Waiting for send to finish...\n"); | |
685 | timeout = 0; | |
686 | do { | |
687 | Dprintk("+"); | |
688 | udelay(100); | |
689 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
690 | } while (send_status && (timeout++ < 1000)); | |
691 | ||
692 | atomic_set(&init_deasserted, 1); | |
693 | ||
694 | /* | |
695 | * Should we send STARTUP IPIs ? | |
696 | * | |
697 | * Determine this based on the APIC version. | |
698 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
699 | */ | |
700 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
701 | num_starts = 2; | |
702 | else | |
703 | num_starts = 0; | |
704 | ||
705 | /* | |
706 | * Run STARTUP IPI loop. | |
707 | */ | |
708 | Dprintk("#startup loops: %d.\n", num_starts); | |
709 | ||
710 | maxlvt = get_maxlvt(); | |
711 | ||
712 | for (j = 1; j <= num_starts; j++) { | |
713 | Dprintk("Sending STARTUP #%d.\n",j); | |
714 | apic_read_around(APIC_SPIV); | |
715 | apic_write(APIC_ESR, 0); | |
716 | apic_read(APIC_ESR); | |
717 | Dprintk("After apic_write.\n"); | |
718 | ||
719 | /* | |
720 | * STARTUP IPI | |
721 | */ | |
722 | ||
723 | /* Target chip */ | |
724 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
725 | ||
726 | /* Boot on the stack */ | |
727 | /* Kick the second */ | |
728 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
729 | | (start_eip >> 12)); | |
730 | ||
731 | /* | |
732 | * Give the other CPU some time to accept the IPI. | |
733 | */ | |
734 | udelay(300); | |
735 | ||
736 | Dprintk("Startup point 1.\n"); | |
737 | ||
738 | Dprintk("Waiting for send to finish...\n"); | |
739 | timeout = 0; | |
740 | do { | |
741 | Dprintk("+"); | |
742 | udelay(100); | |
743 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
744 | } while (send_status && (timeout++ < 1000)); | |
745 | ||
746 | /* | |
747 | * Give the other CPU some time to accept the IPI. | |
748 | */ | |
749 | udelay(200); | |
750 | /* | |
751 | * Due to the Pentium erratum 3AP. | |
752 | */ | |
753 | if (maxlvt > 3) { | |
754 | apic_read_around(APIC_SPIV); | |
755 | apic_write(APIC_ESR, 0); | |
756 | } | |
757 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
758 | if (send_status || accept_status) | |
759 | break; | |
760 | } | |
761 | Dprintk("After Startup.\n"); | |
762 | ||
763 | if (send_status) | |
764 | printk("APIC never delivered???\n"); | |
765 | if (accept_status) | |
766 | printk("APIC delivery error (%lx).\n", accept_status); | |
767 | ||
768 | return (send_status | accept_status); | |
769 | } | |
770 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
771 | ||
772 | extern cpumask_t cpu_initialized; | |
773 | ||
774 | static int __init do_boot_cpu(int apicid) | |
775 | /* | |
776 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
777 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
778 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
779 | */ | |
780 | { | |
781 | struct task_struct *idle; | |
782 | unsigned long boot_error; | |
783 | int timeout, cpu; | |
784 | unsigned long start_eip; | |
785 | unsigned short nmi_high = 0, nmi_low = 0; | |
786 | ||
787 | cpu = ++cpucount; | |
788 | /* | |
789 | * We can't use kernel_thread since we must avoid to | |
790 | * reschedule the child. | |
791 | */ | |
792 | idle = fork_idle(cpu); | |
793 | if (IS_ERR(idle)) | |
794 | panic("failed fork for CPU %d", cpu); | |
795 | idle->thread.eip = (unsigned long) start_secondary; | |
796 | /* start_eip had better be page-aligned! */ | |
797 | start_eip = setup_trampoline(); | |
798 | ||
799 | /* So we see what's up */ | |
800 | printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip); | |
801 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
802 | stack_start.esp = (void *) idle->thread.esp; | |
803 | ||
804 | irq_ctx_init(cpu); | |
805 | ||
806 | /* | |
807 | * This grunge runs the startup process for | |
808 | * the targeted processor. | |
809 | */ | |
810 | ||
811 | atomic_set(&init_deasserted, 0); | |
812 | ||
813 | Dprintk("Setting warm reset code and vector.\n"); | |
814 | ||
815 | store_NMI_vector(&nmi_high, &nmi_low); | |
816 | ||
817 | smpboot_setup_warm_reset_vector(start_eip); | |
818 | ||
819 | /* | |
820 | * Starting actual IPI sequence... | |
821 | */ | |
822 | boot_error = wakeup_secondary_cpu(apicid, start_eip); | |
823 | ||
824 | if (!boot_error) { | |
825 | /* | |
826 | * allow APs to start initializing. | |
827 | */ | |
828 | Dprintk("Before Callout %d.\n", cpu); | |
829 | cpu_set(cpu, cpu_callout_map); | |
830 | Dprintk("After Callout %d.\n", cpu); | |
831 | ||
832 | /* | |
833 | * Wait 5s total for a response | |
834 | */ | |
835 | for (timeout = 0; timeout < 50000; timeout++) { | |
836 | if (cpu_isset(cpu, cpu_callin_map)) | |
837 | break; /* It has booted */ | |
838 | udelay(100); | |
839 | } | |
840 | ||
841 | if (cpu_isset(cpu, cpu_callin_map)) { | |
842 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
843 | Dprintk("OK.\n"); | |
844 | printk("CPU%d: ", cpu); | |
845 | print_cpu_info(&cpu_data[cpu]); | |
846 | Dprintk("CPU has booted.\n"); | |
847 | } else { | |
848 | boot_error= 1; | |
849 | if (*((volatile unsigned char *)trampoline_base) | |
850 | == 0xA5) | |
851 | /* trampoline started but...? */ | |
852 | printk("Stuck ??\n"); | |
853 | else | |
854 | /* trampoline code not run */ | |
855 | printk("Not responding.\n"); | |
856 | inquire_remote_apic(apicid); | |
857 | } | |
858 | } | |
859 | x86_cpu_to_apicid[cpu] = apicid; | |
860 | if (boot_error) { | |
861 | /* Try to put things back the way they were before ... */ | |
862 | unmap_cpu_to_logical_apicid(cpu); | |
863 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
864 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
865 | cpucount--; | |
866 | } | |
867 | ||
868 | /* mark "stuck" area as not stuck */ | |
869 | *((volatile unsigned long *)trampoline_base) = 0; | |
870 | ||
871 | return boot_error; | |
872 | } | |
873 | ||
874 | static void smp_tune_scheduling (void) | |
875 | { | |
876 | unsigned long cachesize; /* kB */ | |
877 | unsigned long bandwidth = 350; /* MB/s */ | |
878 | /* | |
879 | * Rough estimation for SMP scheduling, this is the number of | |
880 | * cycles it takes for a fully memory-limited process to flush | |
881 | * the SMP-local cache. | |
882 | * | |
883 | * (For a P5 this pretty much means we will choose another idle | |
884 | * CPU almost always at wakeup time (this is due to the small | |
885 | * L1 cache), on PIIs it's around 50-100 usecs, depending on | |
886 | * the cache size) | |
887 | */ | |
888 | ||
889 | if (!cpu_khz) { | |
890 | /* | |
891 | * this basically disables processor-affinity | |
892 | * scheduling on SMP without a TSC. | |
893 | */ | |
894 | return; | |
895 | } else { | |
896 | cachesize = boot_cpu_data.x86_cache_size; | |
897 | if (cachesize == -1) { | |
898 | cachesize = 16; /* Pentiums, 2x8kB cache */ | |
899 | bandwidth = 100; | |
900 | } | |
901 | } | |
902 | } | |
903 | ||
904 | /* | |
905 | * Cycle through the processors sending APIC IPIs to boot each. | |
906 | */ | |
907 | ||
908 | static int boot_cpu_logical_apicid; | |
909 | /* Where the IO area was mapped on multiquad, always 0 otherwise */ | |
910 | void *xquad_portio; | |
129f6946 AD |
911 | #ifdef CONFIG_X86_NUMAQ |
912 | EXPORT_SYMBOL(xquad_portio); | |
913 | #endif | |
1da177e4 LT |
914 | |
915 | cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned; | |
129f6946 AD |
916 | #ifdef CONFIG_X86_HT |
917 | EXPORT_SYMBOL(cpu_sibling_map); | |
918 | #endif | |
3dd9d514 | 919 | cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned; |
2df9fa36 | 920 | EXPORT_SYMBOL(cpu_core_map); |
1da177e4 LT |
921 | |
922 | static void __init smp_boot_cpus(unsigned int max_cpus) | |
923 | { | |
924 | int apicid, cpu, bit, kicked; | |
925 | unsigned long bogosum = 0; | |
926 | ||
927 | /* | |
928 | * Setup boot CPU information | |
929 | */ | |
930 | smp_store_cpu_info(0); /* Final full version of the data */ | |
931 | printk("CPU%d: ", 0); | |
932 | print_cpu_info(&cpu_data[0]); | |
933 | ||
934 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
935 | boot_cpu_logical_apicid = logical_smp_processor_id(); | |
936 | x86_cpu_to_apicid[0] = boot_cpu_physical_apicid; | |
937 | ||
938 | current_thread_info()->cpu = 0; | |
939 | smp_tune_scheduling(); | |
940 | cpus_clear(cpu_sibling_map[0]); | |
941 | cpu_set(0, cpu_sibling_map[0]); | |
942 | ||
3dd9d514 AK |
943 | cpus_clear(cpu_core_map[0]); |
944 | cpu_set(0, cpu_core_map[0]); | |
945 | ||
1da177e4 LT |
946 | /* |
947 | * If we couldn't find an SMP configuration at boot time, | |
948 | * get out of here now! | |
949 | */ | |
950 | if (!smp_found_config && !acpi_lapic) { | |
951 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
952 | smpboot_clear_io_apic_irqs(); | |
953 | phys_cpu_present_map = physid_mask_of_physid(0); | |
954 | if (APIC_init_uniprocessor()) | |
955 | printk(KERN_NOTICE "Local APIC not detected." | |
956 | " Using dummy APIC emulation.\n"); | |
957 | map_cpu_to_logical_apicid(); | |
3dd9d514 AK |
958 | cpu_set(0, cpu_sibling_map[0]); |
959 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
960 | return; |
961 | } | |
962 | ||
963 | /* | |
964 | * Should not be necessary because the MP table should list the boot | |
965 | * CPU too, but we do it for the sake of robustness anyway. | |
966 | * Makes no sense to do this check in clustered apic mode, so skip it | |
967 | */ | |
968 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
969 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
970 | boot_cpu_physical_apicid); | |
971 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
972 | } | |
973 | ||
974 | /* | |
975 | * If we couldn't find a local APIC, then get out of here now! | |
976 | */ | |
977 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) { | |
978 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
979 | boot_cpu_physical_apicid); | |
980 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
981 | smpboot_clear_io_apic_irqs(); | |
982 | phys_cpu_present_map = physid_mask_of_physid(0); | |
3dd9d514 AK |
983 | cpu_set(0, cpu_sibling_map[0]); |
984 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
985 | return; |
986 | } | |
987 | ||
988 | verify_local_APIC(); | |
989 | ||
990 | /* | |
991 | * If SMP should be disabled, then really disable it! | |
992 | */ | |
993 | if (!max_cpus) { | |
994 | smp_found_config = 0; | |
995 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); | |
996 | smpboot_clear_io_apic_irqs(); | |
997 | phys_cpu_present_map = physid_mask_of_physid(0); | |
3dd9d514 AK |
998 | cpu_set(0, cpu_sibling_map[0]); |
999 | cpu_set(0, cpu_core_map[0]); | |
1da177e4 LT |
1000 | return; |
1001 | } | |
1002 | ||
1003 | connect_bsp_APIC(); | |
1004 | setup_local_APIC(); | |
1005 | map_cpu_to_logical_apicid(); | |
1006 | ||
1007 | ||
1008 | setup_portio_remap(); | |
1009 | ||
1010 | /* | |
1011 | * Scan the CPU present map and fire up the other CPUs via do_boot_cpu | |
1012 | * | |
1013 | * In clustered apic mode, phys_cpu_present_map is a constructed thus: | |
1014 | * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the | |
1015 | * clustered apic ID. | |
1016 | */ | |
1017 | Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map)); | |
1018 | ||
1019 | kicked = 1; | |
1020 | for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) { | |
1021 | apicid = cpu_present_to_apicid(bit); | |
1022 | /* | |
1023 | * Don't even attempt to start the boot CPU! | |
1024 | */ | |
1025 | if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID)) | |
1026 | continue; | |
1027 | ||
1028 | if (!check_apicid_present(bit)) | |
1029 | continue; | |
1030 | if (max_cpus <= cpucount+1) | |
1031 | continue; | |
1032 | ||
1033 | if (do_boot_cpu(apicid)) | |
1034 | printk("CPU #%d not responding - cannot use it.\n", | |
1035 | apicid); | |
1036 | else | |
1037 | ++kicked; | |
1038 | } | |
1039 | ||
1040 | /* | |
1041 | * Cleanup possible dangling ends... | |
1042 | */ | |
1043 | smpboot_restore_warm_reset_vector(); | |
1044 | ||
1045 | /* | |
1046 | * Allow the user to impress friends. | |
1047 | */ | |
1048 | Dprintk("Before bogomips.\n"); | |
1049 | for (cpu = 0; cpu < NR_CPUS; cpu++) | |
1050 | if (cpu_isset(cpu, cpu_callout_map)) | |
1051 | bogosum += cpu_data[cpu].loops_per_jiffy; | |
1052 | printk(KERN_INFO | |
1053 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
1054 | cpucount+1, | |
1055 | bogosum/(500000/HZ), | |
1056 | (bogosum/(5000/HZ))%100); | |
1057 | ||
1058 | Dprintk("Before bogocount - setting activated=1.\n"); | |
1059 | ||
1060 | if (smp_b_stepping) | |
1061 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n"); | |
1062 | ||
1063 | /* | |
1064 | * Don't taint if we are running SMP kernel on a single non-MP | |
1065 | * approved Athlon | |
1066 | */ | |
1067 | if (tainted & TAINT_UNSAFE_SMP) { | |
1068 | if (cpucount) | |
1069 | printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n"); | |
1070 | else | |
1071 | tainted &= ~TAINT_UNSAFE_SMP; | |
1072 | } | |
1073 | ||
1074 | Dprintk("Boot done.\n"); | |
1075 | ||
1076 | /* | |
1077 | * construct cpu_sibling_map[], so that we can tell sibling CPUs | |
1078 | * efficiently. | |
1079 | */ | |
3dd9d514 | 1080 | for (cpu = 0; cpu < NR_CPUS; cpu++) { |
1da177e4 | 1081 | cpus_clear(cpu_sibling_map[cpu]); |
3dd9d514 AK |
1082 | cpus_clear(cpu_core_map[cpu]); |
1083 | } | |
1da177e4 LT |
1084 | |
1085 | for (cpu = 0; cpu < NR_CPUS; cpu++) { | |
3dd9d514 | 1086 | struct cpuinfo_x86 *c = cpu_data + cpu; |
1da177e4 LT |
1087 | int siblings = 0; |
1088 | int i; | |
1089 | if (!cpu_isset(cpu, cpu_callout_map)) | |
1090 | continue; | |
1091 | ||
1092 | if (smp_num_siblings > 1) { | |
1093 | for (i = 0; i < NR_CPUS; i++) { | |
1094 | if (!cpu_isset(i, cpu_callout_map)) | |
1095 | continue; | |
3dd9d514 | 1096 | if (cpu_core_id[cpu] == cpu_core_id[i]) { |
1da177e4 LT |
1097 | siblings++; |
1098 | cpu_set(i, cpu_sibling_map[cpu]); | |
1099 | } | |
1100 | } | |
1101 | } else { | |
1102 | siblings++; | |
1103 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
1104 | } | |
1105 | ||
49f384b8 | 1106 | if (siblings != smp_num_siblings) { |
1da177e4 | 1107 | printk(KERN_WARNING "WARNING: %d siblings found for CPU%d, should be %d\n", siblings, cpu, smp_num_siblings); |
49f384b8 SS |
1108 | smp_num_siblings = siblings; |
1109 | } | |
3dd9d514 AK |
1110 | |
1111 | if (c->x86_num_cores > 1) { | |
1112 | for (i = 0; i < NR_CPUS; i++) { | |
1113 | if (!cpu_isset(i, cpu_callout_map)) | |
1114 | continue; | |
1115 | if (phys_proc_id[cpu] == phys_proc_id[i]) { | |
1116 | cpu_set(i, cpu_core_map[cpu]); | |
1117 | } | |
1118 | } | |
1119 | } else { | |
1120 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; | |
1121 | } | |
1da177e4 LT |
1122 | } |
1123 | ||
1da177e4 LT |
1124 | smpboot_setup_io_apic(); |
1125 | ||
1126 | setup_boot_APIC_clock(); | |
1127 | ||
1128 | /* | |
1129 | * Synchronize the TSC with the AP | |
1130 | */ | |
1131 | if (cpu_has_tsc && cpucount && cpu_khz) | |
1132 | synchronize_tsc_bp(); | |
1133 | } | |
1134 | ||
1135 | /* These are wrappers to interface to the new boot process. Someone | |
1136 | who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */ | |
1137 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
1138 | { | |
f3705136 ZM |
1139 | smp_commenced_mask = cpumask_of_cpu(0); |
1140 | cpu_callin_map = cpumask_of_cpu(0); | |
1141 | mb(); | |
1da177e4 LT |
1142 | smp_boot_cpus(max_cpus); |
1143 | } | |
1144 | ||
1145 | void __devinit smp_prepare_boot_cpu(void) | |
1146 | { | |
1147 | cpu_set(smp_processor_id(), cpu_online_map); | |
1148 | cpu_set(smp_processor_id(), cpu_callout_map); | |
1149 | } | |
1150 | ||
f3705136 ZM |
1151 | #ifdef CONFIG_HOTPLUG_CPU |
1152 | ||
1153 | /* must be called with the cpucontrol mutex held */ | |
1154 | static int __devinit cpu_enable(unsigned int cpu) | |
1da177e4 | 1155 | { |
f3705136 ZM |
1156 | /* get the target out of its holding state */ |
1157 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
1158 | wmb(); | |
1159 | ||
1160 | /* wait for the processor to ack it. timeout? */ | |
1161 | while (!cpu_online(cpu)) | |
1162 | cpu_relax(); | |
1163 | ||
1164 | fixup_irqs(cpu_online_map); | |
1165 | /* counter the disable in fixup_irqs() */ | |
1166 | local_irq_enable(); | |
1167 | return 0; | |
1168 | } | |
1169 | ||
1170 | int __cpu_disable(void) | |
1171 | { | |
1172 | cpumask_t map = cpu_online_map; | |
1173 | int cpu = smp_processor_id(); | |
1174 | ||
1175 | /* | |
1176 | * Perhaps use cpufreq to drop frequency, but that could go | |
1177 | * into generic code. | |
1178 | * | |
1179 | * We won't take down the boot processor on i386 due to some | |
1180 | * interrupts only being able to be serviced by the BSP. | |
1181 | * Especially so if we're not using an IOAPIC -zwane | |
1182 | */ | |
1183 | if (cpu == 0) | |
1184 | return -EBUSY; | |
1185 | ||
1186 | /* We enable the timer again on the exit path of the death loop */ | |
1187 | disable_APIC_timer(); | |
1188 | /* Allow any queued timer interrupts to get serviced */ | |
1189 | local_irq_enable(); | |
1190 | mdelay(1); | |
1191 | local_irq_disable(); | |
1192 | ||
1193 | cpu_clear(cpu, map); | |
1194 | fixup_irqs(map); | |
1195 | /* It's now safe to remove this processor from the online map */ | |
1196 | cpu_clear(cpu, cpu_online_map); | |
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | void __cpu_die(unsigned int cpu) | |
1201 | { | |
1202 | /* We don't do anything here: idle task is faking death itself. */ | |
1203 | unsigned int i; | |
1204 | ||
1205 | for (i = 0; i < 10; i++) { | |
1206 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1207 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) | |
1208 | return; | |
1209 | current->state = TASK_UNINTERRUPTIBLE; | |
1210 | schedule_timeout(HZ/10); | |
1da177e4 | 1211 | } |
f3705136 ZM |
1212 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1213 | } | |
1214 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1215 | int __cpu_disable(void) | |
1216 | { | |
1217 | return -ENOSYS; | |
1218 | } | |
1da177e4 | 1219 | |
f3705136 ZM |
1220 | void __cpu_die(unsigned int cpu) |
1221 | { | |
1222 | /* We said "no" in __cpu_disable */ | |
1223 | BUG(); | |
1224 | } | |
1225 | #endif /* CONFIG_HOTPLUG_CPU */ | |
1226 | ||
1227 | int __devinit __cpu_up(unsigned int cpu) | |
1228 | { | |
1da177e4 LT |
1229 | /* In case one didn't come up */ |
1230 | if (!cpu_isset(cpu, cpu_callin_map)) { | |
f3705136 | 1231 | printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu); |
1da177e4 LT |
1232 | local_irq_enable(); |
1233 | return -EIO; | |
1234 | } | |
1235 | ||
f3705136 ZM |
1236 | #ifdef CONFIG_HOTPLUG_CPU |
1237 | /* Already up, and in cpu_quiescent now? */ | |
1238 | if (cpu_isset(cpu, smp_commenced_mask)) { | |
1239 | cpu_enable(cpu); | |
1240 | return 0; | |
1241 | } | |
1242 | #endif | |
1243 | ||
1da177e4 LT |
1244 | local_irq_enable(); |
1245 | /* Unleash the CPU! */ | |
1246 | cpu_set(cpu, smp_commenced_mask); | |
1247 | while (!cpu_isset(cpu, cpu_online_map)) | |
1248 | mb(); | |
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | void __init smp_cpus_done(unsigned int max_cpus) | |
1253 | { | |
1254 | #ifdef CONFIG_X86_IO_APIC | |
1255 | setup_ioapic_dest(); | |
1256 | #endif | |
1257 | zap_low_mappings(); | |
1258 | /* | |
1259 | * Disable executability of the SMP trampoline: | |
1260 | */ | |
1261 | set_kernel_exec((unsigned long)trampoline_base, trampoline_exec); | |
1262 | } | |
1263 | ||
1264 | void __init smp_intr_init(void) | |
1265 | { | |
1266 | /* | |
1267 | * IRQ0 must be given a fixed assignment and initialized, | |
1268 | * because it's used before the IO-APIC is set up. | |
1269 | */ | |
1270 | set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); | |
1271 | ||
1272 | /* | |
1273 | * The reschedule interrupt is a CPU-to-CPU reschedule-helper | |
1274 | * IPI, driven by wakeup. | |
1275 | */ | |
1276 | set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt); | |
1277 | ||
1278 | /* IPI for invalidation */ | |
1279 | set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); | |
1280 | ||
1281 | /* IPI for generic function call */ | |
1282 | set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); | |
1283 | } |