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1da177e4 LT |
1 | /* -*- mode: c; c-basic-offset: 8 -*- */ |
2 | ||
3 | /* Copyright (C) 1999,2001 | |
4 | * | |
5 | * Author: J.E.J.Bottomley@HansenPartnership.com | |
6 | * | |
7 | * linux/arch/i386/kernel/voyager_smp.c | |
8 | * | |
9 | * This file provides all the same external entries as smp.c but uses | |
10 | * the voyager hal to provide the functionality | |
11 | */ | |
12 | #include <linux/config.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/mc146818rtc.h> | |
17 | #include <linux/cache.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/smp_lock.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/bootmem.h> | |
23 | #include <linux/completion.h> | |
24 | #include <asm/desc.h> | |
25 | #include <asm/voyager.h> | |
26 | #include <asm/vic.h> | |
27 | #include <asm/mtrr.h> | |
28 | #include <asm/pgalloc.h> | |
29 | #include <asm/tlbflush.h> | |
30 | #include <asm/arch_hooks.h> | |
31 | ||
32 | #include <linux/irq.h> | |
33 | ||
34 | /* TLB state -- visible externally, indexed physically */ | |
35 | DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0 }; | |
36 | ||
37 | /* CPU IRQ affinity -- set to all ones initially */ | |
38 | static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL }; | |
39 | ||
40 | /* per CPU data structure (for /proc/cpuinfo et al), visible externally | |
41 | * indexed physically */ | |
42 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
43 | ||
44 | /* physical ID of the CPU used to boot the system */ | |
45 | unsigned char boot_cpu_id; | |
46 | ||
47 | /* The memory line addresses for the Quad CPIs */ | |
48 | struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned; | |
49 | ||
50 | /* The masks for the Extended VIC processors, filled in by cat_init */ | |
51 | __u32 voyager_extended_vic_processors = 0; | |
52 | ||
53 | /* Masks for the extended Quad processors which cannot be VIC booted */ | |
54 | __u32 voyager_allowed_boot_processors = 0; | |
55 | ||
56 | /* The mask for the Quad Processors (both extended and non-extended) */ | |
57 | __u32 voyager_quad_processors = 0; | |
58 | ||
59 | /* Total count of live CPUs, used in process.c to display | |
60 | * the CPU information and in irq.c for the per CPU irq | |
61 | * activity count. Finally exported by i386_ksyms.c */ | |
62 | static int voyager_extended_cpus = 1; | |
63 | ||
64 | /* Have we found an SMP box - used by time.c to do the profiling | |
65 | interrupt for timeslicing; do not set to 1 until the per CPU timer | |
66 | interrupt is active */ | |
67 | int smp_found_config = 0; | |
68 | ||
69 | /* Used for the invalidate map that's also checked in the spinlock */ | |
70 | static volatile unsigned long smp_invalidate_needed; | |
71 | ||
72 | /* Bitmask of currently online CPUs - used by setup.c for | |
73 | /proc/cpuinfo, visible externally but still physical */ | |
74 | cpumask_t cpu_online_map = CPU_MASK_NONE; | |
75 | ||
76 | /* Bitmask of CPUs present in the system - exported by i386_syms.c, used | |
77 | * by scheduler but indexed physically */ | |
78 | cpumask_t phys_cpu_present_map = CPU_MASK_NONE; | |
79 | ||
80 | ||
81 | /* The internal functions */ | |
82 | static void send_CPI(__u32 cpuset, __u8 cpi); | |
83 | static void ack_CPI(__u8 cpi); | |
84 | static int ack_QIC_CPI(__u8 cpi); | |
85 | static void ack_special_QIC_CPI(__u8 cpi); | |
86 | static void ack_VIC_CPI(__u8 cpi); | |
87 | static void send_CPI_allbutself(__u8 cpi); | |
88 | static void enable_vic_irq(unsigned int irq); | |
89 | static void disable_vic_irq(unsigned int irq); | |
90 | static unsigned int startup_vic_irq(unsigned int irq); | |
91 | static void enable_local_vic_irq(unsigned int irq); | |
92 | static void disable_local_vic_irq(unsigned int irq); | |
93 | static void before_handle_vic_irq(unsigned int irq); | |
94 | static void after_handle_vic_irq(unsigned int irq); | |
95 | static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask); | |
96 | static void ack_vic_irq(unsigned int irq); | |
97 | static void vic_enable_cpi(void); | |
98 | static void do_boot_cpu(__u8 cpuid); | |
99 | static void do_quad_bootstrap(void); | |
1da177e4 LT |
100 | |
101 | int hard_smp_processor_id(void); | |
102 | ||
103 | /* Inline functions */ | |
104 | static inline void | |
105 | send_one_QIC_CPI(__u8 cpu, __u8 cpi) | |
106 | { | |
107 | voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi = | |
108 | (smp_processor_id() << 16) + cpi; | |
109 | } | |
110 | ||
111 | static inline void | |
112 | send_QIC_CPI(__u32 cpuset, __u8 cpi) | |
113 | { | |
114 | int cpu; | |
115 | ||
116 | for_each_online_cpu(cpu) { | |
117 | if(cpuset & (1<<cpu)) { | |
118 | #ifdef VOYAGER_DEBUG | |
119 | if(!cpu_isset(cpu, cpu_online_map)) | |
120 | VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi, cpu)); | |
121 | #endif | |
122 | send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET); | |
123 | } | |
124 | } | |
125 | } | |
126 | ||
6431e6a2 DH |
127 | static inline void |
128 | wrapper_smp_local_timer_interrupt(struct pt_regs *regs) | |
129 | { | |
130 | irq_enter(); | |
131 | smp_local_timer_interrupt(regs); | |
132 | irq_exit(); | |
133 | } | |
134 | ||
1da177e4 LT |
135 | static inline void |
136 | send_one_CPI(__u8 cpu, __u8 cpi) | |
137 | { | |
138 | if(voyager_quad_processors & (1<<cpu)) | |
139 | send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET); | |
140 | else | |
141 | send_CPI(1<<cpu, cpi); | |
142 | } | |
143 | ||
144 | static inline void | |
145 | send_CPI_allbutself(__u8 cpi) | |
146 | { | |
147 | __u8 cpu = smp_processor_id(); | |
148 | __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu); | |
149 | send_CPI(mask, cpi); | |
150 | } | |
151 | ||
152 | static inline int | |
153 | is_cpu_quad(void) | |
154 | { | |
155 | __u8 cpumask = inb(VIC_PROC_WHO_AM_I); | |
156 | return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER); | |
157 | } | |
158 | ||
159 | static inline int | |
160 | is_cpu_extended(void) | |
161 | { | |
162 | __u8 cpu = hard_smp_processor_id(); | |
163 | ||
164 | return(voyager_extended_vic_processors & (1<<cpu)); | |
165 | } | |
166 | ||
167 | static inline int | |
168 | is_cpu_vic_boot(void) | |
169 | { | |
170 | __u8 cpu = hard_smp_processor_id(); | |
171 | ||
172 | return(voyager_extended_vic_processors | |
173 | & voyager_allowed_boot_processors & (1<<cpu)); | |
174 | } | |
175 | ||
176 | ||
177 | static inline void | |
178 | ack_CPI(__u8 cpi) | |
179 | { | |
180 | switch(cpi) { | |
181 | case VIC_CPU_BOOT_CPI: | |
182 | if(is_cpu_quad() && !is_cpu_vic_boot()) | |
183 | ack_QIC_CPI(cpi); | |
184 | else | |
185 | ack_VIC_CPI(cpi); | |
186 | break; | |
187 | case VIC_SYS_INT: | |
188 | case VIC_CMN_INT: | |
189 | /* These are slightly strange. Even on the Quad card, | |
190 | * They are vectored as VIC CPIs */ | |
191 | if(is_cpu_quad()) | |
192 | ack_special_QIC_CPI(cpi); | |
193 | else | |
194 | ack_VIC_CPI(cpi); | |
195 | break; | |
196 | default: | |
197 | printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi); | |
198 | break; | |
199 | } | |
200 | } | |
201 | ||
202 | /* local variables */ | |
203 | ||
204 | /* The VIC IRQ descriptors -- these look almost identical to the | |
205 | * 8259 IRQs except that masks and things must be kept per processor | |
206 | */ | |
207 | static struct hw_interrupt_type vic_irq_type = { | |
208 | .typename = "VIC-level", | |
209 | .startup = startup_vic_irq, | |
210 | .shutdown = disable_vic_irq, | |
211 | .enable = enable_vic_irq, | |
212 | .disable = disable_vic_irq, | |
213 | .ack = before_handle_vic_irq, | |
214 | .end = after_handle_vic_irq, | |
215 | .set_affinity = set_vic_irq_affinity, | |
216 | }; | |
217 | ||
218 | /* used to count up as CPUs are brought on line (starts at 0) */ | |
219 | static int cpucount = 0; | |
220 | ||
221 | /* steal a page from the bottom of memory for the trampoline and | |
222 | * squirrel its address away here. This will be in kernel virtual | |
223 | * space */ | |
224 | static __u32 trampoline_base; | |
225 | ||
226 | /* The per cpu profile stuff - used in smp_local_timer_interrupt */ | |
227 | static DEFINE_PER_CPU(int, prof_multiplier) = 1; | |
228 | static DEFINE_PER_CPU(int, prof_old_multiplier) = 1; | |
229 | static DEFINE_PER_CPU(int, prof_counter) = 1; | |
230 | ||
231 | /* the map used to check if a CPU has booted */ | |
232 | static __u32 cpu_booted_map; | |
233 | ||
234 | /* the synchronize flag used to hold all secondary CPUs spinning in | |
235 | * a tight loop until the boot sequence is ready for them */ | |
236 | static cpumask_t smp_commenced_mask = CPU_MASK_NONE; | |
237 | ||
238 | /* This is for the new dynamic CPU boot code */ | |
239 | cpumask_t cpu_callin_map = CPU_MASK_NONE; | |
240 | cpumask_t cpu_callout_map = CPU_MASK_NONE; | |
241 | ||
242 | /* The per processor IRQ masks (these are usually kept in sync) */ | |
243 | static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned; | |
244 | ||
245 | /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */ | |
246 | static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 }; | |
247 | ||
248 | /* Lock for enable/disable of VIC interrupts */ | |
249 | static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock); | |
250 | ||
251 | /* The boot processor is correctly set up in PC mode when it | |
252 | * comes up, but the secondaries need their master/slave 8259 | |
253 | * pairs initializing correctly */ | |
254 | ||
255 | /* Interrupt counters (per cpu) and total - used to try to | |
256 | * even up the interrupt handling routines */ | |
257 | static long vic_intr_total = 0; | |
258 | static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 }; | |
259 | static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 }; | |
260 | ||
261 | /* Since we can only use CPI0, we fake all the other CPIs */ | |
262 | static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned; | |
263 | ||
264 | /* debugging routine to read the isr of the cpu's pic */ | |
265 | static inline __u16 | |
266 | vic_read_isr(void) | |
267 | { | |
268 | __u16 isr; | |
269 | ||
270 | outb(0x0b, 0xa0); | |
271 | isr = inb(0xa0) << 8; | |
272 | outb(0x0b, 0x20); | |
273 | isr |= inb(0x20); | |
274 | ||
275 | return isr; | |
276 | } | |
277 | ||
278 | static __init void | |
279 | qic_setup(void) | |
280 | { | |
281 | if(!is_cpu_quad()) { | |
282 | /* not a quad, no setup */ | |
283 | return; | |
284 | } | |
285 | outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0); | |
286 | outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1); | |
287 | ||
288 | if(is_cpu_extended()) { | |
289 | /* the QIC duplicate of the VIC base register */ | |
290 | outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER); | |
291 | outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER); | |
292 | ||
293 | /* FIXME: should set up the QIC timer and memory parity | |
294 | * error vectors here */ | |
295 | } | |
296 | } | |
297 | ||
298 | static __init void | |
299 | vic_setup_pic(void) | |
300 | { | |
301 | outb(1, VIC_REDIRECT_REGISTER_1); | |
302 | /* clear the claim registers for dynamic routing */ | |
303 | outb(0, VIC_CLAIM_REGISTER_0); | |
304 | outb(0, VIC_CLAIM_REGISTER_1); | |
305 | ||
306 | outb(0, VIC_PRIORITY_REGISTER); | |
307 | /* Set the Primary and Secondary Microchannel vector | |
308 | * bases to be the same as the ordinary interrupts | |
309 | * | |
310 | * FIXME: This would be more efficient using separate | |
311 | * vectors. */ | |
312 | outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE); | |
313 | outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE); | |
314 | /* Now initiallise the master PIC belonging to this CPU by | |
315 | * sending the four ICWs */ | |
316 | ||
317 | /* ICW1: level triggered, ICW4 needed */ | |
318 | outb(0x19, 0x20); | |
319 | ||
320 | /* ICW2: vector base */ | |
321 | outb(FIRST_EXTERNAL_VECTOR, 0x21); | |
322 | ||
323 | /* ICW3: slave at line 2 */ | |
324 | outb(0x04, 0x21); | |
325 | ||
326 | /* ICW4: 8086 mode */ | |
327 | outb(0x01, 0x21); | |
328 | ||
329 | /* now the same for the slave PIC */ | |
330 | ||
331 | /* ICW1: level trigger, ICW4 needed */ | |
332 | outb(0x19, 0xA0); | |
333 | ||
334 | /* ICW2: slave vector base */ | |
335 | outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1); | |
336 | ||
337 | /* ICW3: slave ID */ | |
338 | outb(0x02, 0xA1); | |
339 | ||
340 | /* ICW4: 8086 mode */ | |
341 | outb(0x01, 0xA1); | |
342 | } | |
343 | ||
344 | static void | |
345 | do_quad_bootstrap(void) | |
346 | { | |
347 | if(is_cpu_quad() && is_cpu_vic_boot()) { | |
348 | int i; | |
349 | unsigned long flags; | |
350 | __u8 cpuid = hard_smp_processor_id(); | |
351 | ||
352 | local_irq_save(flags); | |
353 | ||
354 | for(i = 0; i<4; i++) { | |
355 | /* FIXME: this would be >>3 &0x7 on the 32 way */ | |
356 | if(((cpuid >> 2) & 0x03) == i) | |
357 | /* don't lower our own mask! */ | |
358 | continue; | |
359 | ||
360 | /* masquerade as local Quad CPU */ | |
361 | outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID); | |
362 | /* enable the startup CPI */ | |
363 | outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1); | |
364 | /* restore cpu id */ | |
365 | outb(0, QIC_PROCESSOR_ID); | |
366 | } | |
367 | local_irq_restore(flags); | |
368 | } | |
369 | } | |
370 | ||
371 | ||
372 | /* Set up all the basic stuff: read the SMP config and make all the | |
373 | * SMP information reflect only the boot cpu. All others will be | |
374 | * brought on-line later. */ | |
375 | void __init | |
376 | find_smp_config(void) | |
377 | { | |
378 | int i; | |
379 | ||
380 | boot_cpu_id = hard_smp_processor_id(); | |
381 | ||
382 | printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id); | |
383 | ||
384 | /* initialize the CPU structures (moved from smp_boot_cpus) */ | |
385 | for(i=0; i<NR_CPUS; i++) { | |
386 | cpu_irq_affinity[i] = ~0; | |
387 | } | |
388 | cpu_online_map = cpumask_of_cpu(boot_cpu_id); | |
389 | ||
390 | /* The boot CPU must be extended */ | |
391 | voyager_extended_vic_processors = 1<<boot_cpu_id; | |
392 | /* initially, all of the first 8 cpu's can boot */ | |
393 | voyager_allowed_boot_processors = 0xff; | |
394 | /* set up everything for just this CPU, we can alter | |
395 | * this as we start the other CPUs later */ | |
396 | /* now get the CPU disposition from the extended CMOS */ | |
397 | cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK); | |
398 | cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8; | |
399 | cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16; | |
400 | cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24; | |
401 | printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]); | |
402 | /* Here we set up the VIC to enable SMP */ | |
403 | /* enable the CPIs by writing the base vector to their register */ | |
404 | outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER); | |
405 | outb(1, VIC_REDIRECT_REGISTER_1); | |
406 | /* set the claim registers for static routing --- Boot CPU gets | |
407 | * all interrupts untill all other CPUs started */ | |
408 | outb(0xff, VIC_CLAIM_REGISTER_0); | |
409 | outb(0xff, VIC_CLAIM_REGISTER_1); | |
410 | /* Set the Primary and Secondary Microchannel vector | |
411 | * bases to be the same as the ordinary interrupts | |
412 | * | |
413 | * FIXME: This would be more efficient using separate | |
414 | * vectors. */ | |
415 | outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE); | |
416 | outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE); | |
417 | ||
418 | /* Finally tell the firmware that we're driving */ | |
419 | outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG, | |
420 | VOYAGER_SUS_IN_CONTROL_PORT); | |
421 | ||
422 | current_thread_info()->cpu = boot_cpu_id; | |
423 | } | |
424 | ||
425 | /* | |
426 | * The bootstrap kernel entry code has set these up. Save them | |
427 | * for a given CPU, id is physical */ | |
428 | void __init | |
429 | smp_store_cpu_info(int id) | |
430 | { | |
431 | struct cpuinfo_x86 *c=&cpu_data[id]; | |
432 | ||
433 | *c = boot_cpu_data; | |
434 | ||
435 | identify_cpu(c); | |
436 | } | |
437 | ||
438 | /* set up the trampoline and return the physical address of the code */ | |
439 | static __u32 __init | |
440 | setup_trampoline(void) | |
441 | { | |
442 | /* these two are global symbols in trampoline.S */ | |
443 | extern __u8 trampoline_end[]; | |
444 | extern __u8 trampoline_data[]; | |
445 | ||
446 | memcpy((__u8 *)trampoline_base, trampoline_data, | |
447 | trampoline_end - trampoline_data); | |
448 | return virt_to_phys((__u8 *)trampoline_base); | |
449 | } | |
450 | ||
451 | /* Routine initially called when a non-boot CPU is brought online */ | |
452 | static void __init | |
453 | start_secondary(void *unused) | |
454 | { | |
455 | __u8 cpuid = hard_smp_processor_id(); | |
456 | /* external functions not defined in the headers */ | |
457 | extern void calibrate_delay(void); | |
458 | ||
459 | cpu_init(); | |
460 | ||
461 | /* OK, we're in the routine */ | |
462 | ack_CPI(VIC_CPU_BOOT_CPI); | |
463 | ||
464 | /* setup the 8259 master slave pair belonging to this CPU --- | |
465 | * we won't actually receive any until the boot CPU | |
466 | * relinquishes it's static routing mask */ | |
467 | vic_setup_pic(); | |
468 | ||
469 | qic_setup(); | |
470 | ||
471 | if(is_cpu_quad() && !is_cpu_vic_boot()) { | |
472 | /* clear the boot CPI */ | |
473 | __u8 dummy; | |
474 | ||
475 | dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi; | |
476 | printk("read dummy %d\n", dummy); | |
477 | } | |
478 | ||
479 | /* lower the mask to receive CPIs */ | |
480 | vic_enable_cpi(); | |
481 | ||
482 | VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid)); | |
483 | ||
484 | /* enable interrupts */ | |
485 | local_irq_enable(); | |
486 | ||
487 | /* get our bogomips */ | |
488 | calibrate_delay(); | |
489 | ||
490 | /* save our processor parameters */ | |
491 | smp_store_cpu_info(cpuid); | |
492 | ||
493 | /* if we're a quad, we may need to bootstrap other CPUs */ | |
494 | do_quad_bootstrap(); | |
495 | ||
496 | /* FIXME: this is rather a poor hack to prevent the CPU | |
497 | * activating softirqs while it's supposed to be waiting for | |
498 | * permission to proceed. Without this, the new per CPU stuff | |
499 | * in the softirqs will fail */ | |
500 | local_irq_disable(); | |
501 | cpu_set(cpuid, cpu_callin_map); | |
502 | ||
503 | /* signal that we're done */ | |
504 | cpu_booted_map = 1; | |
505 | ||
506 | while (!cpu_isset(cpuid, smp_commenced_mask)) | |
507 | rep_nop(); | |
508 | local_irq_enable(); | |
509 | ||
510 | local_flush_tlb(); | |
511 | ||
512 | cpu_set(cpuid, cpu_online_map); | |
513 | wmb(); | |
514 | cpu_idle(); | |
515 | } | |
516 | ||
517 | ||
518 | /* Routine to kick start the given CPU and wait for it to report ready | |
519 | * (or timeout in startup). When this routine returns, the requested | |
520 | * CPU is either fully running and configured or known to be dead. | |
521 | * | |
522 | * We call this routine sequentially 1 CPU at a time, so no need for | |
523 | * locking */ | |
524 | ||
525 | static void __init | |
526 | do_boot_cpu(__u8 cpu) | |
527 | { | |
528 | struct task_struct *idle; | |
529 | int timeout; | |
530 | unsigned long flags; | |
531 | int quad_boot = (1<<cpu) & voyager_quad_processors | |
532 | & ~( voyager_extended_vic_processors | |
533 | & voyager_allowed_boot_processors); | |
534 | ||
535 | /* For the 486, we can't use the 4Mb page table trick, so | |
536 | * must map a region of memory */ | |
537 | #ifdef CONFIG_M486 | |
538 | int i; | |
539 | unsigned long *page_table_copies = (unsigned long *) | |
540 | __get_free_page(GFP_KERNEL); | |
541 | #endif | |
542 | pgd_t orig_swapper_pg_dir0; | |
543 | ||
544 | /* This is an area in head.S which was used to set up the | |
545 | * initial kernel stack. We need to alter this to give the | |
546 | * booting CPU a new stack (taken from its idle process) */ | |
547 | extern struct { | |
548 | __u8 *esp; | |
549 | unsigned short ss; | |
550 | } stack_start; | |
551 | /* This is the format of the CPI IDT gate (in real mode) which | |
552 | * we're hijacking to boot the CPU */ | |
553 | union IDTFormat { | |
554 | struct seg { | |
555 | __u16 Offset; | |
556 | __u16 Segment; | |
557 | } idt; | |
558 | __u32 val; | |
559 | } hijack_source; | |
560 | ||
561 | __u32 *hijack_vector; | |
562 | __u32 start_phys_address = setup_trampoline(); | |
563 | ||
564 | /* There's a clever trick to this: The linux trampoline is | |
565 | * compiled to begin at absolute location zero, so make the | |
566 | * address zero but have the data segment selector compensate | |
567 | * for the actual address */ | |
568 | hijack_source.idt.Offset = start_phys_address & 0x000F; | |
569 | hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF; | |
570 | ||
571 | cpucount++; | |
572 | idle = fork_idle(cpu); | |
573 | if(IS_ERR(idle)) | |
574 | panic("failed fork for CPU%d", cpu); | |
575 | idle->thread.eip = (unsigned long) start_secondary; | |
576 | /* init_tasks (in sched.c) is indexed logically */ | |
577 | stack_start.esp = (void *) idle->thread.esp; | |
578 | ||
579 | irq_ctx_init(cpu); | |
580 | ||
581 | /* Note: Don't modify initial ss override */ | |
582 | VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu, | |
583 | (unsigned long)hijack_source.val, hijack_source.idt.Segment, | |
584 | hijack_source.idt.Offset, stack_start.esp)); | |
585 | /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently | |
586 | * (so that the booting CPU can find start_32 */ | |
587 | orig_swapper_pg_dir0 = swapper_pg_dir[0]; | |
588 | #ifdef CONFIG_M486 | |
589 | if(page_table_copies == NULL) | |
590 | panic("No free memory for 486 page tables\n"); | |
591 | for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++) | |
592 | page_table_copies[i] = (i * PAGE_SIZE) | |
593 | | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT; | |
594 | ||
595 | ((unsigned long *)swapper_pg_dir)[0] = | |
596 | ((virt_to_phys(page_table_copies)) & PAGE_MASK) | |
597 | | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT; | |
598 | #else | |
599 | ((unsigned long *)swapper_pg_dir)[0] = | |
600 | (virt_to_phys(pg0) & PAGE_MASK) | |
601 | | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT; | |
602 | #endif | |
603 | ||
604 | if(quad_boot) { | |
605 | printk("CPU %d: non extended Quad boot\n", cpu); | |
606 | hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)*4); | |
607 | *hijack_vector = hijack_source.val; | |
608 | } else { | |
609 | printk("CPU%d: extended VIC boot\n", cpu); | |
610 | hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4); | |
611 | *hijack_vector = hijack_source.val; | |
612 | /* VIC errata, may also receive interrupt at this address */ | |
613 | hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4); | |
614 | *hijack_vector = hijack_source.val; | |
615 | } | |
616 | /* All non-boot CPUs start with interrupts fully masked. Need | |
617 | * to lower the mask of the CPI we're about to send. We do | |
618 | * this in the VIC by masquerading as the processor we're | |
619 | * about to boot and lowering its interrupt mask */ | |
620 | local_irq_save(flags); | |
621 | if(quad_boot) { | |
622 | send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI); | |
623 | } else { | |
624 | outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID); | |
625 | /* here we're altering registers belonging to `cpu' */ | |
626 | ||
627 | outb(VIC_BOOT_INTERRUPT_MASK, 0x21); | |
628 | /* now go back to our original identity */ | |
629 | outb(boot_cpu_id, VIC_PROCESSOR_ID); | |
630 | ||
631 | /* and boot the CPU */ | |
632 | ||
633 | send_CPI((1<<cpu), VIC_CPU_BOOT_CPI); | |
634 | } | |
635 | cpu_booted_map = 0; | |
636 | local_irq_restore(flags); | |
637 | ||
638 | /* now wait for it to become ready (or timeout) */ | |
639 | for(timeout = 0; timeout < 50000; timeout++) { | |
640 | if(cpu_booted_map) | |
641 | break; | |
642 | udelay(100); | |
643 | } | |
644 | /* reset the page table */ | |
645 | swapper_pg_dir[0] = orig_swapper_pg_dir0; | |
646 | local_flush_tlb(); | |
647 | #ifdef CONFIG_M486 | |
648 | free_page((unsigned long)page_table_copies); | |
649 | #endif | |
650 | ||
651 | if (cpu_booted_map) { | |
652 | VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n", | |
653 | cpu, smp_processor_id())); | |
654 | ||
655 | printk("CPU%d: ", cpu); | |
656 | print_cpu_info(&cpu_data[cpu]); | |
657 | wmb(); | |
658 | cpu_set(cpu, cpu_callout_map); | |
659 | } | |
660 | else { | |
661 | printk("CPU%d FAILED TO BOOT: ", cpu); | |
662 | if (*((volatile unsigned char *)phys_to_virt(start_phys_address))==0xA5) | |
663 | printk("Stuck.\n"); | |
664 | else | |
665 | printk("Not responding.\n"); | |
666 | ||
667 | cpucount--; | |
668 | } | |
669 | } | |
670 | ||
671 | void __init | |
672 | smp_boot_cpus(void) | |
673 | { | |
674 | int i; | |
675 | ||
676 | /* CAT BUS initialisation must be done after the memory */ | |
677 | /* FIXME: The L4 has a catbus too, it just needs to be | |
678 | * accessed in a totally different way */ | |
679 | if(voyager_level == 5) { | |
680 | voyager_cat_init(); | |
681 | ||
682 | /* now that the cat has probed the Voyager System Bus, sanity | |
683 | * check the cpu map */ | |
684 | if( ((voyager_quad_processors | voyager_extended_vic_processors) | |
685 | & cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) { | |
686 | /* should panic */ | |
687 | printk("\n\n***WARNING*** Sanity check of CPU present map FAILED\n"); | |
688 | } | |
689 | } else if(voyager_level == 4) | |
690 | voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0]; | |
691 | ||
692 | /* this sets up the idle task to run on the current cpu */ | |
693 | voyager_extended_cpus = 1; | |
694 | /* Remove the global_irq_holder setting, it triggers a BUG() on | |
695 | * schedule at the moment */ | |
696 | //global_irq_holder = boot_cpu_id; | |
697 | ||
698 | /* FIXME: Need to do something about this but currently only works | |
699 | * on CPUs with a tsc which none of mine have. | |
700 | smp_tune_scheduling(); | |
701 | */ | |
702 | smp_store_cpu_info(boot_cpu_id); | |
703 | printk("CPU%d: ", boot_cpu_id); | |
704 | print_cpu_info(&cpu_data[boot_cpu_id]); | |
705 | ||
706 | if(is_cpu_quad()) { | |
707 | /* booting on a Quad CPU */ | |
708 | printk("VOYAGER SMP: Boot CPU is Quad\n"); | |
709 | qic_setup(); | |
710 | do_quad_bootstrap(); | |
711 | } | |
712 | ||
713 | /* enable our own CPIs */ | |
714 | vic_enable_cpi(); | |
715 | ||
716 | cpu_set(boot_cpu_id, cpu_online_map); | |
717 | cpu_set(boot_cpu_id, cpu_callout_map); | |
718 | ||
719 | /* loop over all the extended VIC CPUs and boot them. The | |
720 | * Quad CPUs must be bootstrapped by their extended VIC cpu */ | |
721 | for(i = 0; i < NR_CPUS; i++) { | |
722 | if(i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map)) | |
723 | continue; | |
724 | do_boot_cpu(i); | |
725 | /* This udelay seems to be needed for the Quad boots | |
726 | * don't remove unless you know what you're doing */ | |
727 | udelay(1000); | |
728 | } | |
729 | /* we could compute the total bogomips here, but why bother?, | |
730 | * Code added from smpboot.c */ | |
731 | { | |
732 | unsigned long bogosum = 0; | |
733 | for (i = 0; i < NR_CPUS; i++) | |
734 | if (cpu_isset(i, cpu_online_map)) | |
735 | bogosum += cpu_data[i].loops_per_jiffy; | |
736 | printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
737 | cpucount+1, | |
738 | bogosum/(500000/HZ), | |
739 | (bogosum/(5000/HZ))%100); | |
740 | } | |
741 | voyager_extended_cpus = hweight32(voyager_extended_vic_processors); | |
742 | printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus, num_booting_cpus() - voyager_extended_cpus); | |
743 | /* that's it, switch to symmetric mode */ | |
744 | outb(0, VIC_PRIORITY_REGISTER); | |
745 | outb(0, VIC_CLAIM_REGISTER_0); | |
746 | outb(0, VIC_CLAIM_REGISTER_1); | |
747 | ||
748 | VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus())); | |
749 | } | |
750 | ||
751 | /* Reload the secondary CPUs task structure (this function does not | |
752 | * return ) */ | |
753 | void __init | |
754 | initialize_secondary(void) | |
755 | { | |
756 | #if 0 | |
757 | // AC kernels only | |
758 | set_current(hard_get_current()); | |
759 | #endif | |
760 | ||
761 | /* | |
762 | * We don't actually need to load the full TSS, | |
763 | * basically just the stack pointer and the eip. | |
764 | */ | |
765 | ||
766 | asm volatile( | |
767 | "movl %0,%%esp\n\t" | |
768 | "jmp *%1" | |
769 | : | |
770 | :"r" (current->thread.esp),"r" (current->thread.eip)); | |
771 | } | |
772 | ||
773 | /* handle a Voyager SYS_INT -- If we don't, the base board will | |
774 | * panic the system. | |
775 | * | |
776 | * System interrupts occur because some problem was detected on the | |
777 | * various busses. To find out what you have to probe all the | |
778 | * hardware via the CAT bus. FIXME: At the moment we do nothing. */ | |
779 | fastcall void | |
780 | smp_vic_sys_interrupt(struct pt_regs *regs) | |
781 | { | |
782 | ack_CPI(VIC_SYS_INT); | |
783 | printk("Voyager SYSTEM INTERRUPT\n"); | |
784 | } | |
785 | ||
786 | /* Handle a voyager CMN_INT; These interrupts occur either because of | |
787 | * a system status change or because a single bit memory error | |
788 | * occurred. FIXME: At the moment, ignore all this. */ | |
789 | fastcall void | |
790 | smp_vic_cmn_interrupt(struct pt_regs *regs) | |
791 | { | |
792 | static __u8 in_cmn_int = 0; | |
793 | static DEFINE_SPINLOCK(cmn_int_lock); | |
794 | ||
795 | /* common ints are broadcast, so make sure we only do this once */ | |
796 | _raw_spin_lock(&cmn_int_lock); | |
797 | if(in_cmn_int) | |
798 | goto unlock_end; | |
799 | ||
800 | in_cmn_int++; | |
801 | _raw_spin_unlock(&cmn_int_lock); | |
802 | ||
803 | VDEBUG(("Voyager COMMON INTERRUPT\n")); | |
804 | ||
805 | if(voyager_level == 5) | |
806 | voyager_cat_do_common_interrupt(); | |
807 | ||
808 | _raw_spin_lock(&cmn_int_lock); | |
809 | in_cmn_int = 0; | |
810 | unlock_end: | |
811 | _raw_spin_unlock(&cmn_int_lock); | |
812 | ack_CPI(VIC_CMN_INT); | |
813 | } | |
814 | ||
815 | /* | |
816 | * Reschedule call back. Nothing to do, all the work is done | |
817 | * automatically when we return from the interrupt. */ | |
818 | static void | |
819 | smp_reschedule_interrupt(void) | |
820 | { | |
821 | /* do nothing */ | |
822 | } | |
823 | ||
824 | static struct mm_struct * flush_mm; | |
825 | static unsigned long flush_va; | |
826 | static DEFINE_SPINLOCK(tlbstate_lock); | |
827 | #define FLUSH_ALL 0xffffffff | |
828 | ||
829 | /* | |
830 | * We cannot call mmdrop() because we are in interrupt context, | |
831 | * instead update mm->cpu_vm_mask. | |
832 | * | |
833 | * We need to reload %cr3 since the page tables may be going | |
834 | * away from under us.. | |
835 | */ | |
836 | static inline void | |
837 | leave_mm (unsigned long cpu) | |
838 | { | |
839 | if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) | |
840 | BUG(); | |
841 | cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask); | |
842 | load_cr3(swapper_pg_dir); | |
843 | } | |
844 | ||
845 | ||
846 | /* | |
847 | * Invalidate call-back | |
848 | */ | |
849 | static void | |
850 | smp_invalidate_interrupt(void) | |
851 | { | |
852 | __u8 cpu = smp_processor_id(); | |
853 | ||
854 | if (!test_bit(cpu, &smp_invalidate_needed)) | |
855 | return; | |
856 | /* This will flood messages. Don't uncomment unless you see | |
857 | * Problems with cross cpu invalidation | |
858 | VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n", | |
859 | smp_processor_id())); | |
860 | */ | |
861 | ||
862 | if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) { | |
863 | if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) { | |
864 | if (flush_va == FLUSH_ALL) | |
865 | local_flush_tlb(); | |
866 | else | |
867 | __flush_tlb_one(flush_va); | |
868 | } else | |
869 | leave_mm(cpu); | |
870 | } | |
871 | smp_mb__before_clear_bit(); | |
872 | clear_bit(cpu, &smp_invalidate_needed); | |
873 | smp_mb__after_clear_bit(); | |
874 | } | |
875 | ||
876 | /* All the new flush operations for 2.4 */ | |
877 | ||
878 | ||
879 | /* This routine is called with a physical cpu mask */ | |
880 | static void | |
881 | flush_tlb_others (unsigned long cpumask, struct mm_struct *mm, | |
882 | unsigned long va) | |
883 | { | |
884 | int stuck = 50000; | |
885 | ||
886 | if (!cpumask) | |
887 | BUG(); | |
888 | if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask) | |
889 | BUG(); | |
890 | if (cpumask & (1 << smp_processor_id())) | |
891 | BUG(); | |
892 | if (!mm) | |
893 | BUG(); | |
894 | ||
895 | spin_lock(&tlbstate_lock); | |
896 | ||
897 | flush_mm = mm; | |
898 | flush_va = va; | |
899 | atomic_set_mask(cpumask, &smp_invalidate_needed); | |
900 | /* | |
901 | * We have to send the CPI only to | |
902 | * CPUs affected. | |
903 | */ | |
904 | send_CPI(cpumask, VIC_INVALIDATE_CPI); | |
905 | ||
906 | while (smp_invalidate_needed) { | |
907 | mb(); | |
908 | if(--stuck == 0) { | |
909 | printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id()); | |
910 | break; | |
911 | } | |
912 | } | |
913 | ||
914 | /* Uncomment only to debug invalidation problems | |
915 | VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu)); | |
916 | */ | |
917 | ||
918 | flush_mm = NULL; | |
919 | flush_va = 0; | |
920 | spin_unlock(&tlbstate_lock); | |
921 | } | |
922 | ||
923 | void | |
924 | flush_tlb_current_task(void) | |
925 | { | |
926 | struct mm_struct *mm = current->mm; | |
927 | unsigned long cpu_mask; | |
928 | ||
929 | preempt_disable(); | |
930 | ||
931 | cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id()); | |
932 | local_flush_tlb(); | |
933 | if (cpu_mask) | |
934 | flush_tlb_others(cpu_mask, mm, FLUSH_ALL); | |
935 | ||
936 | preempt_enable(); | |
937 | } | |
938 | ||
939 | ||
940 | void | |
941 | flush_tlb_mm (struct mm_struct * mm) | |
942 | { | |
943 | unsigned long cpu_mask; | |
944 | ||
945 | preempt_disable(); | |
946 | ||
947 | cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id()); | |
948 | ||
949 | if (current->active_mm == mm) { | |
950 | if (current->mm) | |
951 | local_flush_tlb(); | |
952 | else | |
953 | leave_mm(smp_processor_id()); | |
954 | } | |
955 | if (cpu_mask) | |
956 | flush_tlb_others(cpu_mask, mm, FLUSH_ALL); | |
957 | ||
958 | preempt_enable(); | |
959 | } | |
960 | ||
961 | void flush_tlb_page(struct vm_area_struct * vma, unsigned long va) | |
962 | { | |
963 | struct mm_struct *mm = vma->vm_mm; | |
964 | unsigned long cpu_mask; | |
965 | ||
966 | preempt_disable(); | |
967 | ||
968 | cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id()); | |
969 | if (current->active_mm == mm) { | |
970 | if(current->mm) | |
971 | __flush_tlb_one(va); | |
972 | else | |
973 | leave_mm(smp_processor_id()); | |
974 | } | |
975 | ||
976 | if (cpu_mask) | |
977 | flush_tlb_others(cpu_mask, mm, va); | |
978 | ||
979 | preempt_enable(); | |
980 | } | |
981 | ||
982 | /* enable the requested IRQs */ | |
983 | static void | |
984 | smp_enable_irq_interrupt(void) | |
985 | { | |
986 | __u8 irq; | |
987 | __u8 cpu = get_cpu(); | |
988 | ||
989 | VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu, | |
990 | vic_irq_enable_mask[cpu])); | |
991 | ||
992 | spin_lock(&vic_irq_lock); | |
993 | for(irq = 0; irq < 16; irq++) { | |
994 | if(vic_irq_enable_mask[cpu] & (1<<irq)) | |
995 | enable_local_vic_irq(irq); | |
996 | } | |
997 | vic_irq_enable_mask[cpu] = 0; | |
998 | spin_unlock(&vic_irq_lock); | |
999 | ||
1000 | put_cpu_no_resched(); | |
1001 | } | |
1002 | ||
1003 | /* | |
1004 | * CPU halt call-back | |
1005 | */ | |
1006 | static void | |
1007 | smp_stop_cpu_function(void *dummy) | |
1008 | { | |
1009 | VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id())); | |
1010 | cpu_clear(smp_processor_id(), cpu_online_map); | |
1011 | local_irq_disable(); | |
1012 | for(;;) | |
1013 | __asm__("hlt"); | |
1014 | } | |
1015 | ||
1016 | static DEFINE_SPINLOCK(call_lock); | |
1017 | ||
1018 | struct call_data_struct { | |
1019 | void (*func) (void *info); | |
1020 | void *info; | |
1021 | volatile unsigned long started; | |
1022 | volatile unsigned long finished; | |
1023 | int wait; | |
1024 | }; | |
1025 | ||
1026 | static struct call_data_struct * call_data; | |
1027 | ||
1028 | /* execute a thread on a new CPU. The function to be called must be | |
1029 | * previously set up. This is used to schedule a function for | |
1030 | * execution on all CPU's - set up the function then broadcast a | |
1031 | * function_interrupt CPI to come here on each CPU */ | |
1032 | static void | |
1033 | smp_call_function_interrupt(void) | |
1034 | { | |
1035 | void (*func) (void *info) = call_data->func; | |
1036 | void *info = call_data->info; | |
1037 | /* must take copy of wait because call_data may be replaced | |
1038 | * unless the function is waiting for us to finish */ | |
1039 | int wait = call_data->wait; | |
1040 | __u8 cpu = smp_processor_id(); | |
1041 | ||
1042 | /* | |
1043 | * Notify initiating CPU that I've grabbed the data and am | |
1044 | * about to execute the function | |
1045 | */ | |
1046 | mb(); | |
1047 | if(!test_and_clear_bit(cpu, &call_data->started)) { | |
1048 | /* If the bit wasn't set, this could be a replay */ | |
1049 | printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu); | |
1050 | return; | |
1051 | } | |
1052 | /* | |
1053 | * At this point the info structure may be out of scope unless wait==1 | |
1054 | */ | |
1055 | irq_enter(); | |
1056 | (*func)(info); | |
1057 | irq_exit(); | |
1058 | if (wait) { | |
1059 | mb(); | |
1060 | clear_bit(cpu, &call_data->finished); | |
1061 | } | |
1062 | } | |
1063 | ||
1064 | /* Call this function on all CPUs using the function_interrupt above | |
1065 | <func> The function to run. This must be fast and non-blocking. | |
1066 | <info> An arbitrary pointer to pass to the function. | |
1067 | <retry> If true, keep retrying until ready. | |
1068 | <wait> If true, wait until function has completed on other CPUs. | |
1069 | [RETURNS] 0 on success, else a negative status code. Does not return until | |
1070 | remote CPUs are nearly ready to execute <<func>> or are or have executed. | |
1071 | */ | |
1072 | int | |
1073 | smp_call_function (void (*func) (void *info), void *info, int retry, | |
1074 | int wait) | |
1075 | { | |
1076 | struct call_data_struct data; | |
1077 | __u32 mask = cpus_addr(cpu_online_map)[0]; | |
1078 | ||
1079 | mask &= ~(1<<smp_processor_id()); | |
1080 | ||
1081 | if (!mask) | |
1082 | return 0; | |
1083 | ||
1084 | /* Can deadlock when called with interrupts disabled */ | |
1085 | WARN_ON(irqs_disabled()); | |
1086 | ||
1087 | data.func = func; | |
1088 | data.info = info; | |
1089 | data.started = mask; | |
1090 | data.wait = wait; | |
1091 | if (wait) | |
1092 | data.finished = mask; | |
1093 | ||
1094 | spin_lock(&call_lock); | |
1095 | call_data = &data; | |
1096 | wmb(); | |
1097 | /* Send a message to all other CPUs and wait for them to respond */ | |
1098 | send_CPI_allbutself(VIC_CALL_FUNCTION_CPI); | |
1099 | ||
1100 | /* Wait for response */ | |
1101 | while (data.started) | |
1102 | barrier(); | |
1103 | ||
1104 | if (wait) | |
1105 | while (data.finished) | |
1106 | barrier(); | |
1107 | ||
1108 | spin_unlock(&call_lock); | |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | /* Sorry about the name. In an APIC based system, the APICs | |
1114 | * themselves are programmed to send a timer interrupt. This is used | |
1115 | * by linux to reschedule the processor. Voyager doesn't have this, | |
1116 | * so we use the system clock to interrupt one processor, which in | |
1117 | * turn, broadcasts a timer CPI to all the others --- we receive that | |
1118 | * CPI here. We don't use this actually for counting so losing | |
1119 | * ticks doesn't matter | |
1120 | * | |
1121 | * FIXME: For those CPU's which actually have a local APIC, we could | |
1122 | * try to use it to trigger this interrupt instead of having to | |
1123 | * broadcast the timer tick. Unfortunately, all my pentium DYADs have | |
1124 | * no local APIC, so I can't do this | |
1125 | * | |
1126 | * This function is currently a placeholder and is unused in the code */ | |
1127 | fastcall void | |
1128 | smp_apic_timer_interrupt(struct pt_regs *regs) | |
1129 | { | |
1130 | wrapper_smp_local_timer_interrupt(regs); | |
1131 | } | |
1132 | ||
1133 | /* All of the QUAD interrupt GATES */ | |
1134 | fastcall void | |
1135 | smp_qic_timer_interrupt(struct pt_regs *regs) | |
1136 | { | |
1137 | ack_QIC_CPI(QIC_TIMER_CPI); | |
1138 | wrapper_smp_local_timer_interrupt(regs); | |
1139 | } | |
1140 | ||
1141 | fastcall void | |
1142 | smp_qic_invalidate_interrupt(struct pt_regs *regs) | |
1143 | { | |
1144 | ack_QIC_CPI(QIC_INVALIDATE_CPI); | |
1145 | smp_invalidate_interrupt(); | |
1146 | } | |
1147 | ||
1148 | fastcall void | |
1149 | smp_qic_reschedule_interrupt(struct pt_regs *regs) | |
1150 | { | |
1151 | ack_QIC_CPI(QIC_RESCHEDULE_CPI); | |
1152 | smp_reschedule_interrupt(); | |
1153 | } | |
1154 | ||
1155 | fastcall void | |
1156 | smp_qic_enable_irq_interrupt(struct pt_regs *regs) | |
1157 | { | |
1158 | ack_QIC_CPI(QIC_ENABLE_IRQ_CPI); | |
1159 | smp_enable_irq_interrupt(); | |
1160 | } | |
1161 | ||
1162 | fastcall void | |
1163 | smp_qic_call_function_interrupt(struct pt_regs *regs) | |
1164 | { | |
1165 | ack_QIC_CPI(QIC_CALL_FUNCTION_CPI); | |
1166 | smp_call_function_interrupt(); | |
1167 | } | |
1168 | ||
1169 | fastcall void | |
1170 | smp_vic_cpi_interrupt(struct pt_regs *regs) | |
1171 | { | |
1172 | __u8 cpu = smp_processor_id(); | |
1173 | ||
1174 | if(is_cpu_quad()) | |
1175 | ack_QIC_CPI(VIC_CPI_LEVEL0); | |
1176 | else | |
1177 | ack_VIC_CPI(VIC_CPI_LEVEL0); | |
1178 | ||
1179 | if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu])) | |
1180 | wrapper_smp_local_timer_interrupt(regs); | |
1181 | if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu])) | |
1182 | smp_invalidate_interrupt(); | |
1183 | if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu])) | |
1184 | smp_reschedule_interrupt(); | |
1185 | if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu])) | |
1186 | smp_enable_irq_interrupt(); | |
1187 | if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu])) | |
1188 | smp_call_function_interrupt(); | |
1189 | } | |
1190 | ||
1191 | static void | |
1192 | do_flush_tlb_all(void* info) | |
1193 | { | |
1194 | unsigned long cpu = smp_processor_id(); | |
1195 | ||
1196 | __flush_tlb_all(); | |
1197 | if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY) | |
1198 | leave_mm(cpu); | |
1199 | } | |
1200 | ||
1201 | ||
1202 | /* flush the TLB of every active CPU in the system */ | |
1203 | void | |
1204 | flush_tlb_all(void) | |
1205 | { | |
1206 | on_each_cpu(do_flush_tlb_all, 0, 1, 1); | |
1207 | } | |
1208 | ||
1209 | /* used to set up the trampoline for other CPUs when the memory manager | |
1210 | * is sorted out */ | |
1211 | void __init | |
1212 | smp_alloc_memory(void) | |
1213 | { | |
1214 | trampoline_base = (__u32)alloc_bootmem_low_pages(PAGE_SIZE); | |
1215 | if(__pa(trampoline_base) >= 0x93000) | |
1216 | BUG(); | |
1217 | } | |
1218 | ||
1219 | /* send a reschedule CPI to one CPU by physical CPU number*/ | |
1220 | void | |
1221 | smp_send_reschedule(int cpu) | |
1222 | { | |
1223 | send_one_CPI(cpu, VIC_RESCHEDULE_CPI); | |
1224 | } | |
1225 | ||
1226 | ||
1227 | int | |
1228 | hard_smp_processor_id(void) | |
1229 | { | |
1230 | __u8 i; | |
1231 | __u8 cpumask = inb(VIC_PROC_WHO_AM_I); | |
1232 | if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER) | |
1233 | return cpumask & 0x1F; | |
1234 | ||
1235 | for(i = 0; i < 8; i++) { | |
1236 | if(cpumask & (1<<i)) | |
1237 | return i; | |
1238 | } | |
1239 | printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask); | |
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | /* broadcast a halt to all other CPUs */ | |
1244 | void | |
1245 | smp_send_stop(void) | |
1246 | { | |
1247 | smp_call_function(smp_stop_cpu_function, NULL, 1, 1); | |
1248 | } | |
1249 | ||
1250 | /* this function is triggered in time.c when a clock tick fires | |
1251 | * we need to re-broadcast the tick to all CPUs */ | |
1252 | void | |
1253 | smp_vic_timer_interrupt(struct pt_regs *regs) | |
1254 | { | |
1255 | send_CPI_allbutself(VIC_TIMER_CPI); | |
1256 | smp_local_timer_interrupt(regs); | |
1257 | } | |
1258 | ||
1da177e4 LT |
1259 | /* local (per CPU) timer interrupt. It does both profiling and |
1260 | * process statistics/rescheduling. | |
1261 | * | |
1262 | * We do profiling in every local tick, statistics/rescheduling | |
1263 | * happen only every 'profiling multiplier' ticks. The default | |
1264 | * multiplier is 1 and it can be changed by writing the new multiplier | |
1265 | * value into /proc/profile. | |
1266 | */ | |
1267 | void | |
1268 | smp_local_timer_interrupt(struct pt_regs * regs) | |
1269 | { | |
1270 | int cpu = smp_processor_id(); | |
1271 | long weight; | |
1272 | ||
1273 | profile_tick(CPU_PROFILING, regs); | |
1274 | if (--per_cpu(prof_counter, cpu) <= 0) { | |
1275 | /* | |
1276 | * The multiplier may have changed since the last time we got | |
1277 | * to this point as a result of the user writing to | |
1278 | * /proc/profile. In this case we need to adjust the APIC | |
1279 | * timer accordingly. | |
1280 | * | |
1281 | * Interrupts are already masked off at this point. | |
1282 | */ | |
1283 | per_cpu(prof_counter,cpu) = per_cpu(prof_multiplier, cpu); | |
1284 | if (per_cpu(prof_counter, cpu) != | |
1285 | per_cpu(prof_old_multiplier, cpu)) { | |
1286 | /* FIXME: need to update the vic timer tick here */ | |
1287 | per_cpu(prof_old_multiplier, cpu) = | |
1288 | per_cpu(prof_counter, cpu); | |
1289 | } | |
1290 | ||
fa1e1bdf | 1291 | update_process_times(user_mode_vm(regs)); |
1da177e4 LT |
1292 | } |
1293 | ||
1294 | if( ((1<<cpu) & voyager_extended_vic_processors) == 0) | |
1295 | /* only extended VIC processors participate in | |
1296 | * interrupt distribution */ | |
1297 | return; | |
1298 | ||
1299 | /* | |
1300 | * We take the 'long' return path, and there every subsystem | |
1301 | * grabs the apropriate locks (kernel lock/ irq lock). | |
1302 | * | |
1303 | * we might want to decouple profiling from the 'long path', | |
1304 | * and do the profiling totally in assembly. | |
1305 | * | |
1306 | * Currently this isn't too much of an issue (performance wise), | |
1307 | * we can take more than 100K local irqs per second on a 100 MHz P5. | |
1308 | */ | |
1309 | ||
1310 | if((++vic_tick[cpu] & 0x7) != 0) | |
1311 | return; | |
1312 | /* get here every 16 ticks (about every 1/6 of a second) */ | |
1313 | ||
1314 | /* Change our priority to give someone else a chance at getting | |
1315 | * the IRQ. The algorithm goes like this: | |
1316 | * | |
1317 | * In the VIC, the dynamically routed interrupt is always | |
1318 | * handled by the lowest priority eligible (i.e. receiving | |
1319 | * interrupts) CPU. If >1 eligible CPUs are equal lowest, the | |
1320 | * lowest processor number gets it. | |
1321 | * | |
1322 | * The priority of a CPU is controlled by a special per-CPU | |
1323 | * VIC priority register which is 3 bits wide 0 being lowest | |
1324 | * and 7 highest priority.. | |
1325 | * | |
1326 | * Therefore we subtract the average number of interrupts from | |
1327 | * the number we've fielded. If this number is negative, we | |
1328 | * lower the activity count and if it is positive, we raise | |
1329 | * it. | |
1330 | * | |
1331 | * I'm afraid this still leads to odd looking interrupt counts: | |
1332 | * the totals are all roughly equal, but the individual ones | |
1333 | * look rather skewed. | |
1334 | * | |
1335 | * FIXME: This algorithm is total crap when mixed with SMP | |
1336 | * affinity code since we now try to even up the interrupt | |
1337 | * counts when an affinity binding is keeping them on a | |
1338 | * particular CPU*/ | |
1339 | weight = (vic_intr_count[cpu]*voyager_extended_cpus | |
1340 | - vic_intr_total) >> 4; | |
1341 | weight += 4; | |
1342 | if(weight > 7) | |
1343 | weight = 7; | |
1344 | if(weight < 0) | |
1345 | weight = 0; | |
1346 | ||
1347 | outb((__u8)weight, VIC_PRIORITY_REGISTER); | |
1348 | ||
1349 | #ifdef VOYAGER_DEBUG | |
1350 | if((vic_tick[cpu] & 0xFFF) == 0) { | |
1351 | /* print this message roughly every 25 secs */ | |
1352 | printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n", | |
1353 | cpu, vic_tick[cpu], weight); | |
1354 | } | |
1355 | #endif | |
1356 | } | |
1357 | ||
1358 | /* setup the profiling timer */ | |
1359 | int | |
1360 | setup_profiling_timer(unsigned int multiplier) | |
1361 | { | |
1362 | int i; | |
1363 | ||
1364 | if ( (!multiplier)) | |
1365 | return -EINVAL; | |
1366 | ||
1367 | /* | |
1368 | * Set the new multiplier for each CPU. CPUs don't start using the | |
1369 | * new values until the next timer interrupt in which they do process | |
1370 | * accounting. | |
1371 | */ | |
1372 | for (i = 0; i < NR_CPUS; ++i) | |
1373 | per_cpu(prof_multiplier, i) = multiplier; | |
1374 | ||
1375 | return 0; | |
1376 | } | |
1377 | ||
1378 | ||
1379 | /* The CPIs are handled in the per cpu 8259s, so they must be | |
1380 | * enabled to be received: FIX: enabling the CPIs in the early | |
1381 | * boot sequence interferes with bug checking; enable them later | |
1382 | * on in smp_init */ | |
1383 | #define VIC_SET_GATE(cpi, vector) \ | |
1384 | set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector)) | |
1385 | #define QIC_SET_GATE(cpi, vector) \ | |
1386 | set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector)) | |
1387 | ||
1388 | void __init | |
1389 | smp_intr_init(void) | |
1390 | { | |
1391 | int i; | |
1392 | ||
1393 | /* initialize the per cpu irq mask to all disabled */ | |
1394 | for(i = 0; i < NR_CPUS; i++) | |
1395 | vic_irq_mask[i] = 0xFFFF; | |
1396 | ||
1397 | VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt); | |
1398 | ||
1399 | VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt); | |
1400 | VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt); | |
1401 | ||
1402 | QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt); | |
1403 | QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt); | |
1404 | QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt); | |
1405 | QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt); | |
1406 | QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt); | |
1407 | ||
1408 | ||
1409 | /* now put the VIC descriptor into the first 48 IRQs | |
1410 | * | |
1411 | * This is for later: first 16 correspond to PC IRQs; next 16 | |
1412 | * are Primary MC IRQs and final 16 are Secondary MC IRQs */ | |
1413 | for(i = 0; i < 48; i++) | |
1414 | irq_desc[i].handler = &vic_irq_type; | |
1415 | } | |
1416 | ||
1417 | /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per | |
1418 | * processor to receive CPI */ | |
1419 | static void | |
1420 | send_CPI(__u32 cpuset, __u8 cpi) | |
1421 | { | |
1422 | int cpu; | |
1423 | __u32 quad_cpuset = (cpuset & voyager_quad_processors); | |
1424 | ||
1425 | if(cpi < VIC_START_FAKE_CPI) { | |
1426 | /* fake CPI are only used for booting, so send to the | |
1427 | * extended quads as well---Quads must be VIC booted */ | |
1428 | outb((__u8)(cpuset), VIC_CPI_Registers[cpi]); | |
1429 | return; | |
1430 | } | |
1431 | if(quad_cpuset) | |
1432 | send_QIC_CPI(quad_cpuset, cpi); | |
1433 | cpuset &= ~quad_cpuset; | |
1434 | cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */ | |
1435 | if(cpuset == 0) | |
1436 | return; | |
1437 | for_each_online_cpu(cpu) { | |
1438 | if(cpuset & (1<<cpu)) | |
1439 | set_bit(cpi, &vic_cpi_mailbox[cpu]); | |
1440 | } | |
1441 | if(cpuset) | |
1442 | outb((__u8)cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]); | |
1443 | } | |
1444 | ||
1445 | /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and | |
1446 | * set the cache line to shared by reading it. | |
1447 | * | |
1448 | * DON'T make this inline otherwise the cache line read will be | |
1449 | * optimised away | |
1450 | * */ | |
1451 | static int | |
1452 | ack_QIC_CPI(__u8 cpi) { | |
1453 | __u8 cpu = hard_smp_processor_id(); | |
1454 | ||
1455 | cpi &= 7; | |
1456 | ||
1457 | outb(1<<cpi, QIC_INTERRUPT_CLEAR1); | |
1458 | return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi; | |
1459 | } | |
1460 | ||
1461 | static void | |
1462 | ack_special_QIC_CPI(__u8 cpi) | |
1463 | { | |
1464 | switch(cpi) { | |
1465 | case VIC_CMN_INT: | |
1466 | outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0); | |
1467 | break; | |
1468 | case VIC_SYS_INT: | |
1469 | outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0); | |
1470 | break; | |
1471 | } | |
1472 | /* also clear at the VIC, just in case (nop for non-extended proc) */ | |
1473 | ack_VIC_CPI(cpi); | |
1474 | } | |
1475 | ||
1476 | /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */ | |
1477 | static void | |
1478 | ack_VIC_CPI(__u8 cpi) | |
1479 | { | |
1480 | #ifdef VOYAGER_DEBUG | |
1481 | unsigned long flags; | |
1482 | __u16 isr; | |
1483 | __u8 cpu = smp_processor_id(); | |
1484 | ||
1485 | local_irq_save(flags); | |
1486 | isr = vic_read_isr(); | |
1487 | if((isr & (1<<(cpi &7))) == 0) { | |
1488 | printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi); | |
1489 | } | |
1490 | #endif | |
1491 | /* send specific EOI; the two system interrupts have | |
1492 | * bit 4 set for a separate vector but behave as the | |
1493 | * corresponding 3 bit intr */ | |
1494 | outb_p(0x60|(cpi & 7),0x20); | |
1495 | ||
1496 | #ifdef VOYAGER_DEBUG | |
1497 | if((vic_read_isr() & (1<<(cpi &7))) != 0) { | |
1498 | printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi); | |
1499 | } | |
1500 | local_irq_restore(flags); | |
1501 | #endif | |
1502 | } | |
1503 | ||
1504 | /* cribbed with thanks from irq.c */ | |
1505 | #define __byte(x,y) (((unsigned char *)&(y))[x]) | |
1506 | #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu])) | |
1507 | #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu])) | |
1508 | ||
1509 | static unsigned int | |
1510 | startup_vic_irq(unsigned int irq) | |
1511 | { | |
1512 | enable_vic_irq(irq); | |
1513 | ||
1514 | return 0; | |
1515 | } | |
1516 | ||
1517 | /* The enable and disable routines. This is where we run into | |
1518 | * conflicting architectural philosophy. Fundamentally, the voyager | |
1519 | * architecture does not expect to have to disable interrupts globally | |
1520 | * (the IRQ controllers belong to each CPU). The processor masquerade | |
1521 | * which is used to start the system shouldn't be used in a running OS | |
1522 | * since it will cause great confusion if two separate CPUs drive to | |
1523 | * the same IRQ controller (I know, I've tried it). | |
1524 | * | |
1525 | * The solution is a variant on the NCR lazy SPL design: | |
1526 | * | |
1527 | * 1) To disable an interrupt, do nothing (other than set the | |
1528 | * IRQ_DISABLED flag). This dares the interrupt actually to arrive. | |
1529 | * | |
1530 | * 2) If the interrupt dares to come in, raise the local mask against | |
1531 | * it (this will result in all the CPU masks being raised | |
1532 | * eventually). | |
1533 | * | |
1534 | * 3) To enable the interrupt, lower the mask on the local CPU and | |
1535 | * broadcast an Interrupt enable CPI which causes all other CPUs to | |
1536 | * adjust their masks accordingly. */ | |
1537 | ||
1538 | static void | |
1539 | enable_vic_irq(unsigned int irq) | |
1540 | { | |
1541 | /* linux doesn't to processor-irq affinity, so enable on | |
1542 | * all CPUs we know about */ | |
1543 | int cpu = smp_processor_id(), real_cpu; | |
1544 | __u16 mask = (1<<irq); | |
1545 | __u32 processorList = 0; | |
1546 | unsigned long flags; | |
1547 | ||
1548 | VDEBUG(("VOYAGER: enable_vic_irq(%d) CPU%d affinity 0x%lx\n", | |
1549 | irq, cpu, cpu_irq_affinity[cpu])); | |
1550 | spin_lock_irqsave(&vic_irq_lock, flags); | |
1551 | for_each_online_cpu(real_cpu) { | |
1552 | if(!(voyager_extended_vic_processors & (1<<real_cpu))) | |
1553 | continue; | |
1554 | if(!(cpu_irq_affinity[real_cpu] & mask)) { | |
1555 | /* irq has no affinity for this CPU, ignore */ | |
1556 | continue; | |
1557 | } | |
1558 | if(real_cpu == cpu) { | |
1559 | enable_local_vic_irq(irq); | |
1560 | } | |
1561 | else if(vic_irq_mask[real_cpu] & mask) { | |
1562 | vic_irq_enable_mask[real_cpu] |= mask; | |
1563 | processorList |= (1<<real_cpu); | |
1564 | } | |
1565 | } | |
1566 | spin_unlock_irqrestore(&vic_irq_lock, flags); | |
1567 | if(processorList) | |
1568 | send_CPI(processorList, VIC_ENABLE_IRQ_CPI); | |
1569 | } | |
1570 | ||
1571 | static void | |
1572 | disable_vic_irq(unsigned int irq) | |
1573 | { | |
1574 | /* lazy disable, do nothing */ | |
1575 | } | |
1576 | ||
1577 | static void | |
1578 | enable_local_vic_irq(unsigned int irq) | |
1579 | { | |
1580 | __u8 cpu = smp_processor_id(); | |
1581 | __u16 mask = ~(1 << irq); | |
1582 | __u16 old_mask = vic_irq_mask[cpu]; | |
1583 | ||
1584 | vic_irq_mask[cpu] &= mask; | |
1585 | if(vic_irq_mask[cpu] == old_mask) | |
1586 | return; | |
1587 | ||
1588 | VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n", | |
1589 | irq, cpu)); | |
1590 | ||
1591 | if (irq & 8) { | |
1592 | outb_p(cached_A1(cpu),0xA1); | |
1593 | (void)inb_p(0xA1); | |
1594 | } | |
1595 | else { | |
1596 | outb_p(cached_21(cpu),0x21); | |
1597 | (void)inb_p(0x21); | |
1598 | } | |
1599 | } | |
1600 | ||
1601 | static void | |
1602 | disable_local_vic_irq(unsigned int irq) | |
1603 | { | |
1604 | __u8 cpu = smp_processor_id(); | |
1605 | __u16 mask = (1 << irq); | |
1606 | __u16 old_mask = vic_irq_mask[cpu]; | |
1607 | ||
1608 | if(irq == 7) | |
1609 | return; | |
1610 | ||
1611 | vic_irq_mask[cpu] |= mask; | |
1612 | if(old_mask == vic_irq_mask[cpu]) | |
1613 | return; | |
1614 | ||
1615 | VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n", | |
1616 | irq, cpu)); | |
1617 | ||
1618 | if (irq & 8) { | |
1619 | outb_p(cached_A1(cpu),0xA1); | |
1620 | (void)inb_p(0xA1); | |
1621 | } | |
1622 | else { | |
1623 | outb_p(cached_21(cpu),0x21); | |
1624 | (void)inb_p(0x21); | |
1625 | } | |
1626 | } | |
1627 | ||
1628 | /* The VIC is level triggered, so the ack can only be issued after the | |
1629 | * interrupt completes. However, we do Voyager lazy interrupt | |
1630 | * handling here: It is an extremely expensive operation to mask an | |
1631 | * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If | |
1632 | * this interrupt actually comes in, then we mask and ack here to push | |
1633 | * the interrupt off to another CPU */ | |
1634 | static void | |
1635 | before_handle_vic_irq(unsigned int irq) | |
1636 | { | |
1637 | irq_desc_t *desc = irq_desc + irq; | |
1638 | __u8 cpu = smp_processor_id(); | |
1639 | ||
1640 | _raw_spin_lock(&vic_irq_lock); | |
1641 | vic_intr_total++; | |
1642 | vic_intr_count[cpu]++; | |
1643 | ||
1644 | if(!(cpu_irq_affinity[cpu] & (1<<irq))) { | |
1645 | /* The irq is not in our affinity mask, push it off | |
1646 | * onto another CPU */ | |
1647 | VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n", | |
1648 | irq, cpu)); | |
1649 | disable_local_vic_irq(irq); | |
1650 | /* set IRQ_INPROGRESS to prevent the handler in irq.c from | |
1651 | * actually calling the interrupt routine */ | |
1652 | desc->status |= IRQ_REPLAY | IRQ_INPROGRESS; | |
1653 | } else if(desc->status & IRQ_DISABLED) { | |
1654 | /* Damn, the interrupt actually arrived, do the lazy | |
1655 | * disable thing. The interrupt routine in irq.c will | |
1656 | * not handle a IRQ_DISABLED interrupt, so nothing more | |
1657 | * need be done here */ | |
1658 | VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n", | |
1659 | irq, cpu)); | |
1660 | disable_local_vic_irq(irq); | |
1661 | desc->status |= IRQ_REPLAY; | |
1662 | } else { | |
1663 | desc->status &= ~IRQ_REPLAY; | |
1664 | } | |
1665 | ||
1666 | _raw_spin_unlock(&vic_irq_lock); | |
1667 | } | |
1668 | ||
1669 | /* Finish the VIC interrupt: basically mask */ | |
1670 | static void | |
1671 | after_handle_vic_irq(unsigned int irq) | |
1672 | { | |
1673 | irq_desc_t *desc = irq_desc + irq; | |
1674 | ||
1675 | _raw_spin_lock(&vic_irq_lock); | |
1676 | { | |
1677 | unsigned int status = desc->status & ~IRQ_INPROGRESS; | |
1678 | #ifdef VOYAGER_DEBUG | |
1679 | __u16 isr; | |
1680 | #endif | |
1681 | ||
1682 | desc->status = status; | |
1683 | if ((status & IRQ_DISABLED)) | |
1684 | disable_local_vic_irq(irq); | |
1685 | #ifdef VOYAGER_DEBUG | |
1686 | /* DEBUG: before we ack, check what's in progress */ | |
1687 | isr = vic_read_isr(); | |
1688 | if((isr & (1<<irq) && !(status & IRQ_REPLAY)) == 0) { | |
1689 | int i; | |
1690 | __u8 cpu = smp_processor_id(); | |
1691 | __u8 real_cpu; | |
1692 | int mask; /* Um... initialize me??? --RR */ | |
1693 | ||
1694 | printk("VOYAGER SMP: CPU%d lost interrupt %d\n", | |
1695 | cpu, irq); | |
1696 | for_each_cpu(real_cpu, mask) { | |
1697 | ||
1698 | outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu, | |
1699 | VIC_PROCESSOR_ID); | |
1700 | isr = vic_read_isr(); | |
1701 | if(isr & (1<<irq)) { | |
1702 | printk("VOYAGER SMP: CPU%d ack irq %d\n", | |
1703 | real_cpu, irq); | |
1704 | ack_vic_irq(irq); | |
1705 | } | |
1706 | outb(cpu, VIC_PROCESSOR_ID); | |
1707 | } | |
1708 | } | |
1709 | #endif /* VOYAGER_DEBUG */ | |
1710 | /* as soon as we ack, the interrupt is eligible for | |
1711 | * receipt by another CPU so everything must be in | |
1712 | * order here */ | |
1713 | ack_vic_irq(irq); | |
1714 | if(status & IRQ_REPLAY) { | |
1715 | /* replay is set if we disable the interrupt | |
1716 | * in the before_handle_vic_irq() routine, so | |
1717 | * clear the in progress bit here to allow the | |
1718 | * next CPU to handle this correctly */ | |
1719 | desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS); | |
1720 | } | |
1721 | #ifdef VOYAGER_DEBUG | |
1722 | isr = vic_read_isr(); | |
1723 | if((isr & (1<<irq)) != 0) | |
1724 | printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n", | |
1725 | irq, isr); | |
1726 | #endif /* VOYAGER_DEBUG */ | |
1727 | } | |
1728 | _raw_spin_unlock(&vic_irq_lock); | |
1729 | ||
1730 | /* All code after this point is out of the main path - the IRQ | |
1731 | * may be intercepted by another CPU if reasserted */ | |
1732 | } | |
1733 | ||
1734 | ||
1735 | /* Linux processor - interrupt affinity manipulations. | |
1736 | * | |
1737 | * For each processor, we maintain a 32 bit irq affinity mask. | |
1738 | * Initially it is set to all 1's so every processor accepts every | |
1739 | * interrupt. In this call, we change the processor's affinity mask: | |
1740 | * | |
1741 | * Change from enable to disable: | |
1742 | * | |
1743 | * If the interrupt ever comes in to the processor, we will disable it | |
1744 | * and ack it to push it off to another CPU, so just accept the mask here. | |
1745 | * | |
1746 | * Change from disable to enable: | |
1747 | * | |
1748 | * change the mask and then do an interrupt enable CPI to re-enable on | |
1749 | * the selected processors */ | |
1750 | ||
1751 | void | |
1752 | set_vic_irq_affinity(unsigned int irq, cpumask_t mask) | |
1753 | { | |
1754 | /* Only extended processors handle interrupts */ | |
1755 | unsigned long real_mask; | |
1756 | unsigned long irq_mask = 1 << irq; | |
1757 | int cpu; | |
1758 | ||
1759 | real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors; | |
1760 | ||
1761 | if(cpus_addr(mask)[0] == 0) | |
1762 | /* can't have no cpu's to accept the interrupt -- extremely | |
1763 | * bad things will happen */ | |
1764 | return; | |
1765 | ||
1766 | if(irq == 0) | |
1767 | /* can't change the affinity of the timer IRQ. This | |
1768 | * is due to the constraint in the voyager | |
1769 | * architecture that the CPI also comes in on and IRQ | |
1770 | * line and we have chosen IRQ0 for this. If you | |
1771 | * raise the mask on this interrupt, the processor | |
1772 | * will no-longer be able to accept VIC CPIs */ | |
1773 | return; | |
1774 | ||
1775 | if(irq >= 32) | |
1776 | /* You can only have 32 interrupts in a voyager system | |
1777 | * (and 32 only if you have a secondary microchannel | |
1778 | * bus) */ | |
1779 | return; | |
1780 | ||
1781 | for_each_online_cpu(cpu) { | |
1782 | unsigned long cpu_mask = 1 << cpu; | |
1783 | ||
1784 | if(cpu_mask & real_mask) { | |
1785 | /* enable the interrupt for this cpu */ | |
1786 | cpu_irq_affinity[cpu] |= irq_mask; | |
1787 | } else { | |
1788 | /* disable the interrupt for this cpu */ | |
1789 | cpu_irq_affinity[cpu] &= ~irq_mask; | |
1790 | } | |
1791 | } | |
1792 | /* this is magic, we now have the correct affinity maps, so | |
1793 | * enable the interrupt. This will send an enable CPI to | |
1794 | * those cpu's who need to enable it in their local masks, | |
1795 | * causing them to correct for the new affinity . If the | |
1796 | * interrupt is currently globally disabled, it will simply be | |
1797 | * disabled again as it comes in (voyager lazy disable). If | |
1798 | * the affinity map is tightened to disable the interrupt on a | |
1799 | * cpu, it will be pushed off when it comes in */ | |
1800 | enable_vic_irq(irq); | |
1801 | } | |
1802 | ||
1803 | static void | |
1804 | ack_vic_irq(unsigned int irq) | |
1805 | { | |
1806 | if (irq & 8) { | |
1807 | outb(0x62,0x20); /* Specific EOI to cascade */ | |
1808 | outb(0x60|(irq & 7),0xA0); | |
1809 | } else { | |
1810 | outb(0x60 | (irq & 7),0x20); | |
1811 | } | |
1812 | } | |
1813 | ||
1814 | /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259 | |
1815 | * but are not vectored by it. This means that the 8259 mask must be | |
1816 | * lowered to receive them */ | |
1817 | static __init void | |
1818 | vic_enable_cpi(void) | |
1819 | { | |
1820 | __u8 cpu = smp_processor_id(); | |
1821 | ||
1822 | /* just take a copy of the current mask (nop for boot cpu) */ | |
1823 | vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id]; | |
1824 | ||
1825 | enable_local_vic_irq(VIC_CPI_LEVEL0); | |
1826 | enable_local_vic_irq(VIC_CPI_LEVEL1); | |
1827 | /* for sys int and cmn int */ | |
1828 | enable_local_vic_irq(7); | |
1829 | ||
1830 | if(is_cpu_quad()) { | |
1831 | outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0); | |
1832 | outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1); | |
1833 | VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n", | |
1834 | cpu, QIC_CPI_ENABLE)); | |
1835 | } | |
1836 | ||
1837 | VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n", | |
1838 | cpu, vic_irq_mask[cpu])); | |
1839 | } | |
1840 | ||
1841 | void | |
1842 | voyager_smp_dump() | |
1843 | { | |
1844 | int old_cpu = smp_processor_id(), cpu; | |
1845 | ||
1846 | /* dump the interrupt masks of each processor */ | |
1847 | for_each_online_cpu(cpu) { | |
1848 | __u16 imr, isr, irr; | |
1849 | unsigned long flags; | |
1850 | ||
1851 | local_irq_save(flags); | |
1852 | outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID); | |
1853 | imr = (inb(0xa1) << 8) | inb(0x21); | |
1854 | outb(0x0a, 0xa0); | |
1855 | irr = inb(0xa0) << 8; | |
1856 | outb(0x0a, 0x20); | |
1857 | irr |= inb(0x20); | |
1858 | outb(0x0b, 0xa0); | |
1859 | isr = inb(0xa0) << 8; | |
1860 | outb(0x0b, 0x20); | |
1861 | isr |= inb(0x20); | |
1862 | outb(old_cpu, VIC_PROCESSOR_ID); | |
1863 | local_irq_restore(flags); | |
1864 | printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n", | |
1865 | cpu, vic_irq_mask[cpu], imr, irr, isr); | |
1866 | #if 0 | |
1867 | /* These lines are put in to try to unstick an un ack'd irq */ | |
1868 | if(isr != 0) { | |
1869 | int irq; | |
1870 | for(irq=0; irq<16; irq++) { | |
1871 | if(isr & (1<<irq)) { | |
1872 | printk("\tCPU%d: ack irq %d\n", | |
1873 | cpu, irq); | |
1874 | local_irq_save(flags); | |
1875 | outb(VIC_CPU_MASQUERADE_ENABLE | cpu, | |
1876 | VIC_PROCESSOR_ID); | |
1877 | ack_vic_irq(irq); | |
1878 | outb(old_cpu, VIC_PROCESSOR_ID); | |
1879 | local_irq_restore(flags); | |
1880 | } | |
1881 | } | |
1882 | } | |
1883 | #endif | |
1884 | } | |
1885 | } | |
1886 | ||
1887 | void | |
1888 | smp_voyager_power_off(void *dummy) | |
1889 | { | |
1890 | if(smp_processor_id() == boot_cpu_id) | |
1891 | voyager_power_off(); | |
1892 | else | |
1893 | smp_stop_cpu_function(NULL); | |
1894 | } | |
1895 | ||
1896 | void __init | |
1897 | smp_prepare_cpus(unsigned int max_cpus) | |
1898 | { | |
1899 | /* FIXME: ignore max_cpus for now */ | |
1900 | smp_boot_cpus(); | |
1901 | } | |
1902 | ||
1903 | void __devinit smp_prepare_boot_cpu(void) | |
1904 | { | |
1905 | cpu_set(smp_processor_id(), cpu_online_map); | |
1906 | cpu_set(smp_processor_id(), cpu_callout_map); | |
1907 | } | |
1908 | ||
1909 | int __devinit | |
1910 | __cpu_up(unsigned int cpu) | |
1911 | { | |
1912 | /* This only works at boot for x86. See "rewrite" above. */ | |
1913 | if (cpu_isset(cpu, smp_commenced_mask)) | |
1914 | return -ENOSYS; | |
1915 | ||
1916 | /* In case one didn't come up */ | |
1917 | if (!cpu_isset(cpu, cpu_callin_map)) | |
1918 | return -EIO; | |
1919 | /* Unleash the CPU! */ | |
1920 | cpu_set(cpu, smp_commenced_mask); | |
1921 | while (!cpu_isset(cpu, cpu_online_map)) | |
1922 | mb(); | |
1923 | return 0; | |
1924 | } | |
1925 | ||
1926 | void __init | |
1927 | smp_cpus_done(unsigned int max_cpus) | |
1928 | { | |
1929 | zap_low_mappings(); | |
1930 | } |