Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Low-Level PCI Support for PC -- Routing of Interrupts | |
3 | * | |
4 | * (c) 1999--2000 Martin Mares <mj@ucw.cz> | |
5 | */ | |
6 | ||
7 | #include <linux/config.h> | |
8 | #include <linux/types.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/pci.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/dmi.h> | |
16 | #include <asm/io.h> | |
17 | #include <asm/smp.h> | |
18 | #include <asm/io_apic.h> | |
19 | #include <asm/hw_irq.h> | |
20 | #include <linux/acpi.h> | |
21 | ||
22 | #include "pci.h" | |
23 | ||
24 | #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) | |
25 | #define PIRQ_VERSION 0x0100 | |
26 | ||
27 | static int broken_hp_bios_irq9; | |
28 | static int acer_tm360_irqrouting; | |
29 | ||
30 | static struct irq_routing_table *pirq_table; | |
31 | ||
32 | static int pirq_enable_irq(struct pci_dev *dev); | |
33 | ||
34 | /* | |
35 | * Never use: 0, 1, 2 (timer, keyboard, and cascade) | |
36 | * Avoid using: 13, 14 and 15 (FP error and IDE). | |
37 | * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) | |
38 | */ | |
39 | unsigned int pcibios_irq_mask = 0xfff8; | |
40 | ||
41 | static int pirq_penalty[16] = { | |
42 | 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, | |
43 | 0, 0, 0, 0, 1000, 100000, 100000, 100000 | |
44 | }; | |
45 | ||
46 | struct irq_router { | |
47 | char *name; | |
48 | u16 vendor, device; | |
49 | int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq); | |
50 | int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new); | |
51 | }; | |
52 | ||
53 | struct irq_router_handler { | |
54 | u16 vendor; | |
55 | int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device); | |
56 | }; | |
57 | ||
58 | int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL; | |
59 | ||
60 | /* | |
61 | * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. | |
62 | */ | |
63 | ||
64 | static struct irq_routing_table * __init pirq_find_routing_table(void) | |
65 | { | |
66 | u8 *addr; | |
67 | struct irq_routing_table *rt; | |
68 | int i; | |
69 | u8 sum; | |
70 | ||
71 | for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { | |
72 | rt = (struct irq_routing_table *) addr; | |
73 | if (rt->signature != PIRQ_SIGNATURE || | |
74 | rt->version != PIRQ_VERSION || | |
75 | rt->size % 16 || | |
76 | rt->size < sizeof(struct irq_routing_table)) | |
77 | continue; | |
78 | sum = 0; | |
79 | for(i=0; i<rt->size; i++) | |
80 | sum += addr[i]; | |
81 | if (!sum) { | |
82 | DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt); | |
83 | return rt; | |
84 | } | |
85 | } | |
86 | return NULL; | |
87 | } | |
88 | ||
89 | /* | |
90 | * If we have a IRQ routing table, use it to search for peer host | |
91 | * bridges. It's a gross hack, but since there are no other known | |
92 | * ways how to get a list of buses, we have to go this way. | |
93 | */ | |
94 | ||
95 | static void __init pirq_peer_trick(void) | |
96 | { | |
97 | struct irq_routing_table *rt = pirq_table; | |
98 | u8 busmap[256]; | |
99 | int i; | |
100 | struct irq_info *e; | |
101 | ||
102 | memset(busmap, 0, sizeof(busmap)); | |
103 | for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { | |
104 | e = &rt->slots[i]; | |
105 | #ifdef DEBUG | |
106 | { | |
107 | int j; | |
108 | DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); | |
109 | for(j=0; j<4; j++) | |
110 | DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); | |
111 | DBG("\n"); | |
112 | } | |
113 | #endif | |
114 | busmap[e->bus] = 1; | |
115 | } | |
116 | for(i = 1; i < 256; i++) { | |
117 | if (!busmap[i] || pci_find_bus(0, i)) | |
118 | continue; | |
119 | if (pci_scan_bus(i, &pci_root_ops, NULL)) | |
120 | printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i); | |
121 | } | |
122 | pcibios_last_bus = -1; | |
123 | } | |
124 | ||
125 | /* | |
126 | * Code for querying and setting of IRQ routes on various interrupt routers. | |
127 | */ | |
128 | ||
129 | void eisa_set_level_irq(unsigned int irq) | |
130 | { | |
131 | unsigned char mask = 1 << (irq & 7); | |
132 | unsigned int port = 0x4d0 + (irq >> 3); | |
133 | unsigned char val; | |
134 | static u16 eisa_irq_mask; | |
135 | ||
136 | if (irq >= 16 || (1 << irq) & eisa_irq_mask) | |
137 | return; | |
138 | ||
139 | eisa_irq_mask |= (1 << irq); | |
140 | printk("PCI: setting IRQ %u as level-triggered\n", irq); | |
141 | val = inb(port); | |
142 | if (!(val & mask)) { | |
143 | DBG(" -> edge"); | |
144 | outb(val | mask, port); | |
145 | } | |
146 | } | |
147 | ||
148 | /* | |
149 | * Common IRQ routing practice: nybbles in config space, | |
150 | * offset by some magic constant. | |
151 | */ | |
152 | static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) | |
153 | { | |
154 | u8 x; | |
155 | unsigned reg = offset + (nr >> 1); | |
156 | ||
157 | pci_read_config_byte(router, reg, &x); | |
158 | return (nr & 1) ? (x >> 4) : (x & 0xf); | |
159 | } | |
160 | ||
161 | static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val) | |
162 | { | |
163 | u8 x; | |
164 | unsigned reg = offset + (nr >> 1); | |
165 | ||
166 | pci_read_config_byte(router, reg, &x); | |
167 | x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); | |
168 | pci_write_config_byte(router, reg, x); | |
169 | } | |
170 | ||
171 | /* | |
172 | * ALI pirq entries are damn ugly, and completely undocumented. | |
173 | * This has been figured out from pirq tables, and it's not a pretty | |
174 | * picture. | |
175 | */ | |
176 | static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) | |
177 | { | |
178 | static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; | |
179 | ||
180 | return irqmap[read_config_nybble(router, 0x48, pirq-1)]; | |
181 | } | |
182 | ||
183 | static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) | |
184 | { | |
185 | static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; | |
186 | unsigned int val = irqmap[irq]; | |
187 | ||
188 | if (val) { | |
189 | write_config_nybble(router, 0x48, pirq-1, val); | |
190 | return 1; | |
191 | } | |
192 | return 0; | |
193 | } | |
194 | ||
195 | /* | |
196 | * The Intel PIIX4 pirq rules are fairly simple: "pirq" is | |
197 | * just a pointer to the config space. | |
198 | */ | |
199 | static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) | |
200 | { | |
201 | u8 x; | |
202 | ||
203 | pci_read_config_byte(router, pirq, &x); | |
204 | return (x < 16) ? x : 0; | |
205 | } | |
206 | ||
207 | static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) | |
208 | { | |
209 | pci_write_config_byte(router, pirq, irq); | |
210 | return 1; | |
211 | } | |
212 | ||
213 | /* | |
214 | * The VIA pirq rules are nibble-based, like ALI, | |
215 | * but without the ugly irq number munging. | |
216 | * However, PIRQD is in the upper instead of lower 4 bits. | |
217 | */ | |
218 | static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) | |
219 | { | |
220 | return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); | |
221 | } | |
222 | ||
223 | static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) | |
224 | { | |
225 | write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); | |
226 | return 1; | |
227 | } | |
228 | ||
229 | /* | |
230 | * ITE 8330G pirq rules are nibble-based | |
231 | * FIXME: pirqmap may be { 1, 0, 3, 2 }, | |
232 | * 2+3 are both mapped to irq 9 on my system | |
233 | */ | |
234 | static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) | |
235 | { | |
236 | static unsigned char pirqmap[4] = { 1, 0, 2, 3 }; | |
237 | return read_config_nybble(router,0x43, pirqmap[pirq-1]); | |
238 | } | |
239 | ||
240 | static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) | |
241 | { | |
242 | static unsigned char pirqmap[4] = { 1, 0, 2, 3 }; | |
243 | write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); | |
244 | return 1; | |
245 | } | |
246 | ||
247 | /* | |
248 | * OPTI: high four bits are nibble pointer.. | |
249 | * I wonder what the low bits do? | |
250 | */ | |
251 | static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) | |
252 | { | |
253 | return read_config_nybble(router, 0xb8, pirq >> 4); | |
254 | } | |
255 | ||
256 | static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) | |
257 | { | |
258 | write_config_nybble(router, 0xb8, pirq >> 4, irq); | |
259 | return 1; | |
260 | } | |
261 | ||
262 | /* | |
263 | * Cyrix: nibble offset 0x5C | |
264 | * 0x5C bits 7:4 is INTB bits 3:0 is INTA | |
265 | * 0x5D bits 7:4 is INTD bits 3:0 is INTC | |
266 | */ | |
267 | static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) | |
268 | { | |
269 | return read_config_nybble(router, 0x5C, (pirq-1)^1); | |
270 | } | |
271 | ||
272 | static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) | |
273 | { | |
274 | write_config_nybble(router, 0x5C, (pirq-1)^1, irq); | |
275 | return 1; | |
276 | } | |
277 | ||
278 | /* | |
279 | * PIRQ routing for SiS 85C503 router used in several SiS chipsets. | |
280 | * We have to deal with the following issues here: | |
281 | * - vendors have different ideas about the meaning of link values | |
282 | * - some onboard devices (integrated in the chipset) have special | |
283 | * links and are thus routed differently (i.e. not via PCI INTA-INTD) | |
284 | * - different revision of the router have a different layout for | |
285 | * the routing registers, particularly for the onchip devices | |
286 | * | |
287 | * For all routing registers the common thing is we have one byte | |
288 | * per routeable link which is defined as: | |
289 | * bit 7 IRQ mapping enabled (0) or disabled (1) | |
290 | * bits [6:4] reserved (sometimes used for onchip devices) | |
291 | * bits [3:0] IRQ to map to | |
292 | * allowed: 3-7, 9-12, 14-15 | |
293 | * reserved: 0, 1, 2, 8, 13 | |
294 | * | |
295 | * The config-space registers located at 0x41/0x42/0x43/0x44 are | |
296 | * always used to route the normal PCI INT A/B/C/D respectively. | |
297 | * Apparently there are systems implementing PCI routing table using | |
298 | * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D. | |
299 | * We try our best to handle both link mappings. | |
300 | * | |
301 | * Currently (2003-05-21) it appears most SiS chipsets follow the | |
302 | * definition of routing registers from the SiS-5595 southbridge. | |
303 | * According to the SiS 5595 datasheets the revision id's of the | |
304 | * router (ISA-bridge) should be 0x01 or 0xb0. | |
305 | * | |
306 | * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1. | |
307 | * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets. | |
308 | * They seem to work with the current routing code. However there is | |
309 | * some concern because of the two USB-OHCI HCs (original SiS 5595 | |
310 | * had only one). YMMV. | |
311 | * | |
312 | * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1: | |
313 | * | |
314 | * 0x61: IDEIRQ: | |
315 | * bits [6:5] must be written 01 | |
316 | * bit 4 channel-select primary (0), secondary (1) | |
317 | * | |
318 | * 0x62: USBIRQ: | |
319 | * bit 6 OHCI function disabled (0), enabled (1) | |
320 | * | |
321 | * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved | |
322 | * | |
323 | * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved | |
324 | * | |
325 | * We support USBIRQ (in addition to INTA-INTD) and keep the | |
326 | * IDE, ACPI and DAQ routing untouched as set by the BIOS. | |
327 | * | |
328 | * Currently the only reported exception is the new SiS 65x chipset | |
329 | * which includes the SiS 69x southbridge. Here we have the 85C503 | |
330 | * router revision 0x04 and there are changes in the register layout | |
331 | * mostly related to the different USB HCs with USB 2.0 support. | |
332 | * | |
333 | * Onchip routing for router rev-id 0x04 (try-and-error observation) | |
334 | * | |
335 | * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs | |
336 | * bit 6-4 are probably unused, not like 5595 | |
337 | */ | |
338 | ||
339 | #define PIRQ_SIS_IRQ_MASK 0x0f | |
340 | #define PIRQ_SIS_IRQ_DISABLE 0x80 | |
341 | #define PIRQ_SIS_USB_ENABLE 0x40 | |
342 | ||
343 | static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq) | |
344 | { | |
345 | u8 x; | |
346 | int reg; | |
347 | ||
348 | reg = pirq; | |
349 | if (reg >= 0x01 && reg <= 0x04) | |
350 | reg += 0x40; | |
351 | pci_read_config_byte(router, reg, &x); | |
352 | return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK); | |
353 | } | |
354 | ||
355 | static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) | |
356 | { | |
357 | u8 x; | |
358 | int reg; | |
359 | ||
360 | reg = pirq; | |
361 | if (reg >= 0x01 && reg <= 0x04) | |
362 | reg += 0x40; | |
363 | pci_read_config_byte(router, reg, &x); | |
364 | x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE); | |
365 | x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE; | |
366 | pci_write_config_byte(router, reg, x); | |
367 | return 1; | |
368 | } | |
369 | ||
370 | ||
371 | /* | |
372 | * VLSI: nibble offset 0x74 - educated guess due to routing table and | |
373 | * config space of VLSI 82C534 PCI-bridge/router (1004:0102) | |
374 | * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard | |
375 | * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 | |
376 | * for the busbridge to the docking station. | |
377 | */ | |
378 | ||
379 | static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) | |
380 | { | |
381 | if (pirq > 8) { | |
382 | printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq); | |
383 | return 0; | |
384 | } | |
385 | return read_config_nybble(router, 0x74, pirq-1); | |
386 | } | |
387 | ||
388 | static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) | |
389 | { | |
390 | if (pirq > 8) { | |
391 | printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq); | |
392 | return 0; | |
393 | } | |
394 | write_config_nybble(router, 0x74, pirq-1, irq); | |
395 | return 1; | |
396 | } | |
397 | ||
398 | /* | |
399 | * ServerWorks: PCI interrupts mapped to system IRQ lines through Index | |
400 | * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register | |
401 | * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect | |
402 | * register is a straight binary coding of desired PIC IRQ (low nibble). | |
403 | * | |
404 | * The 'link' value in the PIRQ table is already in the correct format | |
405 | * for the Index register. There are some special index values: | |
406 | * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, | |
407 | * and 0x03 for SMBus. | |
408 | */ | |
409 | static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) | |
410 | { | |
411 | outb_p(pirq, 0xc00); | |
412 | return inb(0xc01) & 0xf; | |
413 | } | |
414 | ||
415 | static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) | |
416 | { | |
417 | outb_p(pirq, 0xc00); | |
418 | outb_p(irq, 0xc01); | |
419 | return 1; | |
420 | } | |
421 | ||
422 | /* Support for AMD756 PCI IRQ Routing | |
423 | * Jhon H. Caicedo <jhcaiced@osso.org.co> | |
424 | * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) | |
425 | * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) | |
426 | * The AMD756 pirq rules are nibble-based | |
427 | * offset 0x56 0-3 PIRQA 4-7 PIRQB | |
428 | * offset 0x57 0-3 PIRQC 4-7 PIRQD | |
429 | */ | |
430 | static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) | |
431 | { | |
432 | u8 irq; | |
433 | irq = 0; | |
434 | if (pirq <= 4) | |
435 | { | |
436 | irq = read_config_nybble(router, 0x56, pirq - 1); | |
437 | } | |
438 | printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n", | |
439 | dev->vendor, dev->device, pirq, irq); | |
440 | return irq; | |
441 | } | |
442 | ||
443 | static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) | |
444 | { | |
445 | printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n", | |
446 | dev->vendor, dev->device, pirq, irq); | |
447 | if (pirq <= 4) | |
448 | { | |
449 | write_config_nybble(router, 0x56, pirq - 1, irq); | |
450 | } | |
451 | return 1; | |
452 | } | |
453 | ||
454 | #ifdef CONFIG_PCI_BIOS | |
455 | ||
456 | static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) | |
457 | { | |
458 | struct pci_dev *bridge; | |
459 | int pin = pci_get_interrupt_pin(dev, &bridge); | |
460 | return pcibios_set_irq_routing(bridge, pin, irq); | |
461 | } | |
462 | ||
463 | #endif | |
464 | ||
465 | static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) | |
466 | { | |
467 | static struct pci_device_id pirq_440gx[] = { | |
468 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) }, | |
469 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) }, | |
470 | { }, | |
471 | }; | |
472 | ||
473 | /* 440GX has a proprietary PIRQ router -- don't use it */ | |
474 | if (pci_dev_present(pirq_440gx)) | |
475 | return 0; | |
476 | ||
477 | switch(device) | |
478 | { | |
479 | case PCI_DEVICE_ID_INTEL_82371FB_0: | |
480 | case PCI_DEVICE_ID_INTEL_82371SB_0: | |
481 | case PCI_DEVICE_ID_INTEL_82371AB_0: | |
482 | case PCI_DEVICE_ID_INTEL_82371MX: | |
483 | case PCI_DEVICE_ID_INTEL_82443MX_0: | |
484 | case PCI_DEVICE_ID_INTEL_82801AA_0: | |
485 | case PCI_DEVICE_ID_INTEL_82801AB_0: | |
486 | case PCI_DEVICE_ID_INTEL_82801BA_0: | |
487 | case PCI_DEVICE_ID_INTEL_82801BA_10: | |
488 | case PCI_DEVICE_ID_INTEL_82801CA_0: | |
489 | case PCI_DEVICE_ID_INTEL_82801CA_12: | |
490 | case PCI_DEVICE_ID_INTEL_82801DB_0: | |
491 | case PCI_DEVICE_ID_INTEL_82801E_0: | |
492 | case PCI_DEVICE_ID_INTEL_82801EB_0: | |
493 | case PCI_DEVICE_ID_INTEL_ESB_1: | |
494 | case PCI_DEVICE_ID_INTEL_ICH6_0: | |
495 | case PCI_DEVICE_ID_INTEL_ICH6_1: | |
496 | case PCI_DEVICE_ID_INTEL_ICH7_0: | |
497 | case PCI_DEVICE_ID_INTEL_ICH7_1: | |
498 | r->name = "PIIX/ICH"; | |
499 | r->get = pirq_piix_get; | |
500 | r->set = pirq_piix_set; | |
501 | return 1; | |
502 | } | |
503 | return 0; | |
504 | } | |
505 | ||
506 | static __init int via_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) | |
507 | { | |
508 | /* FIXME: We should move some of the quirk fixup stuff here */ | |
509 | switch(device) | |
510 | { | |
511 | case PCI_DEVICE_ID_VIA_82C586_0: | |
512 | case PCI_DEVICE_ID_VIA_82C596: | |
513 | case PCI_DEVICE_ID_VIA_82C686: | |
514 | case PCI_DEVICE_ID_VIA_8231: | |
515 | /* FIXME: add new ones for 8233/5 */ | |
516 | r->name = "VIA"; | |
517 | r->get = pirq_via_get; | |
518 | r->set = pirq_via_set; | |
519 | return 1; | |
520 | } | |
521 | return 0; | |
522 | } | |
523 | ||
524 | static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) | |
525 | { | |
526 | switch(device) | |
527 | { | |
528 | case PCI_DEVICE_ID_VLSI_82C534: | |
529 | r->name = "VLSI 82C534"; | |
530 | r->get = pirq_vlsi_get; | |
531 | r->set = pirq_vlsi_set; | |
532 | return 1; | |
533 | } | |
534 | return 0; | |
535 | } | |
536 | ||
537 | ||
538 | static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) | |
539 | { | |
540 | switch(device) | |
541 | { | |
542 | case PCI_DEVICE_ID_SERVERWORKS_OSB4: | |
543 | case PCI_DEVICE_ID_SERVERWORKS_CSB5: | |
544 | r->name = "ServerWorks"; | |
545 | r->get = pirq_serverworks_get; | |
546 | r->set = pirq_serverworks_set; | |
547 | return 1; | |
548 | } | |
549 | return 0; | |
550 | } | |
551 | ||
552 | static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) | |
553 | { | |
554 | if (device != PCI_DEVICE_ID_SI_503) | |
555 | return 0; | |
556 | ||
557 | r->name = "SIS"; | |
558 | r->get = pirq_sis_get; | |
559 | r->set = pirq_sis_set; | |
560 | return 1; | |
561 | } | |
562 | ||
563 | static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) | |
564 | { | |
565 | switch(device) | |
566 | { | |
567 | case PCI_DEVICE_ID_CYRIX_5520: | |
568 | r->name = "NatSemi"; | |
569 | r->get = pirq_cyrix_get; | |
570 | r->set = pirq_cyrix_set; | |
571 | return 1; | |
572 | } | |
573 | return 0; | |
574 | } | |
575 | ||
576 | static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) | |
577 | { | |
578 | switch(device) | |
579 | { | |
580 | case PCI_DEVICE_ID_OPTI_82C700: | |
581 | r->name = "OPTI"; | |
582 | r->get = pirq_opti_get; | |
583 | r->set = pirq_opti_set; | |
584 | return 1; | |
585 | } | |
586 | return 0; | |
587 | } | |
588 | ||
589 | static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) | |
590 | { | |
591 | switch(device) | |
592 | { | |
593 | case PCI_DEVICE_ID_ITE_IT8330G_0: | |
594 | r->name = "ITE"; | |
595 | r->get = pirq_ite_get; | |
596 | r->set = pirq_ite_set; | |
597 | return 1; | |
598 | } | |
599 | return 0; | |
600 | } | |
601 | ||
602 | static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) | |
603 | { | |
604 | switch(device) | |
605 | { | |
606 | case PCI_DEVICE_ID_AL_M1533: | |
607 | case PCI_DEVICE_ID_AL_M1563: | |
608 | printk("PCI: Using ALI IRQ Router\n"); | |
609 | r->name = "ALI"; | |
610 | r->get = pirq_ali_get; | |
611 | r->set = pirq_ali_set; | |
612 | return 1; | |
613 | } | |
614 | return 0; | |
615 | } | |
616 | ||
617 | static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) | |
618 | { | |
619 | switch(device) | |
620 | { | |
621 | case PCI_DEVICE_ID_AMD_VIPER_740B: | |
622 | r->name = "AMD756"; | |
623 | break; | |
624 | case PCI_DEVICE_ID_AMD_VIPER_7413: | |
625 | r->name = "AMD766"; | |
626 | break; | |
627 | case PCI_DEVICE_ID_AMD_VIPER_7443: | |
628 | r->name = "AMD768"; | |
629 | break; | |
630 | default: | |
631 | return 0; | |
632 | } | |
633 | r->get = pirq_amd756_get; | |
634 | r->set = pirq_amd756_set; | |
635 | return 1; | |
636 | } | |
637 | ||
638 | static __initdata struct irq_router_handler pirq_routers[] = { | |
639 | { PCI_VENDOR_ID_INTEL, intel_router_probe }, | |
640 | { PCI_VENDOR_ID_AL, ali_router_probe }, | |
641 | { PCI_VENDOR_ID_ITE, ite_router_probe }, | |
642 | { PCI_VENDOR_ID_VIA, via_router_probe }, | |
643 | { PCI_VENDOR_ID_OPTI, opti_router_probe }, | |
644 | { PCI_VENDOR_ID_SI, sis_router_probe }, | |
645 | { PCI_VENDOR_ID_CYRIX, cyrix_router_probe }, | |
646 | { PCI_VENDOR_ID_VLSI, vlsi_router_probe }, | |
647 | { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe }, | |
648 | { PCI_VENDOR_ID_AMD, amd_router_probe }, | |
649 | /* Someone with docs needs to add the ATI Radeon IGP */ | |
650 | { 0, NULL } | |
651 | }; | |
652 | static struct irq_router pirq_router; | |
653 | static struct pci_dev *pirq_router_dev; | |
654 | ||
655 | ||
656 | /* | |
657 | * FIXME: should we have an option to say "generic for | |
658 | * chipset" ? | |
659 | */ | |
660 | ||
661 | static void __init pirq_find_router(struct irq_router *r) | |
662 | { | |
663 | struct irq_routing_table *rt = pirq_table; | |
664 | struct irq_router_handler *h; | |
665 | ||
666 | #ifdef CONFIG_PCI_BIOS | |
667 | if (!rt->signature) { | |
668 | printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n"); | |
669 | r->set = pirq_bios_set; | |
670 | r->name = "BIOS"; | |
671 | return; | |
672 | } | |
673 | #endif | |
674 | ||
675 | /* Default unless a driver reloads it */ | |
676 | r->name = "default"; | |
677 | r->get = NULL; | |
678 | r->set = NULL; | |
679 | ||
680 | DBG("PCI: Attempting to find IRQ router for %04x:%04x\n", | |
681 | rt->rtr_vendor, rt->rtr_device); | |
682 | ||
683 | pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn); | |
684 | if (!pirq_router_dev) { | |
685 | DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn); | |
686 | return; | |
687 | } | |
688 | ||
689 | for( h = pirq_routers; h->vendor; h++) { | |
690 | /* First look for a router match */ | |
691 | if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device)) | |
692 | break; | |
693 | /* Fall back to a device match */ | |
694 | if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device)) | |
695 | break; | |
696 | } | |
697 | printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n", | |
698 | pirq_router.name, | |
699 | pirq_router_dev->vendor, | |
700 | pirq_router_dev->device, | |
701 | pci_name(pirq_router_dev)); | |
702 | } | |
703 | ||
704 | static struct irq_info *pirq_get_info(struct pci_dev *dev) | |
705 | { | |
706 | struct irq_routing_table *rt = pirq_table; | |
707 | int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); | |
708 | struct irq_info *info; | |
709 | ||
710 | for (info = rt->slots; entries--; info++) | |
711 | if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn)) | |
712 | return info; | |
713 | return NULL; | |
714 | } | |
715 | ||
716 | static int pcibios_lookup_irq(struct pci_dev *dev, int assign) | |
717 | { | |
718 | u8 pin; | |
719 | struct irq_info *info; | |
720 | int i, pirq, newirq; | |
721 | int irq = 0; | |
722 | u32 mask; | |
723 | struct irq_router *r = &pirq_router; | |
724 | struct pci_dev *dev2 = NULL; | |
725 | char *msg = NULL; | |
726 | ||
727 | /* Find IRQ pin */ | |
728 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); | |
729 | if (!pin) { | |
730 | DBG(" -> no interrupt pin\n"); | |
731 | return 0; | |
732 | } | |
733 | pin = pin - 1; | |
734 | ||
735 | /* Find IRQ routing entry */ | |
736 | ||
737 | if (!pirq_table) | |
738 | return 0; | |
739 | ||
740 | DBG("IRQ for %s[%c]", pci_name(dev), 'A' + pin); | |
741 | info = pirq_get_info(dev); | |
742 | if (!info) { | |
743 | DBG(" -> not found in routing table\n"); | |
744 | return 0; | |
745 | } | |
746 | pirq = info->irq[pin].link; | |
747 | mask = info->irq[pin].bitmap; | |
748 | if (!pirq) { | |
749 | DBG(" -> not routed\n"); | |
750 | return 0; | |
751 | } | |
752 | DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs); | |
753 | mask &= pcibios_irq_mask; | |
754 | ||
755 | /* Work around broken HP Pavilion Notebooks which assign USB to | |
756 | IRQ 9 even though it is actually wired to IRQ 11 */ | |
757 | ||
758 | if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { | |
759 | dev->irq = 11; | |
760 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); | |
761 | r->set(pirq_router_dev, dev, pirq, 11); | |
762 | } | |
763 | ||
764 | /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */ | |
765 | if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) { | |
766 | pirq = 0x68; | |
767 | mask = 0x400; | |
768 | dev->irq = r->get(pirq_router_dev, dev, pirq); | |
769 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); | |
770 | } | |
771 | ||
772 | /* | |
773 | * Find the best IRQ to assign: use the one | |
774 | * reported by the device if possible. | |
775 | */ | |
776 | newirq = dev->irq; | |
777 | if (!((1 << newirq) & mask)) { | |
778 | if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0; | |
779 | else printk(KERN_WARNING "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n", newirq, pci_name(dev)); | |
780 | } | |
781 | if (!newirq && assign) { | |
782 | for (i = 0; i < 16; i++) { | |
783 | if (!(mask & (1 << i))) | |
784 | continue; | |
785 | if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, SA_SHIRQ)) | |
786 | newirq = i; | |
787 | } | |
788 | } | |
789 | DBG(" -> newirq=%d", newirq); | |
790 | ||
791 | /* Check if it is hardcoded */ | |
792 | if ((pirq & 0xf0) == 0xf0) { | |
793 | irq = pirq & 0xf; | |
794 | DBG(" -> hardcoded IRQ %d\n", irq); | |
795 | msg = "Hardcoded"; | |
796 | } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \ | |
797 | ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) { | |
798 | DBG(" -> got IRQ %d\n", irq); | |
799 | msg = "Found"; | |
800 | } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { | |
801 | DBG(" -> assigning IRQ %d", newirq); | |
802 | if (r->set(pirq_router_dev, dev, pirq, newirq)) { | |
803 | eisa_set_level_irq(newirq); | |
804 | DBG(" ... OK\n"); | |
805 | msg = "Assigned"; | |
806 | irq = newirq; | |
807 | } | |
808 | } | |
809 | ||
810 | if (!irq) { | |
811 | DBG(" ... failed\n"); | |
812 | if (newirq && mask == (1 << newirq)) { | |
813 | msg = "Guessed"; | |
814 | irq = newirq; | |
815 | } else | |
816 | return 0; | |
817 | } | |
818 | printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev)); | |
819 | ||
820 | /* Update IRQ for all devices with the same pirq value */ | |
821 | while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) { | |
822 | pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin); | |
823 | if (!pin) | |
824 | continue; | |
825 | pin--; | |
826 | info = pirq_get_info(dev2); | |
827 | if (!info) | |
828 | continue; | |
829 | if (info->irq[pin].link == pirq) { | |
830 | /* We refuse to override the dev->irq information. Give a warning! */ | |
831 | if ( dev2->irq && dev2->irq != irq && \ | |
832 | (!(pci_probe & PCI_USE_PIRQ_MASK) || \ | |
833 | ((1 << dev2->irq) & mask)) ) { | |
834 | #ifndef CONFIG_PCI_MSI | |
835 | printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n", | |
836 | pci_name(dev2), dev2->irq, irq); | |
837 | #endif | |
838 | continue; | |
839 | } | |
840 | dev2->irq = irq; | |
841 | pirq_penalty[irq]++; | |
842 | if (dev != dev2) | |
843 | printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2)); | |
844 | } | |
845 | } | |
846 | return 1; | |
847 | } | |
848 | ||
849 | static void __init pcibios_fixup_irqs(void) | |
850 | { | |
851 | struct pci_dev *dev = NULL; | |
852 | u8 pin; | |
853 | ||
854 | DBG("PCI: IRQ fixup\n"); | |
855 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
856 | /* | |
857 | * If the BIOS has set an out of range IRQ number, just ignore it. | |
858 | * Also keep track of which IRQ's are already in use. | |
859 | */ | |
860 | if (dev->irq >= 16) { | |
861 | DBG("%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq); | |
862 | dev->irq = 0; | |
863 | } | |
864 | /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */ | |
865 | if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000) | |
866 | pirq_penalty[dev->irq] = 0; | |
867 | pirq_penalty[dev->irq]++; | |
868 | } | |
869 | ||
870 | dev = NULL; | |
871 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
872 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); | |
873 | #ifdef CONFIG_X86_IO_APIC | |
874 | /* | |
875 | * Recalculate IRQ numbers if we use the I/O APIC. | |
876 | */ | |
877 | if (io_apic_assign_pci_irqs) | |
878 | { | |
879 | int irq; | |
880 | ||
881 | if (pin) { | |
882 | pin--; /* interrupt pins are numbered starting from 1 */ | |
883 | irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin); | |
884 | /* | |
885 | * Busses behind bridges are typically not listed in the MP-table. | |
886 | * In this case we have to look up the IRQ based on the parent bus, | |
887 | * parent slot, and pin number. The SMP code detects such bridged | |
888 | * busses itself so we should get into this branch reliably. | |
889 | */ | |
890 | if (irq < 0 && dev->bus->parent) { /* go back to the bridge */ | |
891 | struct pci_dev * bridge = dev->bus->self; | |
892 | ||
893 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
894 | irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, | |
895 | PCI_SLOT(bridge->devfn), pin); | |
896 | if (irq >= 0) | |
897 | printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n", | |
898 | pci_name(bridge), 'A' + pin, irq); | |
899 | } | |
900 | if (irq >= 0) { | |
901 | if (use_pci_vector() && | |
902 | !platform_legacy_irq(irq)) | |
903 | irq = IO_APIC_VECTOR(irq); | |
904 | ||
905 | printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n", | |
906 | pci_name(dev), 'A' + pin, irq); | |
907 | dev->irq = irq; | |
908 | } | |
909 | } | |
910 | } | |
911 | #endif | |
912 | /* | |
913 | * Still no IRQ? Try to lookup one... | |
914 | */ | |
915 | if (pin && !dev->irq) | |
916 | pcibios_lookup_irq(dev, 0); | |
917 | } | |
918 | } | |
919 | ||
920 | /* | |
921 | * Work around broken HP Pavilion Notebooks which assign USB to | |
922 | * IRQ 9 even though it is actually wired to IRQ 11 | |
923 | */ | |
924 | static int __init fix_broken_hp_bios_irq9(struct dmi_system_id *d) | |
925 | { | |
926 | if (!broken_hp_bios_irq9) { | |
927 | broken_hp_bios_irq9 = 1; | |
928 | printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident); | |
929 | } | |
930 | return 0; | |
931 | } | |
932 | ||
933 | /* | |
934 | * Work around broken Acer TravelMate 360 Notebooks which assign | |
935 | * Cardbus to IRQ 11 even though it is actually wired to IRQ 10 | |
936 | */ | |
937 | static int __init fix_acer_tm360_irqrouting(struct dmi_system_id *d) | |
938 | { | |
939 | if (!acer_tm360_irqrouting) { | |
940 | acer_tm360_irqrouting = 1; | |
941 | printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident); | |
942 | } | |
943 | return 0; | |
944 | } | |
945 | ||
946 | static struct dmi_system_id __initdata pciirq_dmi_table[] = { | |
947 | { | |
948 | .callback = fix_broken_hp_bios_irq9, | |
949 | .ident = "HP Pavilion N5400 Series Laptop", | |
950 | .matches = { | |
951 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
952 | DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"), | |
953 | DMI_MATCH(DMI_PRODUCT_VERSION, "HP Pavilion Notebook Model GE"), | |
954 | DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"), | |
955 | }, | |
956 | }, | |
957 | { | |
958 | .callback = fix_acer_tm360_irqrouting, | |
959 | .ident = "Acer TravelMate 36x Laptop", | |
960 | .matches = { | |
961 | DMI_MATCH(DMI_SYS_VENDOR, "Acer"), | |
962 | DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"), | |
963 | }, | |
964 | }, | |
965 | { } | |
966 | }; | |
967 | ||
968 | static int __init pcibios_irq_init(void) | |
969 | { | |
970 | DBG("PCI: IRQ init\n"); | |
971 | ||
972 | if (pcibios_enable_irq || raw_pci_ops == NULL) | |
973 | return 0; | |
974 | ||
975 | dmi_check_system(pciirq_dmi_table); | |
976 | ||
977 | pirq_table = pirq_find_routing_table(); | |
978 | ||
979 | #ifdef CONFIG_PCI_BIOS | |
980 | if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) | |
981 | pirq_table = pcibios_get_irq_routing_table(); | |
982 | #endif | |
983 | if (pirq_table) { | |
984 | pirq_peer_trick(); | |
985 | pirq_find_router(&pirq_router); | |
986 | if (pirq_table->exclusive_irqs) { | |
987 | int i; | |
988 | for (i=0; i<16; i++) | |
989 | if (!(pirq_table->exclusive_irqs & (1 << i))) | |
990 | pirq_penalty[i] += 100; | |
991 | } | |
992 | /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */ | |
993 | if (io_apic_assign_pci_irqs) | |
994 | pirq_table = NULL; | |
995 | } | |
996 | ||
997 | pcibios_enable_irq = pirq_enable_irq; | |
998 | ||
999 | pcibios_fixup_irqs(); | |
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | subsys_initcall(pcibios_irq_init); | |
1004 | ||
1005 | ||
1006 | static void pirq_penalize_isa_irq(int irq) | |
1007 | { | |
1008 | /* | |
1009 | * If any ISAPnP device reports an IRQ in its list of possible | |
1010 | * IRQ's, we try to avoid assigning it to PCI devices. | |
1011 | */ | |
1012 | if (irq < 16) | |
1013 | pirq_penalty[irq] += 100; | |
1014 | } | |
1015 | ||
1016 | void pcibios_penalize_isa_irq(int irq) | |
1017 | { | |
1018 | #ifdef CONFIG_ACPI_PCI | |
1019 | if (!acpi_noirq) | |
1020 | acpi_penalize_isa_irq(irq); | |
1021 | else | |
1022 | #endif | |
1023 | pirq_penalize_isa_irq(irq); | |
1024 | } | |
1025 | ||
1026 | static int pirq_enable_irq(struct pci_dev *dev) | |
1027 | { | |
1028 | u8 pin; | |
1029 | extern int via_interrupt_line_quirk; | |
1030 | struct pci_dev *temp_dev; | |
1031 | ||
1032 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); | |
1033 | if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) { | |
1034 | char *msg = ""; | |
1035 | ||
1036 | pin--; /* interrupt pins are numbered starting from 1 */ | |
1037 | ||
1038 | if (io_apic_assign_pci_irqs) { | |
1039 | int irq; | |
1040 | ||
1041 | irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin); | |
1042 | /* | |
1043 | * Busses behind bridges are typically not listed in the MP-table. | |
1044 | * In this case we have to look up the IRQ based on the parent bus, | |
1045 | * parent slot, and pin number. The SMP code detects such bridged | |
1046 | * busses itself so we should get into this branch reliably. | |
1047 | */ | |
1048 | temp_dev = dev; | |
1049 | while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ | |
1050 | struct pci_dev * bridge = dev->bus->self; | |
1051 | ||
1052 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
1053 | irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, | |
1054 | PCI_SLOT(bridge->devfn), pin); | |
1055 | if (irq >= 0) | |
1056 | printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n", | |
1057 | pci_name(bridge), 'A' + pin, irq); | |
1058 | dev = bridge; | |
1059 | } | |
1060 | dev = temp_dev; | |
1061 | if (irq >= 0) { | |
1062 | #ifdef CONFIG_PCI_MSI | |
1063 | if (!platform_legacy_irq(irq)) | |
1064 | irq = IO_APIC_VECTOR(irq); | |
1065 | #endif | |
1066 | printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n", | |
1067 | pci_name(dev), 'A' + pin, irq); | |
1068 | dev->irq = irq; | |
1069 | return 0; | |
1070 | } else | |
1071 | msg = " Probably buggy MP table."; | |
1072 | } else if (pci_probe & PCI_BIOS_IRQ_SCAN) | |
1073 | msg = ""; | |
1074 | else | |
1075 | msg = " Please try using pci=biosirq."; | |
1076 | ||
1077 | /* With IDE legacy devices the IRQ lookup failure is not a problem.. */ | |
1078 | if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5)) | |
1079 | return 0; | |
1080 | ||
1081 | printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n", | |
1082 | 'A' + pin, pci_name(dev), msg); | |
1083 | } | |
1084 | /* VIA bridges use interrupt line for apic/pci steering across | |
1085 | the V-Link */ | |
1086 | else if (via_interrupt_line_quirk) | |
1087 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq & 15); | |
1088 | return 0; | |
1089 | } | |
1090 | ||
1091 | int pci_vector_resources(int last, int nr_released) | |
1092 | { | |
1093 | int count = nr_released; | |
1094 | ||
1095 | int next = last; | |
1096 | int offset = (last % 8); | |
1097 | ||
1098 | while (next < FIRST_SYSTEM_VECTOR) { | |
1099 | next += 8; | |
1100 | #ifdef CONFIG_X86_64 | |
1101 | if (next == IA32_SYSCALL_VECTOR) | |
1102 | continue; | |
1103 | #else | |
1104 | if (next == SYSCALL_VECTOR) | |
1105 | continue; | |
1106 | #endif | |
1107 | count++; | |
1108 | if (next >= FIRST_SYSTEM_VECTOR) { | |
1109 | if (offset%8) { | |
1110 | next = FIRST_DEVICE_VECTOR + offset; | |
1111 | offset++; | |
1112 | continue; | |
1113 | } | |
1114 | count--; | |
1115 | } | |
1116 | } | |
1117 | ||
1118 | return count; | |
1119 | } |