[deliverable/linux.git] / arch / ia64 / include / asm / pci.h

#ifndef _ASM_IA64_PCI_H
#define _ASM_IA64_PCI_H

#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/types.h>

#include <asm/io.h>
#include <asm/scatterlist.h>
#include <asm/hw_irq.h>

struct pci_vector_struct {
	__u16 segment;	/* PCI Segment number */
	__u16 bus;	/* PCI Bus number */
	__u32 pci_id;	/* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
	__u8 pin;	/* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
	__u32 irq;	/* IRQ assigned */
};

/*
 * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
 * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
 * loader.
 */
#define pcibios_assign_all_busses()     0

#define PCIBIOS_MIN_IO		0x1000
#define PCIBIOS_MIN_MEM		0x10000000

void pcibios_config_init(void);

struct pci_dev;

/*
 * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
 * correspondence between device bus addresses and CPU physical addresses.
 * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
 * bounce buffer handling code in the block and network device layers.
 * Platforms with separate bus address spaces _must_ turn this off and provide
 * a device DMA mapping implementation that takes care of the necessary
 * address translation.
 *
 * For now, the ia64 platforms which may have separate/multiple bus address
 * spaces all have I/O MMUs which support the merging of physically
 * discontiguous buffers, so we can use that as the sole factor to determine
 * the setting of PCI_DMA_BUS_IS_PHYS.
 */
extern unsigned long ia64_max_iommu_merge_mask;
#define PCI_DMA_BUS_IS_PHYS	(ia64_max_iommu_merge_mask == ~0UL)

static inline void
pcibios_penalize_isa_irq (int irq, int active)
{
	/* We don't do dynamic PCI IRQ allocation */
}

#include <asm-generic/pci-dma-compat.h>

#ifdef CONFIG_PCI
static inline void pci_dma_burst_advice(struct pci_dev *pdev,
					enum pci_dma_burst_strategy *strat,
					unsigned long *strategy_parameter)
{
	unsigned long cacheline_size;
	u8 byte;

	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
	if (byte == 0)
		cacheline_size = 1024;
	else
		cacheline_size = (int) byte * 4;

	*strat = PCI_DMA_BURST_MULTIPLE;
	*strategy_parameter = cacheline_size;
}
#endif

#define HAVE_PCI_MMAP
extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
				enum pci_mmap_state mmap_state, int write_combine);
#define HAVE_PCI_LEGACY
extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
				      struct vm_area_struct *vma,
				      enum pci_mmap_state mmap_state);

#define pci_get_legacy_mem platform_pci_get_legacy_mem
#define pci_legacy_read platform_pci_legacy_read
#define pci_legacy_write platform_pci_legacy_write

struct pci_window {
	struct resource resource;
	u64 offset;
};

struct pci_controller {
	void *acpi_handle;
	void *iommu;
	int segment;
	int node;		/* nearest node with memory or -1 for global allocation */

	unsigned int windows;
	struct pci_window *window;

	void *platform_data;
};

#define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
#define pci_domain_nr(busdev)    (PCI_CONTROLLER(busdev)->segment)

extern struct pci_ops pci_root_ops;

static inline int pci_proc_domain(struct pci_bus *bus)
{
	return (pci_domain_nr(bus) != 0);
}

extern void pcibios_resource_to_bus(struct pci_dev *dev,
		struct pci_bus_region *region, struct resource *res);

extern void pcibios_bus_to_resource(struct pci_dev *dev,
		struct resource *res, struct pci_bus_region *region);

static inline struct resource *
pcibios_select_root(struct pci_dev *pdev, struct resource *res)
{
	struct resource *root = NULL;

	if (res->flags & IORESOURCE_IO)
		root = &ioport_resource;
	if (res->flags & IORESOURCE_MEM)
		root = &iomem_resource;

	return root;
}

#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
	return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
}

#ifdef CONFIG_INTEL_IOMMU
extern void pci_iommu_alloc(void);
#endif
#endif /* _ASM_IA64_PCI_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _ASM_IA64_PCI_H
	2	#define _ASM_IA64_PCI_H
	3
	4	#include <linux/mm.h>
	5	#include <linux/slab.h>
	6	#include <linux/spinlock.h>
	7	#include <linux/string.h>
	8	#include <linux/types.h>
	9
	10	#include <asm/io.h>
	11	#include <asm/scatterlist.h>
8621235b	12	#include <asm/hw_irq.h>
1da177e4	13
c140d879 DH	14	struct pci_vector_struct {
	15	__u16 segment; /* PCI Segment number */
	16	__u16 bus; /* PCI Bus number */
	17	__u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
	18	__u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
	19	__u32 irq; /* IRQ assigned */
	20	};
	21
1da177e4 LT	22	/*
	23	* Can be used to override the logic in pci_scan_bus for skipping already-configured bus
	24	* numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
	25	* loader.
	26	*/
	27	#define pcibios_assign_all_busses() 0
1da177e4 LT	28
	29	#define PCIBIOS_MIN_IO 0x1000
	30	#define PCIBIOS_MIN_MEM 0x10000000
	31
	32	void pcibios_config_init(void);
	33
	34	struct pci_dev;
	35
	36	/*
3efe2d84 MW	37	* PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
	38	* correspondence between device bus addresses and CPU physical addresses.
	39	* Platforms with a hardware I/O MMU _must_ turn this off to suppress the
	40	* bounce buffer handling code in the block and network device layers.
	41	* Platforms with separate bus address spaces _must_ turn this off and provide
	42	* a device DMA mapping implementation that takes care of the necessary
1da177e4 LT	43	* address translation.
1da177e4 LT	44	*
3efe2d84 MW	45	* For now, the ia64 platforms which may have separate/multiple bus address
	46	* spaces all have I/O MMUs which support the merging of physically
	47	* discontiguous buffers, so we can use that as the sole factor to determine
	48	* the setting of PCI_DMA_BUS_IS_PHYS.
1da177e4 LT	49	*/
	50	extern unsigned long ia64_max_iommu_merge_mask;
	51	#define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL)
	52
1da177e4	53	static inline void
c9c3e457	54	pcibios_penalize_isa_irq (int irq, int active)
1da177e4 LT	55	{
	56	/* We don't do dynamic PCI IRQ allocation */
	57	}
	58
1da177e4 LT	59	#include <asm-generic/pci-dma-compat.h>
1da177e4 LT	60
bb4a61b6	61	#ifdef CONFIG_PCI
e24c2d96 DM	62	static inline void pci_dma_burst_advice(struct pci_dev *pdev,
	63	enum pci_dma_burst_strategy *strat,
	64	unsigned long *strategy_parameter)
	65	{
	66	unsigned long cacheline_size;
	67	u8 byte;
	68
	69	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
	70	if (byte == 0)
	71	cacheline_size = 1024;
	72	else
	73	cacheline_size = (int) byte * 4;
	74
	75	*strat = PCI_DMA_BURST_MULTIPLE;
	76	*strategy_parameter = cacheline_size;
	77	}
bb4a61b6	78	#endif
e24c2d96	79
1da177e4 LT	80	#define HAVE_PCI_MMAP
	81	extern int pci_mmap_page_range (struct pci_dev dev, struct vm_area_struct vma,
	82	enum pci_mmap_state mmap_state, int write_combine);
	83	#define HAVE_PCI_LEGACY
	84	extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
f19aeb1f BH	85	struct vm_area_struct *vma,
f19aeb1f BH	86	enum pci_mmap_state mmap_state);
1da177e4 LT	87
	88	#define pci_get_legacy_mem platform_pci_get_legacy_mem
	89	#define pci_legacy_read platform_pci_legacy_read
	90	#define pci_legacy_write platform_pci_legacy_write
	91
	92	struct pci_window {
	93	struct resource resource;
	94	u64 offset;
	95	};
	96
	97	struct pci_controller {
	98	void *acpi_handle;
	99	void *iommu;
	100	int segment;
514604c6	101	int node; /* nearest node with memory or -1 for global allocation */
1da177e4 LT	102
	103	unsigned int windows;
	104	struct pci_window *window;
	105
	106	void *platform_data;
	107	};
	108
	109	#define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
	110	#define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment)
	111
	112	extern struct pci_ops pci_root_ops;
	113
	114	static inline int pci_proc_domain(struct pci_bus *bus)
	115	{
	116	return (pci_domain_nr(bus) != 0);
	117	}
	118
1da177e4 LT	119	extern void pcibios_resource_to_bus(struct pci_dev *dev,
	120	struct pci_bus_region region, struct resource res);
	121
	122	extern void pcibios_bus_to_resource(struct pci_dev *dev,
	123	struct resource res, struct pci_bus_region region);
	124
a7db5040 AC	125	static inline struct resource *
	126	pcibios_select_root(struct pci_dev pdev, struct resource res)
	127	{
	128	struct resource *root = NULL;
	129
	130	if (res->flags & IORESOURCE_IO)
	131	root = &ioport_resource;
	132	if (res->flags & IORESOURCE_MEM)
	133	root = &iomem_resource;
	134
	135	return root;
	136	}
1da177e4	137
677c0a78 BZ	138	#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
	139	static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
	140	{
8621235b	141	return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
677c0a78 BZ	142	}
677c0a78 BZ	143
d3f13810	144	#ifdef CONFIG_INTEL_IOMMU
62fdd767 FY	145	extern void pci_iommu_alloc(void);
62fdd767 FY	146	#endif
1da177e4	147	#endif /* _ASM_IA64_PCI_H */