Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * I/O SAPIC support. | |
3 | * | |
4 | * Copyright (C) 1999 Intel Corp. | |
5 | * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> | |
6 | * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com> | |
7 | * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co. | |
8 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
9 | * Copyright (C) 1999 VA Linux Systems | |
10 | * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com> | |
11 | * | |
46cba3dc ST |
12 | * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O |
13 | * APIC code. In particular, we now have separate | |
14 | * handlers for edge and level triggered | |
15 | * interrupts. | |
16 | * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector | |
17 | * allocation PCI to vector mapping, shared PCI | |
18 | * interrupts. | |
19 | * 00/10/27 D. Mosberger Document things a bit more to make them more | |
20 | * understandable. Clean up much of the old | |
21 | * IOSAPIC cruft. | |
22 | * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts | |
23 | * and fixes for ACPI S5(SoftOff) support. | |
1da177e4 | 24 | * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT |
46cba3dc ST |
25 | * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt |
26 | * vectors in iosapic_set_affinity(), | |
27 | * initializations for /proc/irq/#/smp_affinity | |
1da177e4 LT |
28 | * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing. |
29 | * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq | |
46cba3dc ST |
30 | * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to |
31 | * IOSAPIC mapping error | |
1da177e4 | 32 | * 02/07/29 T. Kochi Allocate interrupt vectors dynamically |
46cba3dc ST |
33 | * 02/08/04 T. Kochi Cleaned up terminology (irq, global system |
34 | * interrupt, vector, etc.) | |
35 | * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's | |
36 | * pci_irq code. | |
1da177e4 | 37 | * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC. |
46cba3dc ST |
38 | * Remove iosapic_address & gsi_base from |
39 | * external interfaces. Rationalize | |
40 | * __init/__devinit attributes. | |
1da177e4 | 41 | * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004 |
46cba3dc ST |
42 | * Updated to work with irq migration necessary |
43 | * for CPU Hotplug | |
1da177e4 LT |
44 | */ |
45 | /* | |
46cba3dc ST |
46 | * Here is what the interrupt logic between a PCI device and the kernel looks |
47 | * like: | |
1da177e4 | 48 | * |
46cba3dc ST |
49 | * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, |
50 | * INTD). The device is uniquely identified by its bus-, and slot-number | |
51 | * (the function number does not matter here because all functions share | |
52 | * the same interrupt lines). | |
1da177e4 | 53 | * |
46cba3dc ST |
54 | * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC |
55 | * controller. Multiple interrupt lines may have to share the same | |
56 | * IOSAPIC pin (if they're level triggered and use the same polarity). | |
57 | * Each interrupt line has a unique Global System Interrupt (GSI) number | |
58 | * which can be calculated as the sum of the controller's base GSI number | |
59 | * and the IOSAPIC pin number to which the line connects. | |
1da177e4 | 60 | * |
46cba3dc ST |
61 | * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the |
62 | * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then | |
63 | * sent to the CPU. | |
1da177e4 | 64 | * |
46cba3dc ST |
65 | * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is |
66 | * used as architecture-independent interrupt handling mechanism in Linux. | |
67 | * As an IRQ is a number, we have to have | |
68 | * IA-64 interrupt vector number <-> IRQ number mapping. On smaller | |
69 | * systems, we use one-to-one mapping between IA-64 vector and IRQ. A | |
70 | * platform can implement platform_irq_to_vector(irq) and | |
1da177e4 | 71 | * platform_local_vector_to_irq(vector) APIs to differentiate the mapping. |
7f30491c | 72 | * Please see also arch/ia64/include/asm/hw_irq.h for those APIs. |
1da177e4 LT |
73 | * |
74 | * To sum up, there are three levels of mappings involved: | |
75 | * | |
76 | * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ | |
77 | * | |
46cba3dc ST |
78 | * Note: The term "IRQ" is loosely used everywhere in Linux kernel to |
79 | * describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ | |
80 | * (isa_irq) is the only exception in this source code. | |
1da177e4 | 81 | */ |
1da177e4 LT |
82 | |
83 | #include <linux/acpi.h> | |
84 | #include <linux/init.h> | |
85 | #include <linux/irq.h> | |
86 | #include <linux/kernel.h> | |
87 | #include <linux/list.h> | |
88 | #include <linux/pci.h> | |
5a0e3ad6 | 89 | #include <linux/slab.h> |
1da177e4 | 90 | #include <linux/smp.h> |
1da177e4 | 91 | #include <linux/string.h> |
24eeb568 | 92 | #include <linux/bootmem.h> |
1da177e4 LT |
93 | |
94 | #include <asm/delay.h> | |
95 | #include <asm/hw_irq.h> | |
96 | #include <asm/io.h> | |
97 | #include <asm/iosapic.h> | |
98 | #include <asm/machvec.h> | |
99 | #include <asm/processor.h> | |
100 | #include <asm/ptrace.h> | |
101 | #include <asm/system.h> | |
102 | ||
1da177e4 LT |
103 | #undef DEBUG_INTERRUPT_ROUTING |
104 | ||
105 | #ifdef DEBUG_INTERRUPT_ROUTING | |
106 | #define DBG(fmt...) printk(fmt) | |
107 | #else | |
108 | #define DBG(fmt...) | |
109 | #endif | |
110 | ||
111 | static DEFINE_SPINLOCK(iosapic_lock); | |
112 | ||
46cba3dc ST |
113 | /* |
114 | * These tables map IA-64 vectors to the IOSAPIC pin that generates this | |
115 | * vector. | |
116 | */ | |
e1b30a39 YI |
117 | |
118 | #define NO_REF_RTE 0 | |
119 | ||
c5e3f9e5 YI |
120 | static struct iosapic { |
121 | char __iomem *addr; /* base address of IOSAPIC */ | |
122 | unsigned int gsi_base; /* GSI base */ | |
123 | unsigned short num_rte; /* # of RTEs on this IOSAPIC */ | |
124 | int rtes_inuse; /* # of RTEs in use on this IOSAPIC */ | |
125 | #ifdef CONFIG_NUMA | |
126 | unsigned short node; /* numa node association via pxm */ | |
127 | #endif | |
c1726d6f | 128 | spinlock_t lock; /* lock for indirect reg access */ |
c5e3f9e5 | 129 | } iosapic_lists[NR_IOSAPICS]; |
1da177e4 | 130 | |
24eeb568 | 131 | struct iosapic_rte_info { |
c5e3f9e5 | 132 | struct list_head rte_list; /* RTEs sharing the same vector */ |
24eeb568 KK |
133 | char rte_index; /* IOSAPIC RTE index */ |
134 | int refcnt; /* reference counter */ | |
c5e3f9e5 | 135 | struct iosapic *iosapic; |
24eeb568 KK |
136 | } ____cacheline_aligned; |
137 | ||
138 | static struct iosapic_intr_info { | |
46cba3dc ST |
139 | struct list_head rtes; /* RTEs using this vector (empty => |
140 | * not an IOSAPIC interrupt) */ | |
c4c376f7 | 141 | int count; /* # of registered RTEs */ |
46cba3dc ST |
142 | u32 low32; /* current value of low word of |
143 | * Redirection table entry */ | |
24eeb568 | 144 | unsigned int dest; /* destination CPU physical ID */ |
1da177e4 | 145 | unsigned char dmode : 3; /* delivery mode (see iosapic.h) */ |
46cba3dc ST |
146 | unsigned char polarity: 1; /* interrupt polarity |
147 | * (see iosapic.h) */ | |
1da177e4 | 148 | unsigned char trigger : 1; /* trigger mode (see iosapic.h) */ |
4bbdec7a | 149 | } iosapic_intr_info[NR_IRQS]; |
1da177e4 | 150 | |
0e888adc | 151 | static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */ |
1da177e4 | 152 | |
c1726d6f YI |
153 | static inline void |
154 | iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val) | |
155 | { | |
156 | unsigned long flags; | |
157 | ||
158 | spin_lock_irqsave(&iosapic->lock, flags); | |
159 | __iosapic_write(iosapic->addr, reg, val); | |
160 | spin_unlock_irqrestore(&iosapic->lock, flags); | |
161 | } | |
162 | ||
1da177e4 LT |
163 | /* |
164 | * Find an IOSAPIC associated with a GSI | |
165 | */ | |
166 | static inline int | |
167 | find_iosapic (unsigned int gsi) | |
168 | { | |
169 | int i; | |
170 | ||
0e888adc | 171 | for (i = 0; i < NR_IOSAPICS; i++) { |
46cba3dc ST |
172 | if ((unsigned) (gsi - iosapic_lists[i].gsi_base) < |
173 | iosapic_lists[i].num_rte) | |
1da177e4 LT |
174 | return i; |
175 | } | |
176 | ||
177 | return -1; | |
178 | } | |
179 | ||
4bbdec7a | 180 | static inline int __gsi_to_irq(unsigned int gsi) |
1da177e4 | 181 | { |
4bbdec7a | 182 | int irq; |
1da177e4 | 183 | struct iosapic_intr_info *info; |
24eeb568 | 184 | struct iosapic_rte_info *rte; |
1da177e4 | 185 | |
4bbdec7a YI |
186 | for (irq = 0; irq < NR_IRQS; irq++) { |
187 | info = &iosapic_intr_info[irq]; | |
24eeb568 | 188 | list_for_each_entry(rte, &info->rtes, rte_list) |
c5e3f9e5 | 189 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) |
4bbdec7a YI |
190 | return irq; |
191 | } | |
1da177e4 LT |
192 | return -1; |
193 | } | |
194 | ||
1da177e4 LT |
195 | int |
196 | gsi_to_irq (unsigned int gsi) | |
197 | { | |
24eeb568 KK |
198 | unsigned long flags; |
199 | int irq; | |
4bbdec7a | 200 | |
24eeb568 | 201 | spin_lock_irqsave(&iosapic_lock, flags); |
4bbdec7a | 202 | irq = __gsi_to_irq(gsi); |
24eeb568 | 203 | spin_unlock_irqrestore(&iosapic_lock, flags); |
24eeb568 KK |
204 | return irq; |
205 | } | |
206 | ||
4bbdec7a | 207 | static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi) |
24eeb568 KK |
208 | { |
209 | struct iosapic_rte_info *rte; | |
210 | ||
4bbdec7a | 211 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) |
c5e3f9e5 | 212 | if (rte->iosapic->gsi_base + rte->rte_index == gsi) |
24eeb568 KK |
213 | return rte; |
214 | return NULL; | |
1da177e4 LT |
215 | } |
216 | ||
217 | static void | |
4bbdec7a | 218 | set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask) |
1da177e4 LT |
219 | { |
220 | unsigned long pol, trigger, dmode; | |
221 | u32 low32, high32; | |
1da177e4 LT |
222 | int rte_index; |
223 | char redir; | |
24eeb568 | 224 | struct iosapic_rte_info *rte; |
4bbdec7a | 225 | ia64_vector vector = irq_to_vector(irq); |
1da177e4 LT |
226 | |
227 | DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest); | |
228 | ||
4bbdec7a | 229 | rte = find_rte(irq, gsi); |
24eeb568 | 230 | if (!rte) |
1da177e4 LT |
231 | return; /* not an IOSAPIC interrupt */ |
232 | ||
24eeb568 | 233 | rte_index = rte->rte_index; |
4bbdec7a YI |
234 | pol = iosapic_intr_info[irq].polarity; |
235 | trigger = iosapic_intr_info[irq].trigger; | |
236 | dmode = iosapic_intr_info[irq].dmode; | |
1da177e4 LT |
237 | |
238 | redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0; | |
239 | ||
240 | #ifdef CONFIG_SMP | |
4bbdec7a | 241 | set_irq_affinity_info(irq, (int)(dest & 0xffff), redir); |
1da177e4 LT |
242 | #endif |
243 | ||
244 | low32 = ((pol << IOSAPIC_POLARITY_SHIFT) | | |
245 | (trigger << IOSAPIC_TRIGGER_SHIFT) | | |
246 | (dmode << IOSAPIC_DELIVERY_SHIFT) | | |
247 | ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) | | |
248 | vector); | |
249 | ||
250 | /* dest contains both id and eid */ | |
251 | high32 = (dest << IOSAPIC_DEST_SHIFT); | |
252 | ||
c1726d6f YI |
253 | iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32); |
254 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); | |
4bbdec7a YI |
255 | iosapic_intr_info[irq].low32 = low32; |
256 | iosapic_intr_info[irq].dest = dest; | |
1da177e4 LT |
257 | } |
258 | ||
259 | static void | |
46cba3dc | 260 | nop (unsigned int irq) |
1da177e4 LT |
261 | { |
262 | /* do nothing... */ | |
263 | } | |
264 | ||
a7956113 ZN |
265 | |
266 | #ifdef CONFIG_KEXEC | |
267 | void | |
268 | kexec_disable_iosapic(void) | |
269 | { | |
270 | struct iosapic_intr_info *info; | |
271 | struct iosapic_rte_info *rte; | |
4bbdec7a YI |
272 | ia64_vector vec; |
273 | int irq; | |
274 | ||
275 | for (irq = 0; irq < NR_IRQS; irq++) { | |
276 | info = &iosapic_intr_info[irq]; | |
277 | vec = irq_to_vector(irq); | |
a7956113 ZN |
278 | list_for_each_entry(rte, &info->rtes, |
279 | rte_list) { | |
c1726d6f | 280 | iosapic_write(rte->iosapic, |
a7956113 ZN |
281 | IOSAPIC_RTE_LOW(rte->rte_index), |
282 | IOSAPIC_MASK|vec); | |
c5e3f9e5 | 283 | iosapic_eoi(rte->iosapic->addr, vec); |
a7956113 ZN |
284 | } |
285 | } | |
286 | } | |
287 | #endif | |
288 | ||
1da177e4 LT |
289 | static void |
290 | mask_irq (unsigned int irq) | |
291 | { | |
1da177e4 LT |
292 | u32 low32; |
293 | int rte_index; | |
24eeb568 | 294 | struct iosapic_rte_info *rte; |
1da177e4 | 295 | |
c4c376f7 | 296 | if (!iosapic_intr_info[irq].count) |
1da177e4 LT |
297 | return; /* not an IOSAPIC interrupt! */ |
298 | ||
e3a8f7b8 | 299 | /* set only the mask bit */ |
4bbdec7a YI |
300 | low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK; |
301 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
e3a8f7b8 | 302 | rte_index = rte->rte_index; |
c1726d6f | 303 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); |
1da177e4 | 304 | } |
1da177e4 LT |
305 | } |
306 | ||
307 | static void | |
308 | unmask_irq (unsigned int irq) | |
309 | { | |
1da177e4 LT |
310 | u32 low32; |
311 | int rte_index; | |
24eeb568 | 312 | struct iosapic_rte_info *rte; |
1da177e4 | 313 | |
c4c376f7 | 314 | if (!iosapic_intr_info[irq].count) |
1da177e4 LT |
315 | return; /* not an IOSAPIC interrupt! */ |
316 | ||
4bbdec7a YI |
317 | low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK; |
318 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
e3a8f7b8 | 319 | rte_index = rte->rte_index; |
c1726d6f | 320 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32); |
1da177e4 | 321 | } |
1da177e4 LT |
322 | } |
323 | ||
324 | ||
d5dedd45 | 325 | static int |
0de26520 | 326 | iosapic_set_affinity(unsigned int irq, const struct cpumask *mask) |
1da177e4 LT |
327 | { |
328 | #ifdef CONFIG_SMP | |
1da177e4 | 329 | u32 high32, low32; |
0de26520 | 330 | int cpu, dest, rte_index; |
1da177e4 | 331 | int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0; |
24eeb568 | 332 | struct iosapic_rte_info *rte; |
c1726d6f | 333 | struct iosapic *iosapic; |
1da177e4 LT |
334 | |
335 | irq &= (~IA64_IRQ_REDIRECTED); | |
1da177e4 | 336 | |
0de26520 RR |
337 | cpu = cpumask_first_and(cpu_online_mask, mask); |
338 | if (cpu >= nr_cpu_ids) | |
d5dedd45 | 339 | return -1; |
1da177e4 | 340 | |
0de26520 | 341 | if (irq_prepare_move(irq, cpu)) |
d5dedd45 | 342 | return -1; |
cd378f18 | 343 | |
0de26520 | 344 | dest = cpu_physical_id(cpu); |
1da177e4 | 345 | |
c4c376f7 | 346 | if (!iosapic_intr_info[irq].count) |
d5dedd45 | 347 | return -1; /* not an IOSAPIC interrupt */ |
1da177e4 LT |
348 | |
349 | set_irq_affinity_info(irq, dest, redir); | |
350 | ||
351 | /* dest contains both id and eid */ | |
352 | high32 = dest << IOSAPIC_DEST_SHIFT; | |
353 | ||
4bbdec7a | 354 | low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT); |
e3a8f7b8 YI |
355 | if (redir) |
356 | /* change delivery mode to lowest priority */ | |
357 | low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT); | |
358 | else | |
359 | /* change delivery mode to fixed */ | |
360 | low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT); | |
cd378f18 YI |
361 | low32 &= IOSAPIC_VECTOR_MASK; |
362 | low32 |= irq_to_vector(irq); | |
e3a8f7b8 | 363 | |
4bbdec7a YI |
364 | iosapic_intr_info[irq].low32 = low32; |
365 | iosapic_intr_info[irq].dest = dest; | |
366 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) { | |
c1726d6f | 367 | iosapic = rte->iosapic; |
e3a8f7b8 | 368 | rte_index = rte->rte_index; |
c1726d6f YI |
369 | iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32); |
370 | iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32); | |
1da177e4 | 371 | } |
d5dedd45 | 372 | |
1da177e4 | 373 | #endif |
d5dedd45 | 374 | return 0; |
1da177e4 LT |
375 | } |
376 | ||
377 | /* | |
378 | * Handlers for level-triggered interrupts. | |
379 | */ | |
380 | ||
381 | static unsigned int | |
382 | iosapic_startup_level_irq (unsigned int irq) | |
383 | { | |
384 | unmask_irq(irq); | |
385 | return 0; | |
386 | } | |
387 | ||
388 | static void | |
5d4bff94 | 389 | iosapic_unmask_level_irq (unsigned int irq) |
1da177e4 LT |
390 | { |
391 | ia64_vector vec = irq_to_vector(irq); | |
24eeb568 | 392 | struct iosapic_rte_info *rte; |
cd378f18 YI |
393 | int do_unmask_irq = 0; |
394 | ||
a6cd6322 | 395 | irq_complete_move(irq); |
cd378f18 YI |
396 | if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) { |
397 | do_unmask_irq = 1; | |
398 | mask_irq(irq); | |
5d4bff94 TL |
399 | } else |
400 | unmask_irq(irq); | |
1da177e4 | 401 | |
4bbdec7a | 402 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) |
c5e3f9e5 | 403 | iosapic_eoi(rte->iosapic->addr, vec); |
cd378f18 YI |
404 | |
405 | if (unlikely(do_unmask_irq)) { | |
406 | move_masked_irq(irq); | |
407 | unmask_irq(irq); | |
408 | } | |
1da177e4 LT |
409 | } |
410 | ||
411 | #define iosapic_shutdown_level_irq mask_irq | |
412 | #define iosapic_enable_level_irq unmask_irq | |
413 | #define iosapic_disable_level_irq mask_irq | |
414 | #define iosapic_ack_level_irq nop | |
415 | ||
9e004ebd | 416 | static struct irq_chip irq_type_iosapic_level = { |
06344db3 | 417 | .name = "IO-SAPIC-level", |
1da177e4 LT |
418 | .startup = iosapic_startup_level_irq, |
419 | .shutdown = iosapic_shutdown_level_irq, | |
420 | .enable = iosapic_enable_level_irq, | |
421 | .disable = iosapic_disable_level_irq, | |
422 | .ack = iosapic_ack_level_irq, | |
e253eb0c | 423 | .mask = mask_irq, |
5d4bff94 | 424 | .unmask = iosapic_unmask_level_irq, |
1da177e4 LT |
425 | .set_affinity = iosapic_set_affinity |
426 | }; | |
427 | ||
428 | /* | |
429 | * Handlers for edge-triggered interrupts. | |
430 | */ | |
431 | ||
432 | static unsigned int | |
433 | iosapic_startup_edge_irq (unsigned int irq) | |
434 | { | |
435 | unmask_irq(irq); | |
436 | /* | |
437 | * IOSAPIC simply drops interrupts pended while the | |
438 | * corresponding pin was masked, so we can't know if an | |
439 | * interrupt is pending already. Let's hope not... | |
440 | */ | |
441 | return 0; | |
442 | } | |
443 | ||
444 | static void | |
445 | iosapic_ack_edge_irq (unsigned int irq) | |
446 | { | |
86bc3dfe | 447 | struct irq_desc *idesc = irq_desc + irq; |
1da177e4 | 448 | |
a6cd6322 | 449 | irq_complete_move(irq); |
41503def | 450 | move_native_irq(irq); |
1da177e4 LT |
451 | /* |
452 | * Once we have recorded IRQ_PENDING already, we can mask the | |
453 | * interrupt for real. This prevents IRQ storms from unhandled | |
454 | * devices. | |
455 | */ | |
46cba3dc ST |
456 | if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == |
457 | (IRQ_PENDING|IRQ_DISABLED)) | |
1da177e4 LT |
458 | mask_irq(irq); |
459 | } | |
460 | ||
461 | #define iosapic_enable_edge_irq unmask_irq | |
462 | #define iosapic_disable_edge_irq nop | |
463 | #define iosapic_end_edge_irq nop | |
464 | ||
9e004ebd | 465 | static struct irq_chip irq_type_iosapic_edge = { |
06344db3 | 466 | .name = "IO-SAPIC-edge", |
1da177e4 LT |
467 | .startup = iosapic_startup_edge_irq, |
468 | .shutdown = iosapic_disable_edge_irq, | |
469 | .enable = iosapic_enable_edge_irq, | |
470 | .disable = iosapic_disable_edge_irq, | |
471 | .ack = iosapic_ack_edge_irq, | |
472 | .end = iosapic_end_edge_irq, | |
e253eb0c KH |
473 | .mask = mask_irq, |
474 | .unmask = unmask_irq, | |
1da177e4 LT |
475 | .set_affinity = iosapic_set_affinity |
476 | }; | |
477 | ||
9e004ebd | 478 | static unsigned int |
1da177e4 LT |
479 | iosapic_version (char __iomem *addr) |
480 | { | |
481 | /* | |
482 | * IOSAPIC Version Register return 32 bit structure like: | |
483 | * { | |
484 | * unsigned int version : 8; | |
485 | * unsigned int reserved1 : 8; | |
486 | * unsigned int max_redir : 8; | |
487 | * unsigned int reserved2 : 8; | |
488 | * } | |
489 | */ | |
c1726d6f | 490 | return __iosapic_read(addr, IOSAPIC_VERSION); |
1da177e4 LT |
491 | } |
492 | ||
4bbdec7a | 493 | static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol) |
24eeb568 | 494 | { |
4bbdec7a | 495 | int i, irq = -ENOSPC, min_count = -1; |
24eeb568 KK |
496 | struct iosapic_intr_info *info; |
497 | ||
498 | /* | |
499 | * shared vectors for edge-triggered interrupts are not | |
500 | * supported yet | |
501 | */ | |
502 | if (trigger == IOSAPIC_EDGE) | |
40598cbe | 503 | return -EINVAL; |
24eeb568 | 504 | |
5b592397 | 505 | for (i = 0; i < NR_IRQS; i++) { |
24eeb568 KK |
506 | info = &iosapic_intr_info[i]; |
507 | if (info->trigger == trigger && info->polarity == pol && | |
f8c087f3 YI |
508 | (info->dmode == IOSAPIC_FIXED || |
509 | info->dmode == IOSAPIC_LOWEST_PRIORITY) && | |
510 | can_request_irq(i, IRQF_SHARED)) { | |
24eeb568 | 511 | if (min_count == -1 || info->count < min_count) { |
4bbdec7a | 512 | irq = i; |
24eeb568 KK |
513 | min_count = info->count; |
514 | } | |
515 | } | |
516 | } | |
4bbdec7a | 517 | return irq; |
24eeb568 KK |
518 | } |
519 | ||
1da177e4 LT |
520 | /* |
521 | * if the given vector is already owned by other, | |
522 | * assign a new vector for the other and make the vector available | |
523 | */ | |
524 | static void __init | |
4bbdec7a | 525 | iosapic_reassign_vector (int irq) |
1da177e4 | 526 | { |
4bbdec7a | 527 | int new_irq; |
1da177e4 | 528 | |
c4c376f7 | 529 | if (iosapic_intr_info[irq].count) { |
4bbdec7a YI |
530 | new_irq = create_irq(); |
531 | if (new_irq < 0) | |
d4ed8084 | 532 | panic("%s: out of interrupt vectors!\n", __func__); |
46cba3dc | 533 | printk(KERN_INFO "Reassigning vector %d to %d\n", |
4bbdec7a YI |
534 | irq_to_vector(irq), irq_to_vector(new_irq)); |
535 | memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq], | |
1da177e4 | 536 | sizeof(struct iosapic_intr_info)); |
4bbdec7a YI |
537 | INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes); |
538 | list_move(iosapic_intr_info[irq].rtes.next, | |
539 | &iosapic_intr_info[new_irq].rtes); | |
540 | memset(&iosapic_intr_info[irq], 0, | |
46cba3dc | 541 | sizeof(struct iosapic_intr_info)); |
4bbdec7a YI |
542 | iosapic_intr_info[irq].low32 = IOSAPIC_MASK; |
543 | INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes); | |
1da177e4 LT |
544 | } |
545 | } | |
546 | ||
4bbdec7a | 547 | static inline int irq_is_shared (int irq) |
24eeb568 | 548 | { |
4bbdec7a | 549 | return (iosapic_intr_info[irq].count > 1); |
24eeb568 KK |
550 | } |
551 | ||
33b39e84 IY |
552 | struct irq_chip* |
553 | ia64_native_iosapic_get_irq_chip(unsigned long trigger) | |
554 | { | |
555 | if (trigger == IOSAPIC_EDGE) | |
556 | return &irq_type_iosapic_edge; | |
557 | else | |
558 | return &irq_type_iosapic_level; | |
559 | } | |
560 | ||
14454a1b | 561 | static int |
4bbdec7a | 562 | register_intr (unsigned int gsi, int irq, unsigned char delivery, |
1da177e4 LT |
563 | unsigned long polarity, unsigned long trigger) |
564 | { | |
86bc3dfe | 565 | struct irq_desc *idesc; |
fb824f48 | 566 | struct irq_chip *irq_type; |
1da177e4 | 567 | int index; |
24eeb568 | 568 | struct iosapic_rte_info *rte; |
1da177e4 LT |
569 | |
570 | index = find_iosapic(gsi); | |
571 | if (index < 0) { | |
46cba3dc | 572 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", |
d4ed8084 | 573 | __func__, gsi); |
14454a1b | 574 | return -ENODEV; |
1da177e4 LT |
575 | } |
576 | ||
4bbdec7a | 577 | rte = find_rte(irq, gsi); |
24eeb568 | 578 | if (!rte) { |
4de0a759 | 579 | rte = kzalloc(sizeof (*rte), GFP_ATOMIC); |
24eeb568 | 580 | if (!rte) { |
46cba3dc | 581 | printk(KERN_WARNING "%s: cannot allocate memory\n", |
d4ed8084 | 582 | __func__); |
14454a1b | 583 | return -ENOMEM; |
24eeb568 KK |
584 | } |
585 | ||
c5e3f9e5 YI |
586 | rte->iosapic = &iosapic_lists[index]; |
587 | rte->rte_index = gsi - rte->iosapic->gsi_base; | |
24eeb568 | 588 | rte->refcnt++; |
4bbdec7a YI |
589 | list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes); |
590 | iosapic_intr_info[irq].count++; | |
0e888adc | 591 | iosapic_lists[index].rtes_inuse++; |
24eeb568 | 592 | } |
e1b30a39 | 593 | else if (rte->refcnt == NO_REF_RTE) { |
4bbdec7a | 594 | struct iosapic_intr_info *info = &iosapic_intr_info[irq]; |
e1b30a39 YI |
595 | if (info->count > 0 && |
596 | (info->trigger != trigger || info->polarity != polarity)){ | |
46cba3dc ST |
597 | printk (KERN_WARNING |
598 | "%s: cannot override the interrupt\n", | |
d4ed8084 | 599 | __func__); |
14454a1b | 600 | return -EINVAL; |
24eeb568 | 601 | } |
e1b30a39 YI |
602 | rte->refcnt++; |
603 | iosapic_intr_info[irq].count++; | |
604 | iosapic_lists[index].rtes_inuse++; | |
24eeb568 KK |
605 | } |
606 | ||
4bbdec7a YI |
607 | iosapic_intr_info[irq].polarity = polarity; |
608 | iosapic_intr_info[irq].dmode = delivery; | |
609 | iosapic_intr_info[irq].trigger = trigger; | |
1da177e4 | 610 | |
33b39e84 | 611 | irq_type = iosapic_get_irq_chip(trigger); |
1da177e4 | 612 | |
4bbdec7a | 613 | idesc = irq_desc + irq; |
33b39e84 | 614 | if (irq_type != NULL && idesc->chip != irq_type) { |
8a7c3cd3 | 615 | if (idesc->chip != &no_irq_chip) |
46cba3dc ST |
616 | printk(KERN_WARNING |
617 | "%s: changing vector %d from %s to %s\n", | |
d4ed8084 | 618 | __func__, irq_to_vector(irq), |
351a5839 | 619 | idesc->chip->name, irq_type->name); |
d1bef4ed | 620 | idesc->chip = irq_type; |
1da177e4 | 621 | } |
5d4bff94 TL |
622 | if (trigger == IOSAPIC_EDGE) |
623 | __set_irq_handler_unlocked(irq, handle_edge_irq); | |
624 | else | |
625 | __set_irq_handler_unlocked(irq, handle_level_irq); | |
14454a1b | 626 | return 0; |
1da177e4 LT |
627 | } |
628 | ||
629 | static unsigned int | |
4bbdec7a | 630 | get_target_cpu (unsigned int gsi, int irq) |
1da177e4 LT |
631 | { |
632 | #ifdef CONFIG_SMP | |
633 | static int cpu = -1; | |
ff741906 | 634 | extern int cpe_vector; |
4994be1b | 635 | cpumask_t domain = irq_to_domain(irq); |
1da177e4 | 636 | |
24eeb568 KK |
637 | /* |
638 | * In case of vector shared by multiple RTEs, all RTEs that | |
639 | * share the vector need to use the same destination CPU. | |
640 | */ | |
c4c376f7 | 641 | if (iosapic_intr_info[irq].count) |
4bbdec7a | 642 | return iosapic_intr_info[irq].dest; |
24eeb568 | 643 | |
1da177e4 LT |
644 | /* |
645 | * If the platform supports redirection via XTP, let it | |
646 | * distribute interrupts. | |
647 | */ | |
648 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
649 | return cpu_physical_id(smp_processor_id()); | |
650 | ||
651 | /* | |
652 | * Some interrupts (ACPI SCI, for instance) are registered | |
653 | * before the BSP is marked as online. | |
654 | */ | |
655 | if (!cpu_online(smp_processor_id())) | |
656 | return cpu_physical_id(smp_processor_id()); | |
657 | ||
ff741906 | 658 | #ifdef CONFIG_ACPI |
4bbdec7a | 659 | if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR) |
b88e9265 | 660 | return get_cpei_target_cpu(); |
ff741906 AR |
661 | #endif |
662 | ||
1da177e4 LT |
663 | #ifdef CONFIG_NUMA |
664 | { | |
665 | int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0; | |
fbb776c3 | 666 | const struct cpumask *cpu_mask; |
1da177e4 LT |
667 | |
668 | iosapic_index = find_iosapic(gsi); | |
669 | if (iosapic_index < 0 || | |
670 | iosapic_lists[iosapic_index].node == MAX_NUMNODES) | |
671 | goto skip_numa_setup; | |
672 | ||
fbb776c3 RR |
673 | cpu_mask = cpumask_of_node(iosapic_lists[iosapic_index].node); |
674 | num_cpus = 0; | |
675 | for_each_cpu_and(numa_cpu, cpu_mask, &domain) { | |
676 | if (cpu_online(numa_cpu)) | |
677 | num_cpus++; | |
1da177e4 LT |
678 | } |
679 | ||
1da177e4 LT |
680 | if (!num_cpus) |
681 | goto skip_numa_setup; | |
682 | ||
4bbdec7a YI |
683 | /* Use irq assignment to distribute across cpus in node */ |
684 | cpu_index = irq % num_cpus; | |
1da177e4 | 685 | |
fbb776c3 RR |
686 | for_each_cpu_and(numa_cpu, cpu_mask, &domain) |
687 | if (cpu_online(numa_cpu) && i++ >= cpu_index) | |
688 | break; | |
1da177e4 | 689 | |
fbb776c3 | 690 | if (numa_cpu < nr_cpu_ids) |
1da177e4 LT |
691 | return cpu_physical_id(numa_cpu); |
692 | } | |
693 | skip_numa_setup: | |
694 | #endif | |
695 | /* | |
696 | * Otherwise, round-robin interrupt vectors across all the | |
697 | * processors. (It'd be nice if we could be smarter in the | |
698 | * case of NUMA.) | |
699 | */ | |
700 | do { | |
fbb776c3 | 701 | if (++cpu >= nr_cpu_ids) |
1da177e4 | 702 | cpu = 0; |
4994be1b | 703 | } while (!cpu_online(cpu) || !cpu_isset(cpu, domain)); |
1da177e4 LT |
704 | |
705 | return cpu_physical_id(cpu); | |
46cba3dc | 706 | #else /* CONFIG_SMP */ |
1da177e4 LT |
707 | return cpu_physical_id(smp_processor_id()); |
708 | #endif | |
709 | } | |
710 | ||
c9d059de KK |
711 | static inline unsigned char choose_dmode(void) |
712 | { | |
713 | #ifdef CONFIG_SMP | |
714 | if (smp_int_redirect & SMP_IRQ_REDIRECTION) | |
715 | return IOSAPIC_LOWEST_PRIORITY; | |
716 | #endif | |
717 | return IOSAPIC_FIXED; | |
718 | } | |
719 | ||
1da177e4 LT |
720 | /* |
721 | * ACPI can describe IOSAPIC interrupts via static tables and namespace | |
722 | * methods. This provides an interface to register those interrupts and | |
723 | * program the IOSAPIC RTE. | |
724 | */ | |
725 | int | |
726 | iosapic_register_intr (unsigned int gsi, | |
727 | unsigned long polarity, unsigned long trigger) | |
728 | { | |
4bbdec7a | 729 | int irq, mask = 1, err; |
1da177e4 LT |
730 | unsigned int dest; |
731 | unsigned long flags; | |
24eeb568 KK |
732 | struct iosapic_rte_info *rte; |
733 | u32 low32; | |
c9d059de | 734 | unsigned char dmode; |
40598cbe | 735 | |
1da177e4 LT |
736 | /* |
737 | * If this GSI has already been registered (i.e., it's a | |
738 | * shared interrupt, or we lost a race to register it), | |
739 | * don't touch the RTE. | |
740 | */ | |
741 | spin_lock_irqsave(&iosapic_lock, flags); | |
4bbdec7a YI |
742 | irq = __gsi_to_irq(gsi); |
743 | if (irq > 0) { | |
744 | rte = find_rte(irq, gsi); | |
e1b30a39 YI |
745 | if(iosapic_intr_info[irq].count == 0) { |
746 | assign_irq_vector(irq); | |
747 | dynamic_irq_init(irq); | |
748 | } else if (rte->refcnt != NO_REF_RTE) { | |
749 | rte->refcnt++; | |
750 | goto unlock_iosapic_lock; | |
751 | } | |
752 | } else | |
753 | irq = create_irq(); | |
24eeb568 KK |
754 | |
755 | /* If vector is running out, we try to find a sharable vector */ | |
eb21ab24 | 756 | if (irq < 0) { |
4bbdec7a YI |
757 | irq = iosapic_find_sharable_irq(trigger, polarity); |
758 | if (irq < 0) | |
40598cbe | 759 | goto unlock_iosapic_lock; |
4bbdec7a | 760 | } |
1da177e4 | 761 | |
239007b8 | 762 | raw_spin_lock(&irq_desc[irq].lock); |
4bbdec7a | 763 | dest = get_target_cpu(gsi, irq); |
c9d059de KK |
764 | dmode = choose_dmode(); |
765 | err = register_intr(gsi, irq, dmode, polarity, trigger); | |
e3a8f7b8 | 766 | if (err < 0) { |
239007b8 | 767 | raw_spin_unlock(&irq_desc[irq].lock); |
4bbdec7a | 768 | irq = err; |
224685c0 | 769 | goto unlock_iosapic_lock; |
1da177e4 | 770 | } |
e3a8f7b8 YI |
771 | |
772 | /* | |
773 | * If the vector is shared and already unmasked for other | |
774 | * interrupt sources, don't mask it. | |
775 | */ | |
4bbdec7a YI |
776 | low32 = iosapic_intr_info[irq].low32; |
777 | if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK)) | |
e3a8f7b8 | 778 | mask = 0; |
4bbdec7a | 779 | set_rte(gsi, irq, dest, mask); |
1da177e4 LT |
780 | |
781 | printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n", | |
782 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
783 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
4bbdec7a | 784 | cpu_logical_id(dest), dest, irq_to_vector(irq)); |
224685c0 | 785 | |
239007b8 | 786 | raw_spin_unlock(&irq_desc[irq].lock); |
40598cbe YI |
787 | unlock_iosapic_lock: |
788 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
4bbdec7a | 789 | return irq; |
1da177e4 LT |
790 | } |
791 | ||
1da177e4 LT |
792 | void |
793 | iosapic_unregister_intr (unsigned int gsi) | |
794 | { | |
795 | unsigned long flags; | |
4bbdec7a | 796 | int irq, index; |
86bc3dfe | 797 | struct irq_desc *idesc; |
24eeb568 | 798 | u32 low32; |
1da177e4 | 799 | unsigned long trigger, polarity; |
24eeb568 KK |
800 | unsigned int dest; |
801 | struct iosapic_rte_info *rte; | |
1da177e4 LT |
802 | |
803 | /* | |
804 | * If the irq associated with the gsi is not found, | |
805 | * iosapic_unregister_intr() is unbalanced. We need to check | |
806 | * this again after getting locks. | |
807 | */ | |
808 | irq = gsi_to_irq(gsi); | |
809 | if (irq < 0) { | |
46cba3dc ST |
810 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", |
811 | gsi); | |
1da177e4 LT |
812 | WARN_ON(1); |
813 | return; | |
814 | } | |
1da177e4 | 815 | |
40598cbe | 816 | spin_lock_irqsave(&iosapic_lock, flags); |
4bbdec7a | 817 | if ((rte = find_rte(irq, gsi)) == NULL) { |
e3a8f7b8 YI |
818 | printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n", |
819 | gsi); | |
820 | WARN_ON(1); | |
821 | goto out; | |
822 | } | |
1da177e4 | 823 | |
e3a8f7b8 YI |
824 | if (--rte->refcnt > 0) |
825 | goto out; | |
1da177e4 | 826 | |
40598cbe | 827 | idesc = irq_desc + irq; |
e1b30a39 | 828 | rte->refcnt = NO_REF_RTE; |
40598cbe | 829 | |
e3a8f7b8 | 830 | /* Mask the interrupt */ |
4bbdec7a | 831 | low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK; |
c1726d6f | 832 | iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32); |
1da177e4 | 833 | |
4bbdec7a | 834 | iosapic_intr_info[irq].count--; |
e3a8f7b8 YI |
835 | index = find_iosapic(gsi); |
836 | iosapic_lists[index].rtes_inuse--; | |
837 | WARN_ON(iosapic_lists[index].rtes_inuse < 0); | |
24eeb568 | 838 | |
4bbdec7a YI |
839 | trigger = iosapic_intr_info[irq].trigger; |
840 | polarity = iosapic_intr_info[irq].polarity; | |
841 | dest = iosapic_intr_info[irq].dest; | |
e3a8f7b8 YI |
842 | printk(KERN_INFO |
843 | "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n", | |
844 | gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
845 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
4bbdec7a | 846 | cpu_logical_id(dest), dest, irq_to_vector(irq)); |
24eeb568 | 847 | |
e1b30a39 | 848 | if (iosapic_intr_info[irq].count == 0) { |
451fe00c | 849 | #ifdef CONFIG_SMP |
e3a8f7b8 | 850 | /* Clear affinity */ |
e65e49d0 | 851 | cpumask_setall(idesc->affinity); |
451fe00c | 852 | #endif |
e3a8f7b8 | 853 | /* Clear the interrupt information */ |
e1b30a39 YI |
854 | iosapic_intr_info[irq].dest = 0; |
855 | iosapic_intr_info[irq].dmode = 0; | |
856 | iosapic_intr_info[irq].polarity = 0; | |
857 | iosapic_intr_info[irq].trigger = 0; | |
4bbdec7a | 858 | iosapic_intr_info[irq].low32 |= IOSAPIC_MASK; |
1da177e4 | 859 | |
e1b30a39 YI |
860 | /* Destroy and reserve IRQ */ |
861 | destroy_and_reserve_irq(irq); | |
1da177e4 | 862 | } |
24eeb568 | 863 | out: |
40598cbe | 864 | spin_unlock_irqrestore(&iosapic_lock, flags); |
1da177e4 | 865 | } |
1da177e4 LT |
866 | |
867 | /* | |
868 | * ACPI calls this when it finds an entry for a platform interrupt. | |
1da177e4 LT |
869 | */ |
870 | int __init | |
871 | iosapic_register_platform_intr (u32 int_type, unsigned int gsi, | |
872 | int iosapic_vector, u16 eid, u16 id, | |
873 | unsigned long polarity, unsigned long trigger) | |
874 | { | |
875 | static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"}; | |
876 | unsigned char delivery; | |
eb21ab24 | 877 | int irq, vector, mask = 0; |
1da177e4 LT |
878 | unsigned int dest = ((id << 8) | eid) & 0xffff; |
879 | ||
880 | switch (int_type) { | |
881 | case ACPI_INTERRUPT_PMI: | |
e1b30a39 | 882 | irq = vector = iosapic_vector; |
4994be1b | 883 | bind_irq_vector(irq, vector, CPU_MASK_ALL); |
1da177e4 LT |
884 | /* |
885 | * since PMI vector is alloc'd by FW(ACPI) not by kernel, | |
886 | * we need to make sure the vector is available | |
887 | */ | |
4bbdec7a | 888 | iosapic_reassign_vector(irq); |
1da177e4 LT |
889 | delivery = IOSAPIC_PMI; |
890 | break; | |
891 | case ACPI_INTERRUPT_INIT: | |
eb21ab24 YI |
892 | irq = create_irq(); |
893 | if (irq < 0) | |
d4ed8084 | 894 | panic("%s: out of interrupt vectors!\n", __func__); |
eb21ab24 | 895 | vector = irq_to_vector(irq); |
1da177e4 LT |
896 | delivery = IOSAPIC_INIT; |
897 | break; | |
898 | case ACPI_INTERRUPT_CPEI: | |
e1b30a39 | 899 | irq = vector = IA64_CPE_VECTOR; |
4994be1b | 900 | BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL)); |
aa0ebec9 | 901 | delivery = IOSAPIC_FIXED; |
1da177e4 LT |
902 | mask = 1; |
903 | break; | |
904 | default: | |
d4ed8084 | 905 | printk(KERN_ERR "%s: invalid int type 0x%x\n", __func__, |
46cba3dc | 906 | int_type); |
1da177e4 LT |
907 | return -1; |
908 | } | |
909 | ||
4bbdec7a | 910 | register_intr(gsi, irq, delivery, polarity, trigger); |
1da177e4 | 911 | |
46cba3dc ST |
912 | printk(KERN_INFO |
913 | "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)" | |
914 | " vector %d\n", | |
1da177e4 LT |
915 | int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown", |
916 | int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"), | |
917 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | |
918 | cpu_logical_id(dest), dest, vector); | |
919 | ||
4bbdec7a | 920 | set_rte(gsi, irq, dest, mask); |
1da177e4 LT |
921 | return vector; |
922 | } | |
923 | ||
1da177e4 LT |
924 | /* |
925 | * ACPI calls this when it finds an entry for a legacy ISA IRQ override. | |
1da177e4 | 926 | */ |
0f7ac29e | 927 | void __devinit |
1da177e4 LT |
928 | iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi, |
929 | unsigned long polarity, | |
930 | unsigned long trigger) | |
931 | { | |
4bbdec7a | 932 | int vector, irq; |
1da177e4 | 933 | unsigned int dest = cpu_physical_id(smp_processor_id()); |
c9d059de | 934 | unsigned char dmode; |
1da177e4 | 935 | |
e1b30a39 | 936 | irq = vector = isa_irq_to_vector(isa_irq); |
4994be1b | 937 | BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL)); |
c9d059de KK |
938 | dmode = choose_dmode(); |
939 | register_intr(gsi, irq, dmode, polarity, trigger); | |
1da177e4 LT |
940 | |
941 | DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n", | |
942 | isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level", | |
943 | polarity == IOSAPIC_POL_HIGH ? "high" : "low", | |
944 | cpu_logical_id(dest), dest, vector); | |
945 | ||
4bbdec7a | 946 | set_rte(gsi, irq, dest, 1); |
1da177e4 LT |
947 | } |
948 | ||
33b39e84 IY |
949 | void __init |
950 | ia64_native_iosapic_pcat_compat_init(void) | |
951 | { | |
952 | if (pcat_compat) { | |
953 | /* | |
954 | * Disable the compatibility mode interrupts (8259 style), | |
955 | * needs IN/OUT support enabled. | |
956 | */ | |
957 | printk(KERN_INFO | |
958 | "%s: Disabling PC-AT compatible 8259 interrupts\n", | |
959 | __func__); | |
960 | outb(0xff, 0xA1); | |
961 | outb(0xff, 0x21); | |
962 | } | |
963 | } | |
964 | ||
1da177e4 LT |
965 | void __init |
966 | iosapic_system_init (int system_pcat_compat) | |
967 | { | |
4bbdec7a | 968 | int irq; |
1da177e4 | 969 | |
4bbdec7a YI |
970 | for (irq = 0; irq < NR_IRQS; ++irq) { |
971 | iosapic_intr_info[irq].low32 = IOSAPIC_MASK; | |
46cba3dc | 972 | /* mark as unused */ |
4bbdec7a | 973 | INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes); |
e1b30a39 YI |
974 | |
975 | iosapic_intr_info[irq].count = 0; | |
24eeb568 | 976 | } |
1da177e4 LT |
977 | |
978 | pcat_compat = system_pcat_compat; | |
33b39e84 IY |
979 | if (pcat_compat) |
980 | iosapic_pcat_compat_init(); | |
1da177e4 LT |
981 | } |
982 | ||
0e888adc KK |
983 | static inline int |
984 | iosapic_alloc (void) | |
985 | { | |
986 | int index; | |
987 | ||
988 | for (index = 0; index < NR_IOSAPICS; index++) | |
989 | if (!iosapic_lists[index].addr) | |
990 | return index; | |
991 | ||
d4ed8084 | 992 | printk(KERN_WARNING "%s: failed to allocate iosapic\n", __func__); |
0e888adc KK |
993 | return -1; |
994 | } | |
995 | ||
996 | static inline void | |
997 | iosapic_free (int index) | |
998 | { | |
999 | memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0])); | |
1000 | } | |
1001 | ||
1002 | static inline int | |
1003 | iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver) | |
1004 | { | |
1005 | int index; | |
1006 | unsigned int gsi_end, base, end; | |
1007 | ||
1008 | /* check gsi range */ | |
1009 | gsi_end = gsi_base + ((ver >> 16) & 0xff); | |
1010 | for (index = 0; index < NR_IOSAPICS; index++) { | |
1011 | if (!iosapic_lists[index].addr) | |
1012 | continue; | |
1013 | ||
1014 | base = iosapic_lists[index].gsi_base; | |
1015 | end = base + iosapic_lists[index].num_rte - 1; | |
1016 | ||
e6d1ba5c | 1017 | if (gsi_end < base || end < gsi_base) |
0e888adc KK |
1018 | continue; /* OK */ |
1019 | ||
1020 | return -EBUSY; | |
1021 | } | |
1022 | return 0; | |
1023 | } | |
1024 | ||
1025 | int __devinit | |
1da177e4 LT |
1026 | iosapic_init (unsigned long phys_addr, unsigned int gsi_base) |
1027 | { | |
0e888adc | 1028 | int num_rte, err, index; |
1da177e4 LT |
1029 | unsigned int isa_irq, ver; |
1030 | char __iomem *addr; | |
0e888adc KK |
1031 | unsigned long flags; |
1032 | ||
1033 | spin_lock_irqsave(&iosapic_lock, flags); | |
c1726d6f YI |
1034 | index = find_iosapic(gsi_base); |
1035 | if (index >= 0) { | |
1036 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1037 | return -EBUSY; | |
1038 | } | |
1039 | ||
e3a8f7b8 | 1040 | addr = ioremap(phys_addr, 0); |
e7369e01 RK |
1041 | if (addr == NULL) { |
1042 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1043 | return -ENOMEM; | |
1044 | } | |
e3a8f7b8 | 1045 | ver = iosapic_version(addr); |
e3a8f7b8 YI |
1046 | if ((err = iosapic_check_gsi_range(gsi_base, ver))) { |
1047 | iounmap(addr); | |
1048 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1049 | return err; | |
1050 | } | |
1da177e4 | 1051 | |
e3a8f7b8 YI |
1052 | /* |
1053 | * The MAX_REDIR register holds the highest input pin number | |
1054 | * (starting from 0). We add 1 so that we can use it for | |
1055 | * number of pins (= RTEs) | |
1056 | */ | |
1057 | num_rte = ((ver >> 16) & 0xff) + 1; | |
1da177e4 | 1058 | |
e3a8f7b8 YI |
1059 | index = iosapic_alloc(); |
1060 | iosapic_lists[index].addr = addr; | |
1061 | iosapic_lists[index].gsi_base = gsi_base; | |
1062 | iosapic_lists[index].num_rte = num_rte; | |
1da177e4 | 1063 | #ifdef CONFIG_NUMA |
e3a8f7b8 | 1064 | iosapic_lists[index].node = MAX_NUMNODES; |
1da177e4 | 1065 | #endif |
c1726d6f | 1066 | spin_lock_init(&iosapic_lists[index].lock); |
0e888adc | 1067 | spin_unlock_irqrestore(&iosapic_lock, flags); |
1da177e4 LT |
1068 | |
1069 | if ((gsi_base == 0) && pcat_compat) { | |
1070 | /* | |
46cba3dc ST |
1071 | * Map the legacy ISA devices into the IOSAPIC data. Some of |
1072 | * these may get reprogrammed later on with data from the ACPI | |
1073 | * Interrupt Source Override table. | |
1da177e4 LT |
1074 | */ |
1075 | for (isa_irq = 0; isa_irq < 16; ++isa_irq) | |
46cba3dc ST |
1076 | iosapic_override_isa_irq(isa_irq, isa_irq, |
1077 | IOSAPIC_POL_HIGH, | |
1078 | IOSAPIC_EDGE); | |
1da177e4 | 1079 | } |
0e888adc KK |
1080 | return 0; |
1081 | } | |
1082 | ||
1083 | #ifdef CONFIG_HOTPLUG | |
1084 | int | |
1085 | iosapic_remove (unsigned int gsi_base) | |
1086 | { | |
1087 | int index, err = 0; | |
1088 | unsigned long flags; | |
1089 | ||
1090 | spin_lock_irqsave(&iosapic_lock, flags); | |
e3a8f7b8 YI |
1091 | index = find_iosapic(gsi_base); |
1092 | if (index < 0) { | |
1093 | printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n", | |
d4ed8084 | 1094 | __func__, gsi_base); |
e3a8f7b8 YI |
1095 | goto out; |
1096 | } | |
0e888adc | 1097 | |
e3a8f7b8 YI |
1098 | if (iosapic_lists[index].rtes_inuse) { |
1099 | err = -EBUSY; | |
1100 | printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n", | |
d4ed8084 | 1101 | __func__, gsi_base); |
e3a8f7b8 | 1102 | goto out; |
0e888adc | 1103 | } |
e3a8f7b8 YI |
1104 | |
1105 | iounmap(iosapic_lists[index].addr); | |
1106 | iosapic_free(index); | |
0e888adc KK |
1107 | out: |
1108 | spin_unlock_irqrestore(&iosapic_lock, flags); | |
1109 | return err; | |
1da177e4 | 1110 | } |
0e888adc | 1111 | #endif /* CONFIG_HOTPLUG */ |
1da177e4 LT |
1112 | |
1113 | #ifdef CONFIG_NUMA | |
0e888adc | 1114 | void __devinit |
1da177e4 LT |
1115 | map_iosapic_to_node(unsigned int gsi_base, int node) |
1116 | { | |
1117 | int index; | |
1118 | ||
1119 | index = find_iosapic(gsi_base); | |
1120 | if (index < 0) { | |
1121 | printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n", | |
d4ed8084 | 1122 | __func__, gsi_base); |
1da177e4 LT |
1123 | return; |
1124 | } | |
1125 | iosapic_lists[index].node = node; | |
1126 | return; | |
1127 | } | |
1128 | #endif |