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[PATCH] spinlock consolidation
[deliverable/linux.git] / arch / ia64 / kernel / mca.c
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1da177e4
LT		 1/*
2 * File: mca.c
3 * Purpose: Generic MCA handling layer
4 *
5 * Updated for latest kernel
6 * Copyright (C) 2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 *
9 * Copyright (C) 2002 Dell Inc.
10 * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
11 *
12 * Copyright (C) 2002 Intel
13 * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
14 *
15 * Copyright (C) 2001 Intel
16 * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
17 *
18 * Copyright (C) 2000 Intel
19 * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
20 *
21 * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
22 * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
23 *
24 * 03/04/15 D. Mosberger Added INIT backtrace support.
25 * 02/03/25 M. Domsch GUID cleanups
26 *
27 * 02/01/04 J. Hall Aligned MCA stack to 16 bytes, added platform vs. CPU
28 * error flag, set SAL default return values, changed
29 * error record structure to linked list, added init call
30 * to sal_get_state_info_size().
31 *
32 * 01/01/03 F. Lewis Added setup of CMCI and CPEI IRQs, logging of corrected
33 * platform errors, completed code for logging of
34 * corrected & uncorrected machine check errors, and
35 * updated for conformance with Nov. 2000 revision of the
36 * SAL 3.0 spec.
37 * 00/03/29 C. Fleckenstein Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
38 * added min save state dump, added INIT handler.
39 *
40 * 2003-12-08 Keith Owens <kaos@sgi.com>
41 * smp_call_function() must not be called from interrupt context (can
42 * deadlock on tasklist_lock). Use keventd to call smp_call_function().
43 *
44 * 2004-02-01 Keith Owens <kaos@sgi.com>
45 * Avoid deadlock when using printk() for MCA and INIT records.
46 * Delete all record printing code, moved to salinfo_decode in user space.
47 * Mark variables and functions static where possible.
48 * Delete dead variables and functions.
49 * Reorder to remove the need for forward declarations and to consolidate
50 * related code.
51 */
52#include <linux/config.h>
53#include <linux/types.h>
54#include <linux/init.h>
55#include <linux/sched.h>
56#include <linux/interrupt.h>
57#include <linux/irq.h>
58#include <linux/kallsyms.h>
59#include <linux/smp_lock.h>
60#include <linux/bootmem.h>
61#include <linux/acpi.h>
62#include <linux/timer.h>
63#include <linux/module.h>
64#include <linux/kernel.h>
65#include <linux/smp.h>
66#include <linux/workqueue.h>
67
68#include <asm/delay.h>
69#include <asm/machvec.h>
70#include <asm/meminit.h>
71#include <asm/page.h>
72#include <asm/ptrace.h>
73#include <asm/system.h>
74#include <asm/sal.h>
75#include <asm/mca.h>
76
77#include <asm/irq.h>
78#include <asm/hw_irq.h>
79
80#if defined(IA64_MCA_DEBUG_INFO)
81# define IA64_MCA_DEBUG(fmt...) printk(fmt)
82#else
83# define IA64_MCA_DEBUG(fmt...)
84#endif
85
86/* Used by mca_asm.S */
87ia64_mca_sal_to_os_state_t ia64_sal_to_os_handoff_state;
88ia64_mca_os_to_sal_state_t ia64_os_to_sal_handoff_state;
89u64 ia64_mca_serialize;
90DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
91DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
92DEFINE_PER_CPU(u64, ia64_mca_pal_pte); /* PTE to map PAL code */
93DEFINE_PER_CPU(u64, ia64_mca_pal_base); /* vaddr PAL code granule */
94
95unsigned long __per_cpu_mca[NR_CPUS];
96
97/* In mca_asm.S */
98extern void ia64_monarch_init_handler (void);
99extern void ia64_slave_init_handler (void);
100
101static ia64_mc_info_t ia64_mc_info;
102
103#define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
104#define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */
105#define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */
106#define CPE_HISTORY_LENGTH 5
107#define CMC_HISTORY_LENGTH 5
108
109static struct timer_list cpe_poll_timer;
110static struct timer_list cmc_poll_timer;
111/*
112 * This variable tells whether we are currently in polling mode.
113 * Start with this in the wrong state so we won't play w/ timers
114 * before the system is ready.
115 */
116static int cmc_polling_enabled = 1;
117
118/*
119 * Clearing this variable prevents CPE polling from getting activated
120 * in mca_late_init. Use it if your system doesn't provide a CPEI,
121 * but encounters problems retrieving CPE logs. This should only be
122 * necessary for debugging.
123 */
124static int cpe_poll_enabled = 1;
125
126extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
127
128static int mca_init;
129
130/*
131 * IA64_MCA log support
132 */
133#define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */
134#define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */
135
136typedef struct ia64_state_log_s
137{
138 spinlock_t isl_lock;
139 int isl_index;
140 unsigned long isl_count;
141 ia64_err_rec_t *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
142} ia64_state_log_t;
143
144static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
145
146#define IA64_LOG_ALLOCATE(it, size) \
147 {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
148 (ia64_err_rec_t *)alloc_bootmem(size); \
149 ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
150 (ia64_err_rec_t *)alloc_bootmem(size);}
151#define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
152#define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
153#define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
154#define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index
155#define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index
156#define IA64_LOG_INDEX_INC(it) \
157 {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
158 ia64_state_log[it].isl_count++;}
159#define IA64_LOG_INDEX_DEC(it) \
160 ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
161#define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
162#define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
163#define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count
164
165/*
166 * ia64_log_init
167 * Reset the OS ia64 log buffer
168 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
169 * Outputs : None
170 */
171static void
172ia64_log_init(int sal_info_type)
173{
174 u64 max_size = 0;
175
176 IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
177 IA64_LOG_LOCK_INIT(sal_info_type);
178
179 // SAL will tell us the maximum size of any error record of this type
180 max_size = ia64_sal_get_state_info_size(sal_info_type);
181 if (!max_size)
182 /* alloc_bootmem() doesn't like zero-sized allocations! */
183 return;
184
185 // set up OS data structures to hold error info
186 IA64_LOG_ALLOCATE(sal_info_type, max_size);
187 memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
188 memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
189}
190
191/*
192 * ia64_log_get
193 *
194 * Get the current MCA log from SAL and copy it into the OS log buffer.
195 *
196 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
197 * irq_safe whether you can use printk at this point
198 * Outputs : size (total record length)
199 * *buffer (ptr to error record)
200 *
201 */
202static u64
203ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
204{
205 sal_log_record_header_t *log_buffer;
206 u64 total_len = 0;
207 int s;
208
209 IA64_LOG_LOCK(sal_info_type);
210
211 /* Get the process state information */
212 log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
213
214 total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
215
216 if (total_len) {
217 IA64_LOG_INDEX_INC(sal_info_type);
218 IA64_LOG_UNLOCK(sal_info_type);
219 if (irq_safe) {
220 IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
221 "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len);
222 }
223 *buffer = (u8 *) log_buffer;
224 return total_len;
225 } else {
226 IA64_LOG_UNLOCK(sal_info_type);
227 return 0;
228 }
229}
230
231/*
232 * ia64_mca_log_sal_error_record
233 *
234 * This function retrieves a specified error record type from SAL
235 * and wakes up any processes waiting for error records.
236 *
237 * Inputs : sal_info_type (Type of error record MCA/CMC/CPE/INIT)
238 */
239static void
240ia64_mca_log_sal_error_record(int sal_info_type)
241{
242 u8 *buffer;
243 sal_log_record_header_t *rh;
244 u64 size;
245 int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA && sal_info_type != SAL_INFO_TYPE_INIT;
246#ifdef IA64_MCA_DEBUG_INFO
247 static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
248#endif
249
250 size = ia64_log_get(sal_info_type, &buffer, irq_safe);
251 if (!size)
252 return;
253
254 salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
255
256 if (irq_safe)
257 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
258 smp_processor_id(),
259 sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
260
261 /* Clear logs from corrected errors in case there's no user-level logger */
262 rh = (sal_log_record_header_t *)buffer;
263 if (rh->severity == sal_log_severity_corrected)
264 ia64_sal_clear_state_info(sal_info_type);
265}
266
267/*
268 * platform dependent error handling
269 */
270#ifndef PLATFORM_MCA_HANDLERS
271
272#ifdef CONFIG_ACPI
273
55e59c51 274int cpe_vector = -1;
1da177e4
LT		 275
276static irqreturn_t
277ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs)
278{
279 static unsigned long cpe_history[CPE_HISTORY_LENGTH];
280 static int index;
281 static DEFINE_SPINLOCK(cpe_history_lock);
282
283 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
284 __FUNCTION__, cpe_irq, smp_processor_id());
285
286 /* SAL spec states this should run w/ interrupts enabled */
287 local_irq_enable();
288
289 /* Get the CPE error record and log it */
290 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
291
292 spin_lock(&cpe_history_lock);
293 if (!cpe_poll_enabled && cpe_vector >= 0) {
294
295 int i, count = 1; /* we know 1 happened now */
296 unsigned long now = jiffies;
297
298 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
299 if (now - cpe_history[i] <= HZ)
300 count++;
301 }
302
303 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
304 if (count >= CPE_HISTORY_LENGTH) {
305
306 cpe_poll_enabled = 1;
307 spin_unlock(&cpe_history_lock);
308 disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
309
310 /*
311 * Corrected errors will still be corrected, but
312 * make sure there's a log somewhere that indicates
313 * something is generating more than we can handle.
314 */
315 printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
316
317 mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
318
319 /* lock already released, get out now */
320 return IRQ_HANDLED;
321 } else {
322 cpe_history[index++] = now;
323 if (index == CPE_HISTORY_LENGTH)
324 index = 0;
325 }
326 }
327 spin_unlock(&cpe_history_lock);
328 return IRQ_HANDLED;
329}
330
331#endif /* CONFIG_ACPI */
332
333static void
334show_min_state (pal_min_state_area_t *minstate)
335{
336 u64 iip = minstate->pmsa_iip + ((struct ia64_psr *)(&minstate->pmsa_ipsr))->ri;
337 u64 xip = minstate->pmsa_xip + ((struct ia64_psr *)(&minstate->pmsa_xpsr))->ri;
338
339 printk("NaT bits\t%016lx\n", minstate->pmsa_nat_bits);
340 printk("pr\t\t%016lx\n", minstate->pmsa_pr);
341 printk("b0\t\t%016lx ", minstate->pmsa_br0); print_symbol("%s\n", minstate->pmsa_br0);
342 printk("ar.rsc\t\t%016lx\n", minstate->pmsa_rsc);
343 printk("cr.iip\t\t%016lx ", iip); print_symbol("%s\n", iip);
344 printk("cr.ipsr\t\t%016lx\n", minstate->pmsa_ipsr);
345 printk("cr.ifs\t\t%016lx\n", minstate->pmsa_ifs);
346 printk("xip\t\t%016lx ", xip); print_symbol("%s\n", xip);
347 printk("xpsr\t\t%016lx\n", minstate->pmsa_xpsr);
348 printk("xfs\t\t%016lx\n", minstate->pmsa_xfs);
349 printk("b1\t\t%016lx ", minstate->pmsa_br1);
350 print_symbol("%s\n", minstate->pmsa_br1);
351
352 printk("\nstatic registers r0-r15:\n");
353 printk(" r0- 3 %016lx %016lx %016lx %016lx\n",
354 0UL, minstate->pmsa_gr[0], minstate->pmsa_gr[1], minstate->pmsa_gr[2]);
355 printk(" r4- 7 %016lx %016lx %016lx %016lx\n",
356 minstate->pmsa_gr[3], minstate->pmsa_gr[4],
357 minstate->pmsa_gr[5], minstate->pmsa_gr[6]);
358 printk(" r8-11 %016lx %016lx %016lx %016lx\n",
359 minstate->pmsa_gr[7], minstate->pmsa_gr[8],
360 minstate->pmsa_gr[9], minstate->pmsa_gr[10]);
361 printk("r12-15 %016lx %016lx %016lx %016lx\n",
362 minstate->pmsa_gr[11], minstate->pmsa_gr[12],
363 minstate->pmsa_gr[13], minstate->pmsa_gr[14]);
364
365 printk("\nbank 0:\n");
366 printk("r16-19 %016lx %016lx %016lx %016lx\n",
367 minstate->pmsa_bank0_gr[0], minstate->pmsa_bank0_gr[1],
368 minstate->pmsa_bank0_gr[2], minstate->pmsa_bank0_gr[3]);
369 printk("r20-23 %016lx %016lx %016lx %016lx\n",
370 minstate->pmsa_bank0_gr[4], minstate->pmsa_bank0_gr[5],
371 minstate->pmsa_bank0_gr[6], minstate->pmsa_bank0_gr[7]);
372 printk("r24-27 %016lx %016lx %016lx %016lx\n",
373 minstate->pmsa_bank0_gr[8], minstate->pmsa_bank0_gr[9],
374 minstate->pmsa_bank0_gr[10], minstate->pmsa_bank0_gr[11]);
375 printk("r28-31 %016lx %016lx %016lx %016lx\n",
376 minstate->pmsa_bank0_gr[12], minstate->pmsa_bank0_gr[13],
377 minstate->pmsa_bank0_gr[14], minstate->pmsa_bank0_gr[15]);
378
379 printk("\nbank 1:\n");
380 printk("r16-19 %016lx %016lx %016lx %016lx\n",
381 minstate->pmsa_bank1_gr[0], minstate->pmsa_bank1_gr[1],
382 minstate->pmsa_bank1_gr[2], minstate->pmsa_bank1_gr[3]);
383 printk("r20-23 %016lx %016lx %016lx %016lx\n",
384 minstate->pmsa_bank1_gr[4], minstate->pmsa_bank1_gr[5],
385 minstate->pmsa_bank1_gr[6], minstate->pmsa_bank1_gr[7]);
386 printk("r24-27 %016lx %016lx %016lx %016lx\n",
387 minstate->pmsa_bank1_gr[8], minstate->pmsa_bank1_gr[9],
388 minstate->pmsa_bank1_gr[10], minstate->pmsa_bank1_gr[11]);
389 printk("r28-31 %016lx %016lx %016lx %016lx\n",
390 minstate->pmsa_bank1_gr[12], minstate->pmsa_bank1_gr[13],
391 minstate->pmsa_bank1_gr[14], minstate->pmsa_bank1_gr[15]);
392}
393
394static void
395fetch_min_state (pal_min_state_area_t *ms, struct pt_regs *pt, struct switch_stack *sw)
396{
397 u64 *dst_banked, *src_banked, bit, shift, nat_bits;
398 int i;
399
400 /*
401 * First, update the pt-regs and switch-stack structures with the contents stored
402 * in the min-state area:
403 */
404 if (((struct ia64_psr *) &ms->pmsa_ipsr)->ic == 0) {
405 pt->cr_ipsr = ms->pmsa_xpsr;
406 pt->cr_iip = ms->pmsa_xip;
407 pt->cr_ifs = ms->pmsa_xfs;
408 } else {
409 pt->cr_ipsr = ms->pmsa_ipsr;
410 pt->cr_iip = ms->pmsa_iip;
411 pt->cr_ifs = ms->pmsa_ifs;
412 }
413 pt->ar_rsc = ms->pmsa_rsc;
414 pt->pr = ms->pmsa_pr;
415 pt->r1 = ms->pmsa_gr[0];
416 pt->r2 = ms->pmsa_gr[1];
417 pt->r3 = ms->pmsa_gr[2];
418 sw->r4 = ms->pmsa_gr[3];
419 sw->r5 = ms->pmsa_gr[4];
420 sw->r6 = ms->pmsa_gr[5];
421 sw->r7 = ms->pmsa_gr[6];
422 pt->r8 = ms->pmsa_gr[7];
423 pt->r9 = ms->pmsa_gr[8];
424 pt->r10 = ms->pmsa_gr[9];
425 pt->r11 = ms->pmsa_gr[10];
426 pt->r12 = ms->pmsa_gr[11];
427 pt->r13 = ms->pmsa_gr[12];
428 pt->r14 = ms->pmsa_gr[13];
429 pt->r15 = ms->pmsa_gr[14];
430 dst_banked = &pt->r16; /* r16-r31 are contiguous in struct pt_regs */
431 src_banked = ms->pmsa_bank1_gr;
432 for (i = 0; i < 16; ++i)
433 dst_banked[i] = src_banked[i];
434 pt->b0 = ms->pmsa_br0;
435 sw->b1 = ms->pmsa_br1;
436
437 /* construct the NaT bits for the pt-regs structure: */
438# define PUT_NAT_BIT(dst, addr) \
439 do { \
440 bit = nat_bits & 1; nat_bits >>= 1; \
441 shift = ((unsigned long) addr >> 3) & 0x3f; \
442 dst = ((dst) & ~(1UL << shift)) | (bit << shift); \
443 } while (0)
444
445 /* Rotate the saved NaT bits such that bit 0 corresponds to pmsa_gr[0]: */
446 shift = ((unsigned long) &ms->pmsa_gr[0] >> 3) & 0x3f;
447 nat_bits = (ms->pmsa_nat_bits >> shift) | (ms->pmsa_nat_bits << (64 - shift));
448
449 PUT_NAT_BIT(sw->caller_unat, &pt->r1);
450 PUT_NAT_BIT(sw->caller_unat, &pt->r2);
451 PUT_NAT_BIT(sw->caller_unat, &pt->r3);
452 PUT_NAT_BIT(sw->ar_unat, &sw->r4);
453 PUT_NAT_BIT(sw->ar_unat, &sw->r5);
454 PUT_NAT_BIT(sw->ar_unat, &sw->r6);
455 PUT_NAT_BIT(sw->ar_unat, &sw->r7);
456 PUT_NAT_BIT(sw->caller_unat, &pt->r8); PUT_NAT_BIT(sw->caller_unat, &pt->r9);
457 PUT_NAT_BIT(sw->caller_unat, &pt->r10); PUT_NAT_BIT(sw->caller_unat, &pt->r11);
458 PUT_NAT_BIT(sw->caller_unat, &pt->r12); PUT_NAT_BIT(sw->caller_unat, &pt->r13);
459 PUT_NAT_BIT(sw->caller_unat, &pt->r14); PUT_NAT_BIT(sw->caller_unat, &pt->r15);
460 nat_bits >>= 16; /* skip over bank0 NaT bits */
461 PUT_NAT_BIT(sw->caller_unat, &pt->r16); PUT_NAT_BIT(sw->caller_unat, &pt->r17);
462 PUT_NAT_BIT(sw->caller_unat, &pt->r18); PUT_NAT_BIT(sw->caller_unat, &pt->r19);
463 PUT_NAT_BIT(sw->caller_unat, &pt->r20); PUT_NAT_BIT(sw->caller_unat, &pt->r21);
464 PUT_NAT_BIT(sw->caller_unat, &pt->r22); PUT_NAT_BIT(sw->caller_unat, &pt->r23);
465 PUT_NAT_BIT(sw->caller_unat, &pt->r24); PUT_NAT_BIT(sw->caller_unat, &pt->r25);
466 PUT_NAT_BIT(sw->caller_unat, &pt->r26); PUT_NAT_BIT(sw->caller_unat, &pt->r27);
467 PUT_NAT_BIT(sw->caller_unat, &pt->r28); PUT_NAT_BIT(sw->caller_unat, &pt->r29);
468 PUT_NAT_BIT(sw->caller_unat, &pt->r30); PUT_NAT_BIT(sw->caller_unat, &pt->r31);
469}
470
471static void
472init_handler_platform (pal_min_state_area_t *ms,
473 struct pt_regs *pt, struct switch_stack *sw)
474{
475 struct unw_frame_info info;
476
477 /* if a kernel debugger is available call it here else just dump the registers */
478
479 /*
480 * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be
481 * generated via the BMC's command-line interface, but since the console is on the
482 * same serial line, the user will need some time to switch out of the BMC before
483 * the dump begins.
484 */
485 printk("Delaying for 5 seconds...\n");
486 udelay(5*1000000);
487 show_min_state(ms);
488
489 printk("Backtrace of current task (pid %d, %s)\n", current->pid, current->comm);
490 fetch_min_state(ms, pt, sw);
491 unw_init_from_interruption(&info, current, pt, sw);
492 ia64_do_show_stack(&info, NULL);
493
fb1c8f93 494 if (read_trylock(&tasklist_lock)) {
1da177e4
LT		 495 struct task_struct *g, *t;
496 do_each_thread (g, t) {
497 if (t == current)
498 continue;
499
500 printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
501 show_stack(t, NULL);
502 } while_each_thread (g, t);
503 }
1da177e4
LT		 504
505 printk("\nINIT dump complete. Please reboot now.\n");
506 while (1); /* hang city if no debugger */
507}
508
509#ifdef CONFIG_ACPI
510/*
511 * ia64_mca_register_cpev
512 *
513 * Register the corrected platform error vector with SAL.
514 *
515 * Inputs
516 * cpev Corrected Platform Error Vector number
517 *
518 * Outputs
519 * None
520 */
521static void
522ia64_mca_register_cpev (int cpev)
523{
524 /* Register the CPE interrupt vector with SAL */
525 struct ia64_sal_retval isrv;
526
527 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
528 if (isrv.status) {
529 printk(KERN_ERR "Failed to register Corrected Platform "
530 "Error interrupt vector with SAL (status %ld)\n", isrv.status);
531 return;
532 }
533
534 IA64_MCA_DEBUG("%s: corrected platform error "
535 "vector %#x registered\n", __FUNCTION__, cpev);
536}
537#endif /* CONFIG_ACPI */
538
539#endif /* PLATFORM_MCA_HANDLERS */
540
541/*
542 * ia64_mca_cmc_vector_setup
543 *
544 * Setup the corrected machine check vector register in the processor.
545 * (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
546 * This function is invoked on a per-processor basis.
547 *
548 * Inputs
549 * None
550 *
551 * Outputs
552 * None
553 */
554void
555ia64_mca_cmc_vector_setup (void)
556{
557 cmcv_reg_t cmcv;
558
559 cmcv.cmcv_regval = 0;
560 cmcv.cmcv_mask = 1; /* Mask/disable interrupt at first */
561 cmcv.cmcv_vector = IA64_CMC_VECTOR;
562 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
563
564 IA64_MCA_DEBUG("%s: CPU %d corrected "
565 "machine check vector %#x registered.\n",
566 __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR);
567
568 IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
569 __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
570}
571
572/*
573 * ia64_mca_cmc_vector_disable
574 *
575 * Mask the corrected machine check vector register in the processor.
576 * This function is invoked on a per-processor basis.
577 *
578 * Inputs
579 * dummy(unused)
580 *
581 * Outputs
582 * None
583 */
584static void
585ia64_mca_cmc_vector_disable (void *dummy)
586{
587 cmcv_reg_t cmcv;
588
589 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
590
591 cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
592 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
593
594 IA64_MCA_DEBUG("%s: CPU %d corrected "
595 "machine check vector %#x disabled.\n",
596 __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
597}
598
599/*
600 * ia64_mca_cmc_vector_enable
601 *
602 * Unmask the corrected machine check vector register in the processor.
603 * This function is invoked on a per-processor basis.
604 *
605 * Inputs
606 * dummy(unused)
607 *
608 * Outputs
609 * None
610 */
611static void
612ia64_mca_cmc_vector_enable (void *dummy)
613{
614 cmcv_reg_t cmcv;
615
616 cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
617
618 cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
619 ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
620
621 IA64_MCA_DEBUG("%s: CPU %d corrected "
622 "machine check vector %#x enabled.\n",
623 __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
624}
625
626/*
627 * ia64_mca_cmc_vector_disable_keventd
628 *
629 * Called via keventd (smp_call_function() is not safe in interrupt context) to
630 * disable the cmc interrupt vector.
631 */
632static void
633ia64_mca_cmc_vector_disable_keventd(void *unused)
634{
635 on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
636}
637
638/*
639 * ia64_mca_cmc_vector_enable_keventd
640 *
641 * Called via keventd (smp_call_function() is not safe in interrupt context) to
642 * enable the cmc interrupt vector.
643 */
644static void
645ia64_mca_cmc_vector_enable_keventd(void *unused)
646{
647 on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
648}
649
650/*
651 * ia64_mca_wakeup_ipi_wait
652 *
653 * Wait for the inter-cpu interrupt to be sent by the
654 * monarch processor once it is done with handling the
655 * MCA.
656 *
657 * Inputs : None
658 * Outputs : None
659 */
660static void
661ia64_mca_wakeup_ipi_wait(void)
662{
663 int irr_num = (IA64_MCA_WAKEUP_VECTOR >> 6);
664 int irr_bit = (IA64_MCA_WAKEUP_VECTOR & 0x3f);
665 u64 irr = 0;
666
667 do {
668 switch(irr_num) {
669 case 0:
670 irr = ia64_getreg(_IA64_REG_CR_IRR0);
671 break;
672 case 1:
673 irr = ia64_getreg(_IA64_REG_CR_IRR1);
674 break;
675 case 2:
676 irr = ia64_getreg(_IA64_REG_CR_IRR2);
677 break;
678 case 3:
679 irr = ia64_getreg(_IA64_REG_CR_IRR3);
680 break;
681 }
682 cpu_relax();
683 } while (!(irr & (1UL << irr_bit))) ;
684}
685
686/*
687 * ia64_mca_wakeup
688 *
689 * Send an inter-cpu interrupt to wake-up a particular cpu
690 * and mark that cpu to be out of rendez.
691 *
692 * Inputs : cpuid
693 * Outputs : None
694 */
695static void
696ia64_mca_wakeup(int cpu)
697{
698 platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
699 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
700
701}
702
703/*
704 * ia64_mca_wakeup_all
705 *
706 * Wakeup all the cpus which have rendez'ed previously.
707 *
708 * Inputs : None
709 * Outputs : None
710 */
711static void
712ia64_mca_wakeup_all(void)
713{
714 int cpu;
715
716 /* Clear the Rendez checkin flag for all cpus */
717 for(cpu = 0; cpu < NR_CPUS; cpu++) {
718 if (!cpu_online(cpu))
719 continue;
720 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
721 ia64_mca_wakeup(cpu);
722 }
723
724}
725
726/*
727 * ia64_mca_rendez_interrupt_handler
728 *
729 * This is handler used to put slave processors into spinloop
730 * while the monarch processor does the mca handling and later
731 * wake each slave up once the monarch is done.
732 *
733 * Inputs : None
734 * Outputs : None
735 */
736static irqreturn_t
737ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *ptregs)
738{
739 unsigned long flags;
740 int cpu = smp_processor_id();
741
742 /* Mask all interrupts */
743 local_irq_save(flags);
744
745 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
746 /* Register with the SAL monarch that the slave has
747 * reached SAL
748 */
749 ia64_sal_mc_rendez();
750
751 /* Wait for the wakeup IPI from the monarch
752 * This waiting is done by polling on the wakeup-interrupt
753 * vector bit in the processor's IRRs
754 */
755 ia64_mca_wakeup_ipi_wait();
756
757 /* Enable all interrupts */
758 local_irq_restore(flags);
759 return IRQ_HANDLED;
760}
761
762/*
763 * ia64_mca_wakeup_int_handler
764 *
765 * The interrupt handler for processing the inter-cpu interrupt to the
766 * slave cpu which was spinning in the rendez loop.
767 * Since this spinning is done by turning off the interrupts and
768 * polling on the wakeup-interrupt bit in the IRR, there is
769 * nothing useful to be done in the handler.
770 *
771 * Inputs : wakeup_irq (Wakeup-interrupt bit)
772 * arg (Interrupt handler specific argument)
773 * ptregs (Exception frame at the time of the interrupt)
774 * Outputs : None
775 *
776 */
777static irqreturn_t
778ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg, struct pt_regs *ptregs)
779{
780 return IRQ_HANDLED;
781}
782
783/*
784 * ia64_return_to_sal_check
785 *
786 * This is function called before going back from the OS_MCA handler
787 * to the OS_MCA dispatch code which finally takes the control back
788 * to the SAL.
789 * The main purpose of this routine is to setup the OS_MCA to SAL
790 * return state which can be used by the OS_MCA dispatch code
791 * just before going back to SAL.
792 *
793 * Inputs : None
794 * Outputs : None
795 */
796
797static void
798ia64_return_to_sal_check(int recover)
799{
800
801 /* Copy over some relevant stuff from the sal_to_os_mca_handoff
802 * so that it can be used at the time of os_mca_to_sal_handoff
803 */
804 ia64_os_to_sal_handoff_state.imots_sal_gp =
805 ia64_sal_to_os_handoff_state.imsto_sal_gp;
806
807 ia64_os_to_sal_handoff_state.imots_sal_check_ra =
808 ia64_sal_to_os_handoff_state.imsto_sal_check_ra;
809
810 if (recover)
811 ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_CORRECTED;
812 else
813 ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_COLD_BOOT;
814
815 /* Default = tell SAL to return to same context */
816 ia64_os_to_sal_handoff_state.imots_context = IA64_MCA_SAME_CONTEXT;
817
818 ia64_os_to_sal_handoff_state.imots_new_min_state =
819 (u64 *)ia64_sal_to_os_handoff_state.pal_min_state;
820
821}
822
823/* Function pointer for extra MCA recovery */
824int (*ia64_mca_ucmc_extension)
825 (void*,ia64_mca_sal_to_os_state_t*,ia64_mca_os_to_sal_state_t*)
826 = NULL;
827
828int
829ia64_reg_MCA_extension(void *fn)
830{
831 if (ia64_mca_ucmc_extension)
832 return 1;
833
834 ia64_mca_ucmc_extension = fn;
835 return 0;
836}
837
838void
839ia64_unreg_MCA_extension(void)
840{
841 if (ia64_mca_ucmc_extension)
842 ia64_mca_ucmc_extension = NULL;
843}
844
845EXPORT_SYMBOL(ia64_reg_MCA_extension);
846EXPORT_SYMBOL(ia64_unreg_MCA_extension);
847
848/*
849 * ia64_mca_ucmc_handler
850 *
851 * This is uncorrectable machine check handler called from OS_MCA
852 * dispatch code which is in turn called from SAL_CHECK().
853 * This is the place where the core of OS MCA handling is done.
854 * Right now the logs are extracted and displayed in a well-defined
855 * format. This handler code is supposed to be run only on the
856 * monarch processor. Once the monarch is done with MCA handling
857 * further MCA logging is enabled by clearing logs.
858 * Monarch also has the duty of sending wakeup-IPIs to pull the
859 * slave processors out of rendezvous spinloop.
860 *
861 * Inputs : None
862 * Outputs : None
863 */
864void
865ia64_mca_ucmc_handler(void)
866{
867 pal_processor_state_info_t *psp = (pal_processor_state_info_t *)
868 &ia64_sal_to_os_handoff_state.proc_state_param;
869 int recover;
870
871 /* Get the MCA error record and log it */
872 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
873
874 /* TLB error is only exist in this SAL error record */
875 recover = (psp->tc && !(psp->cc || psp->bc || psp->rc || psp->uc))
876 /* other error recovery */
877 || (ia64_mca_ucmc_extension
878 && ia64_mca_ucmc_extension(
879 IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
880 &ia64_sal_to_os_handoff_state,
881 &ia64_os_to_sal_handoff_state));
882
883 if (recover) {
884 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
885 rh->severity = sal_log_severity_corrected;
886 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
887 }
888 /*
889 * Wakeup all the processors which are spinning in the rendezvous
890 * loop.
891 */
892 ia64_mca_wakeup_all();
893
894 /* Return to SAL */
895 ia64_return_to_sal_check(recover);
896}
897
898static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd, NULL);
899static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd, NULL);
900
901/*
902 * ia64_mca_cmc_int_handler
903 *
904 * This is corrected machine check interrupt handler.
905 * Right now the logs are extracted and displayed in a well-defined
906 * format.
907 *
908 * Inputs
909 * interrupt number
910 * client data arg ptr
911 * saved registers ptr
912 *
913 * Outputs
914 * None
915 */
916static irqreturn_t
917ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)
918{
919 static unsigned long cmc_history[CMC_HISTORY_LENGTH];
920 static int index;
921 static DEFINE_SPINLOCK(cmc_history_lock);
922
923 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
924 __FUNCTION__, cmc_irq, smp_processor_id());
925
926 /* SAL spec states this should run w/ interrupts enabled */
927 local_irq_enable();
928
929 /* Get the CMC error record and log it */
930 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
931
932 spin_lock(&cmc_history_lock);
933 if (!cmc_polling_enabled) {
934 int i, count = 1; /* we know 1 happened now */
935 unsigned long now = jiffies;
936
937 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
938 if (now - cmc_history[i] <= HZ)
939 count++;
940 }
941
942 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
943 if (count >= CMC_HISTORY_LENGTH) {
944
945 cmc_polling_enabled = 1;
946 spin_unlock(&cmc_history_lock);
947 schedule_work(&cmc_disable_work);
948
949 /*
950 * Corrected errors will still be corrected, but
951 * make sure there's a log somewhere that indicates
952 * something is generating more than we can handle.
953 */
954 printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
955
956 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
957
958 /* lock already released, get out now */
959 return IRQ_HANDLED;
960 } else {
961 cmc_history[index++] = now;
962 if (index == CMC_HISTORY_LENGTH)
963 index = 0;
964 }
965 }
966 spin_unlock(&cmc_history_lock);
967 return IRQ_HANDLED;
968}
969
970/*
971 * ia64_mca_cmc_int_caller
972 *
973 * Triggered by sw interrupt from CMC polling routine. Calls
974 * real interrupt handler and either triggers a sw interrupt
975 * on the next cpu or does cleanup at the end.
976 *
977 * Inputs
978 * interrupt number
979 * client data arg ptr
980 * saved registers ptr
981 * Outputs
982 * handled
983 */
984static irqreturn_t
985ia64_mca_cmc_int_caller(int cmc_irq, void *arg, struct pt_regs *ptregs)
986{
987 static int start_count = -1;
988 unsigned int cpuid;
989
990 cpuid = smp_processor_id();
991
992 /* If first cpu, update count */
993 if (start_count == -1)
994 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
995
996 ia64_mca_cmc_int_handler(cmc_irq, arg, ptregs);
997
998 for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
999
1000 if (cpuid < NR_CPUS) {
1001 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1002 } else {
1003 /* If no log record, switch out of polling mode */
1004 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1005
1006 printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1007 schedule_work(&cmc_enable_work);
1008 cmc_polling_enabled = 0;
1009
1010 } else {
1011
1012 mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1013 }
1014
1015 start_count = -1;
1016 }
1017
1018 return IRQ_HANDLED;
1019}
1020
1021/*
1022 * ia64_mca_cmc_poll
1023 *
1024 * Poll for Corrected Machine Checks (CMCs)
1025 *
1026 * Inputs : dummy(unused)
1027 * Outputs : None
1028 *
1029 */
1030static void
1031ia64_mca_cmc_poll (unsigned long dummy)
1032{
1033 /* Trigger a CMC interrupt cascade */
1034 platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1035}
1036
1037/*
1038 * ia64_mca_cpe_int_caller
1039 *
1040 * Triggered by sw interrupt from CPE polling routine. Calls
1041 * real interrupt handler and either triggers a sw interrupt
1042 * on the next cpu or does cleanup at the end.
1043 *
1044 * Inputs
1045 * interrupt number
1046 * client data arg ptr
1047 * saved registers ptr
1048 * Outputs
1049 * handled
1050 */
1051#ifdef CONFIG_ACPI
1052
1053static irqreturn_t
1054ia64_mca_cpe_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
1055{
1056 static int start_count = -1;
1057 static int poll_time = MIN_CPE_POLL_INTERVAL;
1058 unsigned int cpuid;
1059
1060 cpuid = smp_processor_id();
1061
1062 /* If first cpu, update count */
1063 if (start_count == -1)
1064 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1065
1066 ia64_mca_cpe_int_handler(cpe_irq, arg, ptregs);
1067
1068 for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1069
1070 if (cpuid < NR_CPUS) {
1071 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1072 } else {
1073 /*
1074 * If a log was recorded, increase our polling frequency,
1075 * otherwise, backoff or return to interrupt mode.
1076 */
1077 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1078 poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1079 } else if (cpe_vector < 0) {
1080 poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1081 } else {
1082 poll_time = MIN_CPE_POLL_INTERVAL;
1083
1084 printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1085 enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1086 cpe_poll_enabled = 0;
1087 }
1088
1089 if (cpe_poll_enabled)
1090 mod_timer(&cpe_poll_timer, jiffies + poll_time);
1091 start_count = -1;
1092 }
1093
1094 return IRQ_HANDLED;
1095}
1096
1da177e4
LT		 1097/*
1098 * ia64_mca_cpe_poll
1099 *
1100 * Poll for Corrected Platform Errors (CPEs), trigger interrupt
1101 * on first cpu, from there it will trickle through all the cpus.
1102 *
1103 * Inputs : dummy(unused)
1104 * Outputs : None
1105 *
1106 */
1107static void
1108ia64_mca_cpe_poll (unsigned long dummy)
1109{
1110 /* Trigger a CPE interrupt cascade */
1111 platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1112}
1113
b655913b
PC		 1114#endif /* CONFIG_ACPI */
1115
1da177e4
LT		 1116/*
1117 * C portion of the OS INIT handler
1118 *
1119 * Called from ia64_monarch_init_handler
1120 *
1121 * Inputs: pointer to pt_regs where processor info was saved.
1122 *
1123 * Returns:
1124 * 0 if SAL must warm boot the System
1125 * 1 if SAL must return to interrupted context using PAL_MC_RESUME
1126 *
1127 */
1128void
1129ia64_init_handler (struct pt_regs *pt, struct switch_stack *sw)
1130{
1131 pal_min_state_area_t *ms;
1132
1133 oops_in_progress = 1; /* avoid deadlock in printk, but it makes recovery dodgy */
1134 console_loglevel = 15; /* make sure printks make it to console */
1135
1136 printk(KERN_INFO "Entered OS INIT handler. PSP=%lx\n",
1137 ia64_sal_to_os_handoff_state.proc_state_param);
1138
1139 /*
1140 * Address of minstate area provided by PAL is physical,
1141 * uncacheable (bit 63 set). Convert to Linux virtual
1142 * address in region 6.
1143 */
1144 ms = (pal_min_state_area_t *)(ia64_sal_to_os_handoff_state.pal_min_state | (6ul<<61));
1145
1146 init_handler_platform(ms, pt, sw); /* call platform specific routines */
1147}
1148
1149static int __init
1150ia64_mca_disable_cpe_polling(char *str)
1151{
1152 cpe_poll_enabled = 0;
1153 return 1;
1154}
1155
1156__setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1157
1158static struct irqaction cmci_irqaction = {
1159 .handler = ia64_mca_cmc_int_handler,
1160 .flags = SA_INTERRUPT,
1161 .name = "cmc_hndlr"
1162};
1163
1164static struct irqaction cmcp_irqaction = {
1165 .handler = ia64_mca_cmc_int_caller,
1166 .flags = SA_INTERRUPT,
1167 .name = "cmc_poll"
1168};
1169
1170static struct irqaction mca_rdzv_irqaction = {
1171 .handler = ia64_mca_rendez_int_handler,
1172 .flags = SA_INTERRUPT,
1173 .name = "mca_rdzv"
1174};
1175
1176static struct irqaction mca_wkup_irqaction = {
1177 .handler = ia64_mca_wakeup_int_handler,
1178 .flags = SA_INTERRUPT,
1179 .name = "mca_wkup"
1180};
1181
1182#ifdef CONFIG_ACPI
1183static struct irqaction mca_cpe_irqaction = {
1184 .handler = ia64_mca_cpe_int_handler,
1185 .flags = SA_INTERRUPT,
1186 .name = "cpe_hndlr"
1187};
1188
1189static struct irqaction mca_cpep_irqaction = {
1190 .handler = ia64_mca_cpe_int_caller,
1191 .flags = SA_INTERRUPT,
1192 .name = "cpe_poll"
1193};
1194#endif /* CONFIG_ACPI */
1195
1196/* Do per-CPU MCA-related initialization. */
1197
1198void __devinit
1199ia64_mca_cpu_init(void *cpu_data)
1200{
1201 void *pal_vaddr;
1202
1203 if (smp_processor_id() == 0) {
1204 void *mca_data;
1205 int cpu;
1206
1207 mca_data = alloc_bootmem(sizeof(struct ia64_mca_cpu)
1208 * NR_CPUS);
1209 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1210 __per_cpu_mca[cpu] = __pa(mca_data);
1211 mca_data += sizeof(struct ia64_mca_cpu);
1212 }
1213 }
1214
1215 /*
1216 * The MCA info structure was allocated earlier and its
1217 * physical address saved in __per_cpu_mca[cpu]. Copy that
1218 * address * to ia64_mca_data so we can access it as a per-CPU
1219 * variable.
1220 */
1221 __get_cpu_var(ia64_mca_data) = __per_cpu_mca[smp_processor_id()];
1222
1223 /*
1224 * Stash away a copy of the PTE needed to map the per-CPU page.
1225 * We may need it during MCA recovery.
1226 */
1227 __get_cpu_var(ia64_mca_per_cpu_pte) =
1228 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL));
1229
1230 /*
1231 * Also, stash away a copy of the PAL address and the PTE
1232 * needed to map it.
1233 */
1234 pal_vaddr = efi_get_pal_addr();
1235 if (!pal_vaddr)
1236 return;
1237 __get_cpu_var(ia64_mca_pal_base) =
1238 GRANULEROUNDDOWN((unsigned long) pal_vaddr);
1239 __get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr),
1240 PAGE_KERNEL));
1241}
1242
1243/*
1244 * ia64_mca_init
1245 *
1246 * Do all the system level mca specific initialization.
1247 *
1248 * 1. Register spinloop and wakeup request interrupt vectors
1249 *
1250 * 2. Register OS_MCA handler entry point
1251 *
1252 * 3. Register OS_INIT handler entry point
1253 *
1254 * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1255 *
1256 * Note that this initialization is done very early before some kernel
1257 * services are available.
1258 *
1259 * Inputs : None
1260 *
1261 * Outputs : None
1262 */
1263void __init
1264ia64_mca_init(void)
1265{
1266 ia64_fptr_t *mon_init_ptr = (ia64_fptr_t *)ia64_monarch_init_handler;
1267 ia64_fptr_t *slave_init_ptr = (ia64_fptr_t *)ia64_slave_init_handler;
1268 ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1269 int i;
1270 s64 rc;
1271 struct ia64_sal_retval isrv;
1272 u64 timeout = IA64_MCA_RENDEZ_TIMEOUT; /* platform specific */
1273
1274 IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__);
1275
1276 /* Clear the Rendez checkin flag for all cpus */
1277 for(i = 0 ; i < NR_CPUS; i++)
1278 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1279
1280 /*
1281 * Register the rendezvous spinloop and wakeup mechanism with SAL
1282 */
1283
1284 /* Register the rendezvous interrupt vector with SAL */
1285 while (1) {
1286 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1287 SAL_MC_PARAM_MECHANISM_INT,
1288 IA64_MCA_RENDEZ_VECTOR,
1289 timeout,
1290 SAL_MC_PARAM_RZ_ALWAYS);
1291 rc = isrv.status;
1292 if (rc == 0)
1293 break;
1294 if (rc == -2) {
1295 printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1296 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1297 timeout = isrv.v0;
1298 continue;
1299 }
1300 printk(KERN_ERR "Failed to register rendezvous interrupt "
1301 "with SAL (status %ld)\n", rc);
1302 return;
1303 }
1304
1305 /* Register the wakeup interrupt vector with SAL */
1306 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1307 SAL_MC_PARAM_MECHANISM_INT,
1308 IA64_MCA_WAKEUP_VECTOR,
1309 0, 0);
1310 rc = isrv.status;
1311 if (rc) {
1312 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1313 "(status %ld)\n", rc);
1314 return;
1315 }
1316
1317 IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__);
1318
1319 ia64_mc_info.imi_mca_handler = ia64_tpa(mca_hldlr_ptr->fp);
1320 /*
1321 * XXX - disable SAL checksum by setting size to 0; should be
1322 * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1323 */
1324 ia64_mc_info.imi_mca_handler_size = 0;
1325
1326 /* Register the os mca handler with SAL */
1327 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1328 ia64_mc_info.imi_mca_handler,
1329 ia64_tpa(mca_hldlr_ptr->gp),
1330 ia64_mc_info.imi_mca_handler_size,
1331 0, 0, 0)))
1332 {
1333 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1334 "(status %ld)\n", rc);
1335 return;
1336 }
1337
1338 IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__,
1339 ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1340
1341 /*
1342 * XXX - disable SAL checksum by setting size to 0, should be
1343 * size of the actual init handler in mca_asm.S.
1344 */
1345 ia64_mc_info.imi_monarch_init_handler = ia64_tpa(mon_init_ptr->fp);
1346 ia64_mc_info.imi_monarch_init_handler_size = 0;
1347 ia64_mc_info.imi_slave_init_handler = ia64_tpa(slave_init_ptr->fp);
1348 ia64_mc_info.imi_slave_init_handler_size = 0;
1349
1350 IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__,
1351 ia64_mc_info.imi_monarch_init_handler);
1352
1353 /* Register the os init handler with SAL */
1354 if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1355 ia64_mc_info.imi_monarch_init_handler,
1356 ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1357 ia64_mc_info.imi_monarch_init_handler_size,
1358 ia64_mc_info.imi_slave_init_handler,
1359 ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1360 ia64_mc_info.imi_slave_init_handler_size)))
1361 {
1362 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1363 "(status %ld)\n", rc);
1364 return;
1365 }
1366
1367 IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__);
1368
1369 /*
1370 * Configure the CMCI/P vector and handler. Interrupts for CMC are
1371 * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1372 */
1373 register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
1374 register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
1375 ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */
1376
1377 /* Setup the MCA rendezvous interrupt vector */
1378 register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
1379
1380 /* Setup the MCA wakeup interrupt vector */
1381 register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
1382
1383#ifdef CONFIG_ACPI
bb68c12b 1384 /* Setup the CPEI/P handler */
1da177e4
LT		 1385 register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
1386#endif
1387
1388 /* Initialize the areas set aside by the OS to buffer the
1389 * platform/processor error states for MCA/INIT/CMC
1390 * handling.
1391 */
1392 ia64_log_init(SAL_INFO_TYPE_MCA);
1393 ia64_log_init(SAL_INFO_TYPE_INIT);
1394 ia64_log_init(SAL_INFO_TYPE_CMC);
1395 ia64_log_init(SAL_INFO_TYPE_CPE);
1396
1397 mca_init = 1;
1398 printk(KERN_INFO "MCA related initialization done\n");
1399}
1400
1401/*
1402 * ia64_mca_late_init
1403 *
1404 * Opportunity to setup things that require initialization later
1405 * than ia64_mca_init. Setup a timer to poll for CPEs if the
1406 * platform doesn't support an interrupt driven mechanism.
1407 *
1408 * Inputs : None
1409 * Outputs : Status
1410 */
1411static int __init
1412ia64_mca_late_init(void)
1413{
1414 if (!mca_init)
1415 return 0;
1416
1417 /* Setup the CMCI/P vector and handler */
1418 init_timer(&cmc_poll_timer);
1419 cmc_poll_timer.function = ia64_mca_cmc_poll;
1420
1421 /* Unmask/enable the vector */
1422 cmc_polling_enabled = 0;
1423 schedule_work(&cmc_enable_work);
1424
1425 IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__);
1426
1427#ifdef CONFIG_ACPI
1428 /* Setup the CPEI/P vector and handler */
bb68c12b 1429 cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
1da177e4
LT		 1430 init_timer(&cpe_poll_timer);
1431 cpe_poll_timer.function = ia64_mca_cpe_poll;
1432
1433 {
1434 irq_desc_t *desc;
1435 unsigned int irq;
1436
1437 if (cpe_vector >= 0) {
1438 /* If platform supports CPEI, enable the irq. */
1439 cpe_poll_enabled = 0;
1440 for (irq = 0; irq < NR_IRQS; ++irq)
1441 if (irq_to_vector(irq) == cpe_vector) {
1442 desc = irq_descp(irq);
1443 desc->status |= IRQ_PER_CPU;
1444 setup_irq(irq, &mca_cpe_irqaction);
1445 }
1446 ia64_mca_register_cpev(cpe_vector);
1447 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__);
1448 } else {
1449 /* If platform doesn't support CPEI, get the timer going. */
1450 if (cpe_poll_enabled) {
1451 ia64_mca_cpe_poll(0UL);
1452 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__);
1453 }
1454 }
1455 }
1456#endif
1457
1458 return 0;
1459}
1460
1461device_initcall(ia64_mca_late_init);
Linux kernel - Deliverables
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