Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
[deliverable/linux.git] / arch / ia64 / kernel / msi_ia64.c
CommitLineData
fd58e55f
MM
1/*
2 * MSI hooks for standard x86 apic
3 */
4
5#include <linux/pci.h>
6#include <linux/irq.h>
3b7d1921 7#include <linux/msi.h>
62fdd767 8#include <linux/dmar.h>
a4cffb64 9#include <asm/smp.h>
2fa8937f 10#include <asm/msidef.h>
fd58e55f 11
3b7d1921 12static struct irq_chip ia64_msi_chip;
fd58e55f 13
3b7d1921 14#ifdef CONFIG_SMP
f1f701e9
TG
15static int ia64_set_msi_irq_affinity(struct irq_data *idata,
16 const cpumask_t *cpu_mask, bool force)
fd58e55f 17{
3b7d1921 18 struct msi_msg msg;
cd378f18 19 u32 addr, data;
785aebd0 20 int cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
f1f701e9 21 unsigned int irq = idata->irq;
3b7d1921 22
a6cd6322 23 if (irq_prepare_move(irq, cpu))
d5dedd45 24 return -1;
4994be1b 25
507a883e 26 __get_cached_msi_msg(irq_data_get_msi_desc(idata), &msg);
fd58e55f 27
3b7d1921 28 addr = msg.address_lo;
2fa8937f
XZ
29 addr &= MSI_ADDR_DEST_ID_MASK;
30 addr |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu));
3b7d1921 31 msg.address_lo = addr;
fd58e55f 32
cd378f18
YI
33 data = msg.data;
34 data &= MSI_DATA_VECTOR_MASK;
35 data |= MSI_DATA_VECTOR(irq_to_vector(irq));
36 msg.data = data;
37
83a18912 38 pci_write_msi_msg(irq, &msg);
c42574ed 39 cpumask_copy(irq_data_get_affinity_mask(idata), cpumask_of(cpu));
d5dedd45
YL
40
41 return 0;
fd58e55f 42}
3b7d1921 43#endif /* CONFIG_SMP */
fd58e55f 44
f7feaca7 45int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
fd58e55f 46{
3b7d1921 47 struct msi_msg msg;
fd58e55f 48 unsigned long dest_phys_id;
8a3a0ee7 49 int irq, vector;
fd58e55f 50
f7feaca7
EB
51 irq = create_irq();
52 if (irq < 0)
53 return irq;
54
53c909c9 55 irq_set_msi_desc(irq, desc);
51f7bd85
RR
56 dest_phys_id = cpu_physical_id(cpumask_any_and(&(irq_to_domain(irq)),
57 cpu_online_mask));
9438a121 58 vector = irq_to_vector(irq);
fd58e55f 59
3b7d1921
EB
60 msg.address_hi = 0;
61 msg.address_lo =
38bc0361 62 MSI_ADDR_HEADER |
2fa8937f 63 MSI_ADDR_DEST_MODE_PHYS |
38bc0361 64 MSI_ADDR_REDIRECTION_CPU |
2fa8937f 65 MSI_ADDR_DEST_ID_CPU(dest_phys_id);
fd58e55f 66
3b7d1921 67 msg.data =
38bc0361 68 MSI_DATA_TRIGGER_EDGE |
fd58e55f
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69 MSI_DATA_LEVEL_ASSERT |
70 MSI_DATA_DELIVERY_FIXED |
71 MSI_DATA_VECTOR(vector);
72
83a18912 73 pci_write_msi_msg(irq, &msg);
53c909c9 74 irq_set_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);
3b7d1921 75
3aff0373 76 return 0;
fd58e55f
MM
77}
78
3b7d1921 79void ia64_teardown_msi_irq(unsigned int irq)
fd58e55f 80{
f7feaca7 81 destroy_irq(irq);
fd58e55f
MM
82}
83
f1f701e9 84static void ia64_ack_msi_irq(struct irq_data *data)
3b7d1921 85{
f1f701e9 86 irq_complete_move(data->irq);
97499b2e 87 irq_move_irq(data);
3b7d1921
EB
88 ia64_eoi();
89}
90
f1f701e9 91static int ia64_msi_retrigger_irq(struct irq_data *data)
3b7d1921 92{
f1f701e9 93 unsigned int vector = irq_to_vector(data->irq);
3b7d1921
EB
94 ia64_resend_irq(vector);
95
96 return 1;
97}
98
fd58e55f 99/*
3b7d1921 100 * Generic ops used on most IA64 platforms.
fd58e55f 101 */
3b7d1921 102static struct irq_chip ia64_msi_chip = {
f1f701e9 103 .name = "PCI-MSI",
280510f1
TG
104 .irq_mask = pci_msi_mask_irq,
105 .irq_unmask = pci_msi_unmask_irq,
f1f701e9 106 .irq_ack = ia64_ack_msi_irq,
3b7d1921 107#ifdef CONFIG_SMP
f1f701e9 108 .irq_set_affinity = ia64_set_msi_irq_affinity,
3b7d1921 109#endif
f1f701e9 110 .irq_retrigger = ia64_msi_retrigger_irq,
fd58e55f 111};
3b7d1921
EB
112
113
f7feaca7 114int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
3b7d1921
EB
115{
116 if (platform_setup_msi_irq)
f7feaca7 117 return platform_setup_msi_irq(pdev, desc);
3b7d1921 118
f7feaca7 119 return ia64_setup_msi_irq(pdev, desc);
3b7d1921
EB
120}
121
122void arch_teardown_msi_irq(unsigned int irq)
123{
124 if (platform_teardown_msi_irq)
125 return platform_teardown_msi_irq(irq);
126
127 return ia64_teardown_msi_irq(irq);
128}
62fdd767 129
d3f13810 130#ifdef CONFIG_INTEL_IOMMU
62fdd767 131#ifdef CONFIG_SMP
f1f701e9
TG
132static int dmar_msi_set_affinity(struct irq_data *data,
133 const struct cpumask *mask, bool force)
62fdd767 134{
f1f701e9 135 unsigned int irq = data->irq;
62fdd767
FY
136 struct irq_cfg *cfg = irq_cfg + irq;
137 struct msi_msg msg;
785aebd0 138 int cpu = cpumask_first_and(mask, cpu_online_mask);
62fdd767
FY
139
140 if (irq_prepare_move(irq, cpu))
d5dedd45 141 return -1;
62fdd767
FY
142
143 dmar_msi_read(irq, &msg);
144
145 msg.data &= ~MSI_DATA_VECTOR_MASK;
146 msg.data |= MSI_DATA_VECTOR(cfg->vector);
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147 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
148 msg.address_lo |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu));
62fdd767
FY
149
150 dmar_msi_write(irq, &msg);
c42574ed 151 cpumask_copy(irq_data_get_affinity_mask(data), mask);
d5dedd45
YL
152
153 return 0;
62fdd767
FY
154}
155#endif /* CONFIG_SMP */
156
9542b21e 157static struct irq_chip dmar_msi_type = {
62fdd767 158 .name = "DMAR_MSI",
5c2837fb
TG
159 .irq_unmask = dmar_msi_unmask,
160 .irq_mask = dmar_msi_mask,
f1f701e9 161 .irq_ack = ia64_ack_msi_irq,
62fdd767 162#ifdef CONFIG_SMP
f1f701e9 163 .irq_set_affinity = dmar_msi_set_affinity,
62fdd767 164#endif
f1f701e9 165 .irq_retrigger = ia64_msi_retrigger_irq,
62fdd767
FY
166};
167
34742db8 168static void
62fdd767
FY
169msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
170{
171 struct irq_cfg *cfg = irq_cfg + irq;
172 unsigned dest;
62fdd767 173
51f7bd85
RR
174 dest = cpu_physical_id(cpumask_first_and(&(irq_to_domain(irq)),
175 cpu_online_mask));
62fdd767
FY
176
177 msg->address_hi = 0;
178 msg->address_lo =
179 MSI_ADDR_HEADER |
2fa8937f 180 MSI_ADDR_DEST_MODE_PHYS |
62fdd767 181 MSI_ADDR_REDIRECTION_CPU |
2fa8937f 182 MSI_ADDR_DEST_ID_CPU(dest);
62fdd767
FY
183
184 msg->data =
185 MSI_DATA_TRIGGER_EDGE |
186 MSI_DATA_LEVEL_ASSERT |
187 MSI_DATA_DELIVERY_FIXED |
188 MSI_DATA_VECTOR(cfg->vector);
62fdd767
FY
189}
190
34742db8 191int dmar_alloc_hwirq(int id, int node, void *arg)
62fdd767 192{
34742db8 193 int irq;
62fdd767
FY
194 struct msi_msg msg;
195
34742db8
JL
196 irq = create_irq();
197 if (irq > 0) {
198 irq_set_handler_data(irq, arg);
199 irq_set_chip_and_handler_name(irq, &dmar_msi_type,
200 handle_edge_irq, "edge");
201 msi_compose_msg(NULL, irq, &msg);
202 dmar_msi_write(irq, &msg);
203 }
204
205 return irq;
206}
207
208void dmar_free_hwirq(int irq)
209{
210 irq_set_handler_data(irq, NULL);
211 destroy_irq(irq);
62fdd767 212}
d3f13810 213#endif /* CONFIG_INTEL_IOMMU */
62fdd767 214
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