[deliverable/linux.git] / arch / ia64 / sn / kernel / irq.c

/*
 * Platform dependent support for SGI SN
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (c) 2000-2008 Silicon Graphics, Inc.  All Rights Reserved.
 */

#include <linux/irq.h>
#include <linux/spinlock.h>
#include <linux/init.h>
#include <linux/rculist.h>
#include <linux/slab.h>
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>
#include <asm/sn/intr.h>
#include <asm/sn/pcibr_provider.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include <asm/sn/shub_mmr.h>
#include <asm/sn/sn_sal.h>
#include <asm/sn/sn_feature_sets.h>

static void register_intr_pda(struct sn_irq_info *sn_irq_info);
static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);

extern int sn_ioif_inited;
struct list_head **sn_irq_lh;
static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */

u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
				     struct sn_irq_info *sn_irq_info,
				     int req_irq, nasid_t req_nasid,
				     int req_slice)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
			(u64) SAL_INTR_ALLOC, (u64) local_nasid,
			(u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
			(u64) req_nasid, (u64) req_slice);

	return ret_stuff.status;
}

void sn_intr_free(nasid_t local_nasid, int local_widget,
				struct sn_irq_info *sn_irq_info)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
			(u64) SAL_INTR_FREE, (u64) local_nasid,
			(u64) local_widget, (u64) sn_irq_info->irq_irq,
			(u64) sn_irq_info->irq_cookie, 0, 0);
}

u64 sn_intr_redirect(nasid_t local_nasid, int local_widget,
		      struct sn_irq_info *sn_irq_info,
		      nasid_t req_nasid, int req_slice)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
			(u64) SAL_INTR_REDIRECT, (u64) local_nasid,
			(u64) local_widget, __pa(sn_irq_info),
			(u64) req_nasid, (u64) req_slice, 0);

	return ret_stuff.status;
}

static unsigned int sn_startup_irq(struct irq_data *data)
{
	return 0;
}

static void sn_shutdown_irq(struct irq_data *data)
{
}

extern void ia64_mca_register_cpev(int);

static void sn_disable_irq(struct irq_data *data)
{
	if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR))
		ia64_mca_register_cpev(0);
}

static void sn_enable_irq(struct irq_data *data)
{
	if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR))
		ia64_mca_register_cpev(data->irq);
}

static void sn_ack_irq(struct irq_data *data)
{
	u64 event_occurred, mask;
	unsigned int irq = data->irq & 0xff;

	event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
	mask = event_occurred & SH_ALL_INT_MASK;
	HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
	__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);

	irq_move_irq(data);
}

struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
				       nasid_t nasid, int slice)
{
	int vector;
	int cpuid;
#ifdef CONFIG_SMP
	int cpuphys;
#endif
	int64_t bridge;
	int local_widget, status;
	nasid_t local_nasid;
	struct sn_irq_info *new_irq_info;
	struct sn_pcibus_provider *pci_provider;

	bridge = (u64) sn_irq_info->irq_bridge;
	if (!bridge) {
		return NULL; /* irq is not a device interrupt */
	}

	local_nasid = NASID_GET(bridge);

	if (local_nasid & 1)
		local_widget = TIO_SWIN_WIDGETNUM(bridge);
	else
		local_widget = SWIN_WIDGETNUM(bridge);
	vector = sn_irq_info->irq_irq;

	/* Make use of SAL_INTR_REDIRECT if PROM supports it */
	status = sn_intr_redirect(local_nasid, local_widget, sn_irq_info, nasid, slice);
	if (!status) {
		new_irq_info = sn_irq_info;
		goto finish_up;
	}

	/*
	 * PROM does not support SAL_INTR_REDIRECT, or it failed.
	 * Revert to old method.
	 */
	new_irq_info = kmemdup(sn_irq_info, sizeof(struct sn_irq_info),
			       GFP_ATOMIC);
	if (new_irq_info == NULL)
		return NULL;

	/* Free the old PROM new_irq_info structure */
	sn_intr_free(local_nasid, local_widget, new_irq_info);
	unregister_intr_pda(new_irq_info);

	/* allocate a new PROM new_irq_info struct */
	status = sn_intr_alloc(local_nasid, local_widget,
			       new_irq_info, vector,
			       nasid, slice);

	/* SAL call failed */
	if (status) {
		kfree(new_irq_info);
		return NULL;
	}

	register_intr_pda(new_irq_info);
	spin_lock(&sn_irq_info_lock);
	list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
	spin_unlock(&sn_irq_info_lock);
	kfree_rcu(sn_irq_info, rcu);


finish_up:
	/* Update kernels new_irq_info with new target info */
	cpuid = nasid_slice_to_cpuid(new_irq_info->irq_nasid,
				     new_irq_info->irq_slice);
	new_irq_info->irq_cpuid = cpuid;

	pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];

	/*
	 * If this represents a line interrupt, target it.  If it's
	 * an msi (irq_int_bit < 0), it's already targeted.
	 */
	if (new_irq_info->irq_int_bit >= 0 &&
	    pci_provider && pci_provider->target_interrupt)
		(pci_provider->target_interrupt)(new_irq_info);

#ifdef CONFIG_SMP
	cpuphys = cpu_physical_id(cpuid);
	set_irq_affinity_info((vector & 0xff), cpuphys, 0);
#endif

	return new_irq_info;
}

static int sn_set_affinity_irq(struct irq_data *data,
			       const struct cpumask *mask, bool force)
{
	struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
	unsigned int irq = data->irq;
	nasid_t nasid;
	int slice;

	nasid = cpuid_to_nasid(cpumask_first_and(mask, cpu_online_mask));
	slice = cpuid_to_slice(cpumask_first_and(mask, cpu_online_mask));

	list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
				 sn_irq_lh[irq], list)
		(void)sn_retarget_vector(sn_irq_info, nasid, slice);

	return 0;
}

#ifdef CONFIG_SMP
void sn_set_err_irq_affinity(unsigned int irq)
{
        /*
         * On systems which support CPU disabling (SHub2), all error interrupts
         * are targeted at the boot CPU.
         */
        if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT))
                set_irq_affinity_info(irq, cpu_physical_id(0), 0);
}
#else
void sn_set_err_irq_affinity(unsigned int irq) { }
#endif

static void
sn_mask_irq(struct irq_data *data)
{
}

static void
sn_unmask_irq(struct irq_data *data)
{
}

struct irq_chip irq_type_sn = {
	.name			= "SN hub",
	.irq_startup		= sn_startup_irq,
	.irq_shutdown		= sn_shutdown_irq,
	.irq_enable		= sn_enable_irq,
	.irq_disable		= sn_disable_irq,
	.irq_ack		= sn_ack_irq,
	.irq_mask		= sn_mask_irq,
	.irq_unmask		= sn_unmask_irq,
	.irq_set_affinity	= sn_set_affinity_irq
};

ia64_vector sn_irq_to_vector(int irq)
{
	if (irq >= IA64_NUM_VECTORS)
		return 0;
	return (ia64_vector)irq;
}

unsigned int sn_local_vector_to_irq(u8 vector)
{
	return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
}

void sn_irq_init(void)
{
	int i;

	ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
	ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;

	for (i = 0; i < NR_IRQS; i++) {
		if (irq_get_chip(i) == &no_irq_chip)
			irq_set_chip(i, &irq_type_sn);
	}
}

static void register_intr_pda(struct sn_irq_info *sn_irq_info)
{
	int irq = sn_irq_info->irq_irq;
	int cpu = sn_irq_info->irq_cpuid;

	if (pdacpu(cpu)->sn_last_irq < irq) {
		pdacpu(cpu)->sn_last_irq = irq;
	}

	if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq)
		pdacpu(cpu)->sn_first_irq = irq;
}

static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
{
	int irq = sn_irq_info->irq_irq;
	int cpu = sn_irq_info->irq_cpuid;
	struct sn_irq_info *tmp_irq_info;
	int i, foundmatch;

	rcu_read_lock();
	if (pdacpu(cpu)->sn_last_irq == irq) {
		foundmatch = 0;
		for (i = pdacpu(cpu)->sn_last_irq - 1;
		     i && !foundmatch; i--) {
			list_for_each_entry_rcu(tmp_irq_info,
						sn_irq_lh[i],
						list) {
				if (tmp_irq_info->irq_cpuid == cpu) {
					foundmatch = 1;
					break;
				}
			}
		}
		pdacpu(cpu)->sn_last_irq = i;
	}

	if (pdacpu(cpu)->sn_first_irq == irq) {
		foundmatch = 0;
		for (i = pdacpu(cpu)->sn_first_irq + 1;
		     i < NR_IRQS && !foundmatch; i++) {
			list_for_each_entry_rcu(tmp_irq_info,
						sn_irq_lh[i],
						list) {
				if (tmp_irq_info->irq_cpuid == cpu) {
					foundmatch = 1;
					break;
				}
			}
		}
		pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
	}
	rcu_read_unlock();
}

void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
{
	nasid_t nasid = sn_irq_info->irq_nasid;
	int slice = sn_irq_info->irq_slice;
	int cpu = nasid_slice_to_cpuid(nasid, slice);
#ifdef CONFIG_SMP
	int cpuphys;
#endif

	pci_dev_get(pci_dev);
	sn_irq_info->irq_cpuid = cpu;
	sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);

	/* link it into the sn_irq[irq] list */
	spin_lock(&sn_irq_info_lock);
	list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
	reserve_irq_vector(sn_irq_info->irq_irq);
	if (sn_irq_info->irq_int_bit != -1)
		irq_set_handler(sn_irq_info->irq_irq, handle_level_irq);
	spin_unlock(&sn_irq_info_lock);

	register_intr_pda(sn_irq_info);
#ifdef CONFIG_SMP
	cpuphys = cpu_physical_id(cpu);
	set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0);
	/*
	 * Affinity was set by the PROM, prevent it from
	 * being reset by the request_irq() path.
	 */
	irqd_mark_affinity_was_set(irq_get_irq_data(sn_irq_info->irq_irq));
#endif
}

void sn_irq_unfixup(struct pci_dev *pci_dev)
{
	struct sn_irq_info *sn_irq_info;

	/* Only cleanup IRQ stuff if this device has a host bus context */
	if (!SN_PCIDEV_BUSSOFT(pci_dev))
		return;

	sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
	if (!sn_irq_info)
		return;
	if (!sn_irq_info->irq_irq) {
		kfree(sn_irq_info);
		return;
	}

	unregister_intr_pda(sn_irq_info);
	spin_lock(&sn_irq_info_lock);
	list_del_rcu(&sn_irq_info->list);
	spin_unlock(&sn_irq_info_lock);
	if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
		free_irq_vector(sn_irq_info->irq_irq);
	kfree_rcu(sn_irq_info, rcu);
	pci_dev_put(pci_dev);

}

static inline void
sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
{
	struct sn_pcibus_provider *pci_provider;

	pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];

	/* Don't force an interrupt if the irq has been disabled */
	if (!irqd_irq_disabled(irq_get_irq_data(sn_irq_info->irq_irq)) &&
	    pci_provider && pci_provider->force_interrupt)
		(*pci_provider->force_interrupt)(sn_irq_info);
}

/*
 * Check for lost interrupts.  If the PIC int_status reg. says that
 * an interrupt has been sent, but not handled, and the interrupt
 * is not pending in either the cpu irr regs or in the soft irr regs,
 * and the interrupt is not in service, then the interrupt may have
 * been lost.  Force an interrupt on that pin.  It is possible that
 * the interrupt is in flight, so we may generate a spurious interrupt,
 * but we should never miss a real lost interrupt.
 */
static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
{
	u64 regval;
	struct pcidev_info *pcidev_info;
	struct pcibus_info *pcibus_info;

	/*
	 * Bridge types attached to TIO (anything but PIC) do not need this WAR
	 * since they do not target Shub II interrupt registers.  If that
	 * ever changes, this check needs to accommodate.
	 */
	if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
		return;

	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	if (!pcidev_info)
		return;

	pcibus_info =
	    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	    pdi_pcibus_info;
	regval = pcireg_intr_status_get(pcibus_info);

	if (!ia64_get_irr(irq_to_vector(irq))) {
		if (!test_bit(irq, pda->sn_in_service_ivecs)) {
			regval &= 0xff;
			if (sn_irq_info->irq_int_bit & regval &
			    sn_irq_info->irq_last_intr) {
				regval &= ~(sn_irq_info->irq_int_bit & regval);
				sn_call_force_intr_provider(sn_irq_info);
			}
		}
	}
	sn_irq_info->irq_last_intr = regval;
}

void sn_lb_int_war_check(void)
{
	struct sn_irq_info *sn_irq_info;
	int i;

	if (!sn_ioif_inited || pda->sn_first_irq == 0)
		return;

	rcu_read_lock();
	for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
		list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
			sn_check_intr(i, sn_irq_info);
		}
	}
	rcu_read_unlock();
}

void __init sn_irq_lh_init(void)
{
	int i;

	sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL);
	if (!sn_irq_lh)
		panic("SN PCI INIT: Failed to allocate memory for PCI init\n");

	for (i = 0; i < NR_IRQS; i++) {
		sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
		if (!sn_irq_lh[i])
			panic("SN PCI INIT: Failed IRQ memory allocation\n");

		INIT_LIST_HEAD(sn_irq_lh[i]);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Platform dependent support for SGI SN
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
ff740fb0	8	* Copyright (c) 2000-2008 Silicon Graphics, Inc. All Rights Reserved.
1da177e4 LT	9	*/
	10
	11	#include <linux/irq.h>
cb4cb2cb	12	#include <linux/spinlock.h>
2fcc3db0	13	#include <linux/init.h>
82524746	14	#include <linux/rculist.h>
5a0e3ad6	15	#include <linux/slab.h>
1da177e4 LT	16	#include <asm/sn/addrs.h>
1da177e4 LT	17	#include <asm/sn/arch.h>
c13cf371 PB	18	#include <asm/sn/intr.h>
c13cf371 PB	19	#include <asm/sn/pcibr_provider.h>
9b08ebd1 MM	20	#include <asm/sn/pcibus_provider_defs.h>
9b08ebd1 MM	21	#include <asm/sn/pcidev.h>
1da177e4 LT	22	#include <asm/sn/shub_mmr.h>
1da177e4 LT	23	#include <asm/sn/sn_sal.h>
6e9de181	24	#include <asm/sn/sn_feature_sets.h>
1da177e4	25
1da177e4 LT	26	static void register_intr_pda(struct sn_irq_info *sn_irq_info);
	27	static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
	28
1da177e4	29	extern int sn_ioif_inited;
83821d3f	30	struct list_head **sn_irq_lh;
34af946a	31	static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */
1da177e4	32
83821d3f MM	33	u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
83821d3f MM	34	struct sn_irq_info *sn_irq_info,
1da177e4 LT	35	int req_irq, nasid_t req_nasid,
	36	int req_slice)
	37	{
	38	struct ia64_sal_retval ret_stuff;
	39	ret_stuff.status = 0;
	40	ret_stuff.v0 = 0;
	41
	42	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
	43	(u64) SAL_INTR_ALLOC, (u64) local_nasid,
83821d3f	44	(u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
1da177e4	45	(u64) req_nasid, (u64) req_slice);
83821d3f	46
1da177e4 LT	47	return ret_stuff.status;
	48	}
	49
83821d3f	50	void sn_intr_free(nasid_t local_nasid, int local_widget,
1da177e4 LT	51	struct sn_irq_info *sn_irq_info)
	52	{
	53	struct ia64_sal_retval ret_stuff;
	54	ret_stuff.status = 0;
	55	ret_stuff.v0 = 0;
	56
	57	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
	58	(u64) SAL_INTR_FREE, (u64) local_nasid,
	59	(u64) local_widget, (u64) sn_irq_info->irq_irq,
	60	(u64) sn_irq_info->irq_cookie, 0, 0);
	61	}
	62
0e17b560 JK	63	u64 sn_intr_redirect(nasid_t local_nasid, int local_widget,
	64	struct sn_irq_info *sn_irq_info,
	65	nasid_t req_nasid, int req_slice)
	66	{
	67	struct ia64_sal_retval ret_stuff;
	68	ret_stuff.status = 0;
	69	ret_stuff.v0 = 0;
	70
	71	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
	72	(u64) SAL_INTR_REDIRECT, (u64) local_nasid,
	73	(u64) local_widget, __pa(sn_irq_info),
	74	(u64) req_nasid, (u64) req_slice, 0);
	75
	76	return ret_stuff.status;
	77	}
	78
545c8d8d	79	static unsigned int sn_startup_irq(struct irq_data *data)
1da177e4 LT	80	{
	81	return 0;
	82	}
	83
545c8d8d	84	static void sn_shutdown_irq(struct irq_data *data)
1da177e4 LT	85	{
	86	}
	87
1f3b6045 RA	88	extern void ia64_mca_register_cpev(int);
1f3b6045 RA	89
545c8d8d	90	static void sn_disable_irq(struct irq_data *data)
1da177e4	91	{
545c8d8d	92	if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR))
1f3b6045	93	ia64_mca_register_cpev(0);
1da177e4 LT	94	}
1da177e4 LT	95
545c8d8d	96	static void sn_enable_irq(struct irq_data *data)
1da177e4	97	{
545c8d8d TG	98	if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR))
545c8d8d TG	99	ia64_mca_register_cpev(data->irq);
1da177e4 LT	100	}
1da177e4 LT	101
545c8d8d	102	static void sn_ack_irq(struct irq_data *data)
1da177e4	103	{
2fcc3db0	104	u64 event_occurred, mask;
545c8d8d	105	unsigned int irq = data->irq & 0xff;
1da177e4	106
2fcc3db0	107	event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
be539c73	108	mask = event_occurred & SH_ALL_INT_MASK;
2fcc3db0	109	HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
1da177e4 LT	110	__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
1da177e4 LT	111
b5f01496	112	irq_move_irq(data);
1da177e4 LT	113	}
1da177e4 LT	114
83821d3f MM	115	struct sn_irq_info sn_retarget_vector(struct sn_irq_info sn_irq_info,
83821d3f MM	116	nasid_t nasid, int slice)
1da177e4	117	{
83821d3f	118	int vector;
c6957771 JK	119	int cpuid;
c6957771 JK	120	#ifdef CONFIG_SMP
83821d3f	121	int cpuphys;
c6957771	122	#endif
83821d3f MM	123	int64_t bridge;
	124	int local_widget, status;
	125	nasid_t local_nasid;
	126	struct sn_irq_info *new_irq_info;
	127	struct sn_pcibus_provider *pci_provider;
	128
0e17b560	129	bridge = (u64) sn_irq_info->irq_bridge;
83821d3f	130	if (!bridge) {
83821d3f MM	131	return NULL; /* irq is not a device interrupt */
83821d3f MM	132	}
1da177e4	133
83821d3f	134	local_nasid = NASID_GET(bridge);
1da177e4	135
83821d3f MM	136	if (local_nasid & 1)
	137	local_widget = TIO_SWIN_WIDGETNUM(bridge);
	138	else
	139	local_widget = SWIN_WIDGETNUM(bridge);
83821d3f	140	vector = sn_irq_info->irq_irq;
0e17b560 JK	141
	142	/* Make use of SAL_INTR_REDIRECT if PROM supports it */
	143	status = sn_intr_redirect(local_nasid, local_widget, sn_irq_info, nasid, slice);
	144	if (!status) {
	145	new_irq_info = sn_irq_info;
	146	goto finish_up;
	147	}
	148
	149	/*
	150	* PROM does not support SAL_INTR_REDIRECT, or it failed.
	151	* Revert to old method.
	152	*/
b82a3ecd TM	153	new_irq_info = kmemdup(sn_irq_info, sizeof(struct sn_irq_info),
b82a3ecd TM	154	GFP_ATOMIC);
0e17b560 JK	155	if (new_irq_info == NULL)
	156	return NULL;
	157
83821d3f MM	158	/* Free the old PROM new_irq_info structure */
83821d3f MM	159	sn_intr_free(local_nasid, local_widget, new_irq_info);
83821d3f	160	unregister_intr_pda(new_irq_info);
1da177e4	161
83821d3f MM	162	/* allocate a new PROM new_irq_info struct */
	163	status = sn_intr_alloc(local_nasid, local_widget,
	164	new_irq_info, vector,
	165	nasid, slice);
1da177e4	166
83821d3f MM	167	/* SAL call failed */
	168	if (status) {
	169	kfree(new_irq_info);
	170	return NULL;
	171	}
cb4cb2cb	172
0e17b560 JK	173	register_intr_pda(new_irq_info);
	174	spin_lock(&sn_irq_info_lock);
	175	list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
	176	spin_unlock(&sn_irq_info_lock);
f218a7ee	177	kfree_rcu(sn_irq_info, rcu);
0e17b560 JK	178
	179
	180	finish_up:
c6957771 JK	181	/* Update kernels new_irq_info with new target info */
	182	cpuid = nasid_slice_to_cpuid(new_irq_info->irq_nasid,
	183	new_irq_info->irq_slice);
	184	new_irq_info->irq_cpuid = cpuid;
1da177e4	185
83821d3f	186	pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
cb4cb2cb	187
83821d3f MM	188	/*
	189	* If this represents a line interrupt, target it. If it's
	190	* an msi (irq_int_bit < 0), it's already targeted.
	191	*/
	192	if (new_irq_info->irq_int_bit >= 0 &&
	193	pci_provider && pci_provider->target_interrupt)
	194	(pci_provider->target_interrupt)(new_irq_info);
cb4cb2cb	195
1da177e4	196	#ifdef CONFIG_SMP
c6957771	197	cpuphys = cpu_physical_id(cpuid);
83821d3f	198	set_irq_affinity_info((vector & 0xff), cpuphys, 0);
1da177e4	199	#endif
83821d3f MM	200
	201	return new_irq_info;
	202	}
	203
545c8d8d TG	204	static int sn_set_affinity_irq(struct irq_data *data,
545c8d8d TG	205	const struct cpumask *mask, bool force)
83821d3f MM	206	{
83821d3f MM	207	struct sn_irq_info sn_irq_info, sn_irq_info_safe;
545c8d8d	208	unsigned int irq = data->irq;
83821d3f MM	209	nasid_t nasid;
	210	int slice;
	211
785aebd0 TG	212	nasid = cpuid_to_nasid(cpumask_first_and(mask, cpu_online_mask));
785aebd0 TG	213	slice = cpuid_to_slice(cpumask_first_and(mask, cpu_online_mask));
83821d3f MM	214
	215	list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
	216	sn_irq_lh[irq], list)
	217	(void)sn_retarget_vector(sn_irq_info, nasid, slice);
d5dedd45 YL	218
d5dedd45 YL	219	return 0;
1da177e4 LT	220	}
1da177e4 LT	221
6e9de181 JK	222	#ifdef CONFIG_SMP
	223	void sn_set_err_irq_affinity(unsigned int irq)
	224	{
	225	/*
	226	* On systems which support CPU disabling (SHub2), all error interrupts
25985edc	227	* are targeted at the boot CPU.
6e9de181 JK	228	*/
	229	if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT))
	230	set_irq_affinity_info(irq, cpu_physical_id(0), 0);
	231	}
	232	#else
	233	void sn_set_err_irq_affinity(unsigned int irq) { }
	234	#endif
	235
e253eb0c	236	static void
545c8d8d	237	sn_mask_irq(struct irq_data *data)
e253eb0c KH	238	{
	239	}
	240
	241	static void
545c8d8d	242	sn_unmask_irq(struct irq_data *data)
e253eb0c KH	243	{
	244	}
	245
	246	struct irq_chip irq_type_sn = {
545c8d8d TG	247	.name = "SN hub",
	248	.irq_startup = sn_startup_irq,
	249	.irq_shutdown = sn_shutdown_irq,
	250	.irq_enable = sn_enable_irq,
	251	.irq_disable = sn_disable_irq,
	252	.irq_ack = sn_ack_irq,
	253	.irq_mask = sn_mask_irq,
	254	.irq_unmask = sn_unmask_irq,
	255	.irq_set_affinity = sn_set_affinity_irq
1da177e4 LT	256	};
1da177e4 LT	257
1115200a KK	258	ia64_vector sn_irq_to_vector(int irq)
	259	{
	260	if (irq >= IA64_NUM_VECTORS)
	261	return 0;
	262	return (ia64_vector)irq;
	263	}
	264
1da177e4 LT	265	unsigned int sn_local_vector_to_irq(u8 vector)
	266	{
	267	return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
	268	}
	269
	270	void sn_irq_init(void)
	271	{
	272	int i;
1da177e4	273
10083072 MM	274	ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
	275	ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
	276
1da177e4	277	for (i = 0; i < NR_IRQS; i++) {
a2178334 TG	278	if (irq_get_chip(i) == &no_irq_chip)
a2178334 TG	279	irq_set_chip(i, &irq_type_sn);
1da177e4 LT	280	}
	281	}
	282
	283	static void register_intr_pda(struct sn_irq_info *sn_irq_info)
	284	{
	285	int irq = sn_irq_info->irq_irq;
	286	int cpu = sn_irq_info->irq_cpuid;
	287
	288	if (pdacpu(cpu)->sn_last_irq < irq) {
	289	pdacpu(cpu)->sn_last_irq = irq;
	290	}
	291
2fcc3db0	292	if (pdacpu(cpu)->sn_first_irq == 0 \|\| pdacpu(cpu)->sn_first_irq > irq)
1da177e4	293	pdacpu(cpu)->sn_first_irq = irq;
1da177e4 LT	294	}
	295
	296	static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
	297	{
	298	int irq = sn_irq_info->irq_irq;
	299	int cpu = sn_irq_info->irq_cpuid;
	300	struct sn_irq_info *tmp_irq_info;
	301	int i, foundmatch;
	302
cb4cb2cb	303	rcu_read_lock();
1da177e4 LT	304	if (pdacpu(cpu)->sn_last_irq == irq) {
1da177e4 LT	305	foundmatch = 0;
cb4cb2cb PB	306	for (i = pdacpu(cpu)->sn_last_irq - 1;
	307	i && !foundmatch; i--) {
	308	list_for_each_entry_rcu(tmp_irq_info,
	309	sn_irq_lh[i],
	310	list) {
1da177e4	311	if (tmp_irq_info->irq_cpuid == cpu) {
cb4cb2cb	312	foundmatch = 1;
1da177e4 LT	313	break;
1da177e4 LT	314	}
1da177e4 LT	315	}
	316	}
	317	pdacpu(cpu)->sn_last_irq = i;
	318	}
	319
	320	if (pdacpu(cpu)->sn_first_irq == irq) {
	321	foundmatch = 0;
cb4cb2cb PB	322	for (i = pdacpu(cpu)->sn_first_irq + 1;
	323	i < NR_IRQS && !foundmatch; i++) {
	324	list_for_each_entry_rcu(tmp_irq_info,
	325	sn_irq_lh[i],
	326	list) {
1da177e4	327	if (tmp_irq_info->irq_cpuid == cpu) {
cb4cb2cb	328	foundmatch = 1;
1da177e4 LT	329	break;
1da177e4 LT	330	}
1da177e4 LT	331	}
	332	}
	333	pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
	334	}
cb4cb2cb	335	rcu_read_unlock();
1da177e4 LT	336	}
1da177e4 LT	337
1da177e4 LT	338	void sn_irq_fixup(struct pci_dev pci_dev, struct sn_irq_info sn_irq_info)
	339	{
	340	nasid_t nasid = sn_irq_info->irq_nasid;
	341	int slice = sn_irq_info->irq_slice;
	342	int cpu = nasid_slice_to_cpuid(nasid, slice);
c6957771 JK	343	#ifdef CONFIG_SMP
	344	int cpuphys;
	345	#endif
1da177e4	346
cb4cb2cb	347	pci_dev_get(pci_dev);
1da177e4 LT	348	sn_irq_info->irq_cpuid = cpu;
	349	sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);
	350
	351	/* link it into the sn_irq[irq] list */
cb4cb2cb PB	352	spin_lock(&sn_irq_info_lock);
cb4cb2cb PB	353	list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
10083072	354	reserve_irq_vector(sn_irq_info->irq_irq);
48e30fa0 DS	355	if (sn_irq_info->irq_int_bit != -1)
48e30fa0 DS	356	irq_set_handler(sn_irq_info->irq_irq, handle_level_irq);
cb4cb2cb	357	spin_unlock(&sn_irq_info_lock);
1da177e4	358
2fcc3db0	359	register_intr_pda(sn_irq_info);
c6957771 JK	360	#ifdef CONFIG_SMP
	361	cpuphys = cpu_physical_id(cpu);
	362	set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0);
ff740fb0 JK	363	/*
	364	* Affinity was set by the PROM, prevent it from
	365	* being reset by the request_irq() path.
	366	*/
33776b00	367	irqd_mark_affinity_was_set(irq_get_irq_data(sn_irq_info->irq_irq));
c6957771	368	#endif
1da177e4 LT	369	}
1da177e4 LT	370
cb4cb2cb PB	371	void sn_irq_unfixup(struct pci_dev *pci_dev)
	372	{
	373	struct sn_irq_info *sn_irq_info;
	374
	375	/* Only cleanup IRQ stuff if this device has a host bus context */
	376	if (!SN_PCIDEV_BUSSOFT(pci_dev))
	377	return;
	378
	379	sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
8b34ff42 PB	380	if (!sn_irq_info)
	381	return;
	382	if (!sn_irq_info->irq_irq) {
6f354b01	383	kfree(sn_irq_info);
cb4cb2cb	384	return;
6f354b01	385	}
cb4cb2cb PB	386
	387	unregister_intr_pda(sn_irq_info);
	388	spin_lock(&sn_irq_info_lock);
	389	list_del_rcu(&sn_irq_info->list);
	390	spin_unlock(&sn_irq_info_lock);
10083072 MM	391	if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
10083072 MM	392	free_irq_vector(sn_irq_info->irq_irq);
f218a7ee	393	kfree_rcu(sn_irq_info, rcu);
cb4cb2cb	394	pci_dev_put(pci_dev);
10083072	395
cb4cb2cb PB	396	}
cb4cb2cb PB	397
735e60f4 MM	398	static inline void
	399	sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
	400	{
	401	struct sn_pcibus_provider *pci_provider;
	402
	403	pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
352b0ef5 MH	404
352b0ef5 MH	405	/* Don't force an interrupt if the irq has been disabled */
4275f4c8	406	if (!irqd_irq_disabled(irq_get_irq_data(sn_irq_info->irq_irq)) &&
352b0ef5	407	pci_provider && pci_provider->force_interrupt)
735e60f4 MM	408	(*pci_provider->force_interrupt)(sn_irq_info);
	409	}
	410
1da177e4 LT	411	/*
	412	* Check for lost interrupts. If the PIC int_status reg. says that
	413	* an interrupt has been sent, but not handled, and the interrupt
	414	* is not pending in either the cpu irr regs or in the soft irr regs,
	415	* and the interrupt is not in service, then the interrupt may have
	416	* been lost. Force an interrupt on that pin. It is possible that
	417	* the interrupt is in flight, so we may generate a spurious interrupt,
	418	* but we should never miss a real lost interrupt.
	419	*/
	420	static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
	421	{
53493dcf	422	u64 regval;
1da177e4 LT	423	struct pcidev_info *pcidev_info;
	424	struct pcibus_info *pcibus_info;
	425
735e60f4 MM	426	/*
	427	* Bridge types attached to TIO (anything but PIC) do not need this WAR
	428	* since they do not target Shub II interrupt registers. If that
25985edc	429	* ever changes, this check needs to accommodate.
735e60f4 MM	430	*/
	431	if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
	432	return;
	433
1da177e4 LT	434	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
	435	if (!pcidev_info)
	436	return;
	437
	438	pcibus_info =
	439	(struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
	440	pdi_pcibus_info;
	441	regval = pcireg_intr_status_get(pcibus_info);
	442
9a4e5549	443	if (!ia64_get_irr(irq_to_vector(irq))) {
735e60f4 MM	444	if (!test_bit(irq, pda->sn_in_service_ivecs)) {
	445	regval &= 0xff;
	446	if (sn_irq_info->irq_int_bit & regval &
	447	sn_irq_info->irq_last_intr) {
	448	regval &= ~(sn_irq_info->irq_int_bit & regval);
	449	sn_call_force_intr_provider(sn_irq_info);
1da177e4 LT	450	}
	451	}
	452	}
	453	sn_irq_info->irq_last_intr = regval;
	454	}
	455
	456	void sn_lb_int_war_check(void)
	457	{
cb4cb2cb	458	struct sn_irq_info *sn_irq_info;
1da177e4 LT	459	int i;
	460
	461	if (!sn_ioif_inited \|\| pda->sn_first_irq == 0)
	462	return;
cb4cb2cb PB	463
cb4cb2cb PB	464	rcu_read_lock();
1da177e4	465	for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
cb4cb2cb	466	list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
735e60f4	467	sn_check_intr(i, sn_irq_info);
1da177e4 LT	468	}
1da177e4 LT	469	}
cb4cb2cb PB	470	rcu_read_unlock();
	471	}
	472
2fcc3db0	473	void __init sn_irq_lh_init(void)
cb4cb2cb PB	474	{
	475	int i;
	476
	477	sn_irq_lh = kmalloc(sizeof(struct list_head ) NR_IRQS, GFP_KERNEL);
	478	if (!sn_irq_lh)
	479	panic("SN PCI INIT: Failed to allocate memory for PCI init\n");
	480
	481	for (i = 0; i < NR_IRQS; i++) {
	482	sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
	483	if (!sn_irq_lh[i])
	484	panic("SN PCI INIT: Failed IRQ memory allocation\n");
	485
	486	INIT_LIST_HEAD(sn_irq_lh[i]);
	487	}
1da177e4	488	}