Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Platform dependent support for SGI SN | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
2fcc3db0 | 8 | * Copyright (c) 2000-2006 Silicon Graphics, Inc. All Rights Reserved. |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/irq.h> | |
cb4cb2cb | 12 | #include <linux/spinlock.h> |
2fcc3db0 | 13 | #include <linux/init.h> |
1da177e4 LT |
14 | #include <asm/sn/addrs.h> |
15 | #include <asm/sn/arch.h> | |
c13cf371 PB |
16 | #include <asm/sn/intr.h> |
17 | #include <asm/sn/pcibr_provider.h> | |
9b08ebd1 MM |
18 | #include <asm/sn/pcibus_provider_defs.h> |
19 | #include <asm/sn/pcidev.h> | |
1da177e4 LT |
20 | #include <asm/sn/shub_mmr.h> |
21 | #include <asm/sn/sn_sal.h> | |
22 | ||
23 | static void force_interrupt(int irq); | |
24 | static void register_intr_pda(struct sn_irq_info *sn_irq_info); | |
25 | static void unregister_intr_pda(struct sn_irq_info *sn_irq_info); | |
26 | ||
d0d59b98 | 27 | int sn_force_interrupt_flag = 1; |
1da177e4 | 28 | extern int sn_ioif_inited; |
cb4cb2cb PB |
29 | static struct list_head **sn_irq_lh; |
30 | static spinlock_t sn_irq_info_lock = SPIN_LOCK_UNLOCKED; /* non-IRQ lock */ | |
1da177e4 | 31 | |
53493dcf | 32 | static inline u64 sn_intr_alloc(nasid_t local_nasid, int local_widget, |
1da177e4 LT |
33 | u64 sn_irq_info, |
34 | int req_irq, nasid_t req_nasid, | |
35 | int req_slice) | |
36 | { | |
37 | struct ia64_sal_retval ret_stuff; | |
38 | ret_stuff.status = 0; | |
39 | ret_stuff.v0 = 0; | |
40 | ||
41 | SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT, | |
42 | (u64) SAL_INTR_ALLOC, (u64) local_nasid, | |
43 | (u64) local_widget, (u64) sn_irq_info, (u64) req_irq, | |
44 | (u64) req_nasid, (u64) req_slice); | |
45 | return ret_stuff.status; | |
46 | } | |
47 | ||
48 | static inline void sn_intr_free(nasid_t local_nasid, int local_widget, | |
49 | struct sn_irq_info *sn_irq_info) | |
50 | { | |
51 | struct ia64_sal_retval ret_stuff; | |
52 | ret_stuff.status = 0; | |
53 | ret_stuff.v0 = 0; | |
54 | ||
55 | SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT, | |
56 | (u64) SAL_INTR_FREE, (u64) local_nasid, | |
57 | (u64) local_widget, (u64) sn_irq_info->irq_irq, | |
58 | (u64) sn_irq_info->irq_cookie, 0, 0); | |
59 | } | |
60 | ||
61 | static unsigned int sn_startup_irq(unsigned int irq) | |
62 | { | |
63 | return 0; | |
64 | } | |
65 | ||
66 | static void sn_shutdown_irq(unsigned int irq) | |
67 | { | |
68 | } | |
69 | ||
70 | static void sn_disable_irq(unsigned int irq) | |
71 | { | |
72 | } | |
73 | ||
74 | static void sn_enable_irq(unsigned int irq) | |
75 | { | |
76 | } | |
77 | ||
78 | static void sn_ack_irq(unsigned int irq) | |
79 | { | |
2fcc3db0 | 80 | u64 event_occurred, mask; |
1da177e4 LT |
81 | |
82 | irq = irq & 0xff; | |
2fcc3db0 | 83 | event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED)); |
be539c73 | 84 | mask = event_occurred & SH_ALL_INT_MASK; |
2fcc3db0 | 85 | HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask); |
1da177e4 LT |
86 | __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs); |
87 | ||
689388bb | 88 | move_native_irq(irq); |
1da177e4 LT |
89 | } |
90 | ||
91 | static void sn_end_irq(unsigned int irq) | |
92 | { | |
1da177e4 | 93 | int ivec; |
0aa2c72e | 94 | u64 event_occurred; |
1da177e4 LT |
95 | |
96 | ivec = irq & 0xff; | |
97 | if (ivec == SGI_UART_VECTOR) { | |
0aa2c72e | 98 | event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED)); |
cb4cb2cb | 99 | /* If the UART bit is set here, we may have received an |
1da177e4 LT |
100 | * interrupt from the UART that the driver missed. To |
101 | * make sure, we IPI ourselves to force us to look again. | |
102 | */ | |
103 | if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) { | |
104 | platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR, | |
105 | IA64_IPI_DM_INT, 0); | |
106 | } | |
107 | } | |
108 | __clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs); | |
109 | if (sn_force_interrupt_flag) | |
110 | force_interrupt(irq); | |
111 | } | |
112 | ||
cb4cb2cb PB |
113 | static void sn_irq_info_free(struct rcu_head *head); |
114 | ||
1da177e4 LT |
115 | static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask) |
116 | { | |
cb4cb2cb | 117 | struct sn_irq_info *sn_irq_info, *sn_irq_info_safe; |
1da177e4 | 118 | int cpuid, cpuphys; |
1da177e4 LT |
119 | |
120 | cpuid = first_cpu(mask); | |
121 | cpuphys = cpu_physical_id(cpuid); | |
1da177e4 | 122 | |
cb4cb2cb PB |
123 | list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe, |
124 | sn_irq_lh[irq], list) { | |
53493dcf | 125 | u64 bridge; |
cb4cb2cb PB |
126 | int local_widget, status; |
127 | nasid_t local_nasid; | |
128 | struct sn_irq_info *new_irq_info; | |
8409668b | 129 | struct sn_pcibus_provider *pci_provider; |
cb4cb2cb PB |
130 | |
131 | new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC); | |
132 | if (new_irq_info == NULL) | |
133 | break; | |
134 | memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info)); | |
135 | ||
53493dcf | 136 | bridge = (u64) new_irq_info->irq_bridge; |
cb4cb2cb PB |
137 | if (!bridge) { |
138 | kfree(new_irq_info); | |
139 | break; /* irq is not a device interrupt */ | |
140 | } | |
1da177e4 | 141 | |
cb4cb2cb | 142 | local_nasid = NASID_GET(bridge); |
1da177e4 LT |
143 | |
144 | if (local_nasid & 1) | |
145 | local_widget = TIO_SWIN_WIDGETNUM(bridge); | |
146 | else | |
147 | local_widget = SWIN_WIDGETNUM(bridge); | |
148 | ||
cb4cb2cb PB |
149 | /* Free the old PROM new_irq_info structure */ |
150 | sn_intr_free(local_nasid, local_widget, new_irq_info); | |
151 | /* Update kernels new_irq_info with new target info */ | |
152 | unregister_intr_pda(new_irq_info); | |
1da177e4 | 153 | |
cb4cb2cb | 154 | /* allocate a new PROM new_irq_info struct */ |
1da177e4 | 155 | status = sn_intr_alloc(local_nasid, local_widget, |
cb4cb2cb PB |
156 | __pa(new_irq_info), irq, |
157 | cpuid_to_nasid(cpuid), | |
158 | cpuid_to_slice(cpuid)); | |
159 | ||
160 | /* SAL call failed */ | |
161 | if (status) { | |
162 | kfree(new_irq_info); | |
163 | break; | |
164 | } | |
1da177e4 | 165 | |
cb4cb2cb PB |
166 | new_irq_info->irq_cpuid = cpuid; |
167 | register_intr_pda(new_irq_info); | |
168 | ||
8409668b MM |
169 | pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type]; |
170 | if (pci_provider && pci_provider->target_interrupt) | |
171 | (pci_provider->target_interrupt)(new_irq_info); | |
cb4cb2cb PB |
172 | |
173 | spin_lock(&sn_irq_info_lock); | |
174 | list_replace_rcu(&sn_irq_info->list, &new_irq_info->list); | |
175 | spin_unlock(&sn_irq_info_lock); | |
176 | call_rcu(&sn_irq_info->rcu, sn_irq_info_free); | |
1da177e4 LT |
177 | |
178 | #ifdef CONFIG_SMP | |
cb4cb2cb | 179 | set_irq_affinity_info((irq & 0xff), cpuphys, 0); |
1da177e4 | 180 | #endif |
1da177e4 | 181 | } |
1da177e4 LT |
182 | } |
183 | ||
184 | struct hw_interrupt_type irq_type_sn = { | |
cb4cb2cb PB |
185 | .typename = "SN hub", |
186 | .startup = sn_startup_irq, | |
187 | .shutdown = sn_shutdown_irq, | |
188 | .enable = sn_enable_irq, | |
189 | .disable = sn_disable_irq, | |
190 | .ack = sn_ack_irq, | |
191 | .end = sn_end_irq, | |
192 | .set_affinity = sn_set_affinity_irq | |
1da177e4 LT |
193 | }; |
194 | ||
195 | unsigned int sn_local_vector_to_irq(u8 vector) | |
196 | { | |
197 | return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector)); | |
198 | } | |
199 | ||
200 | void sn_irq_init(void) | |
201 | { | |
202 | int i; | |
203 | irq_desc_t *base_desc = irq_desc; | |
204 | ||
205 | for (i = 0; i < NR_IRQS; i++) { | |
206 | if (base_desc[i].handler == &no_irq_type) { | |
207 | base_desc[i].handler = &irq_type_sn; | |
208 | } | |
209 | } | |
210 | } | |
211 | ||
212 | static void register_intr_pda(struct sn_irq_info *sn_irq_info) | |
213 | { | |
214 | int irq = sn_irq_info->irq_irq; | |
215 | int cpu = sn_irq_info->irq_cpuid; | |
216 | ||
217 | if (pdacpu(cpu)->sn_last_irq < irq) { | |
218 | pdacpu(cpu)->sn_last_irq = irq; | |
219 | } | |
220 | ||
2fcc3db0 | 221 | if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq) |
1da177e4 | 222 | pdacpu(cpu)->sn_first_irq = irq; |
1da177e4 LT |
223 | } |
224 | ||
225 | static void unregister_intr_pda(struct sn_irq_info *sn_irq_info) | |
226 | { | |
227 | int irq = sn_irq_info->irq_irq; | |
228 | int cpu = sn_irq_info->irq_cpuid; | |
229 | struct sn_irq_info *tmp_irq_info; | |
230 | int i, foundmatch; | |
231 | ||
cb4cb2cb | 232 | rcu_read_lock(); |
1da177e4 LT |
233 | if (pdacpu(cpu)->sn_last_irq == irq) { |
234 | foundmatch = 0; | |
cb4cb2cb PB |
235 | for (i = pdacpu(cpu)->sn_last_irq - 1; |
236 | i && !foundmatch; i--) { | |
237 | list_for_each_entry_rcu(tmp_irq_info, | |
238 | sn_irq_lh[i], | |
239 | list) { | |
1da177e4 | 240 | if (tmp_irq_info->irq_cpuid == cpu) { |
cb4cb2cb | 241 | foundmatch = 1; |
1da177e4 LT |
242 | break; |
243 | } | |
1da177e4 LT |
244 | } |
245 | } | |
246 | pdacpu(cpu)->sn_last_irq = i; | |
247 | } | |
248 | ||
249 | if (pdacpu(cpu)->sn_first_irq == irq) { | |
250 | foundmatch = 0; | |
cb4cb2cb PB |
251 | for (i = pdacpu(cpu)->sn_first_irq + 1; |
252 | i < NR_IRQS && !foundmatch; i++) { | |
253 | list_for_each_entry_rcu(tmp_irq_info, | |
254 | sn_irq_lh[i], | |
255 | list) { | |
1da177e4 | 256 | if (tmp_irq_info->irq_cpuid == cpu) { |
cb4cb2cb | 257 | foundmatch = 1; |
1da177e4 LT |
258 | break; |
259 | } | |
1da177e4 LT |
260 | } |
261 | } | |
262 | pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i); | |
263 | } | |
cb4cb2cb | 264 | rcu_read_unlock(); |
1da177e4 LT |
265 | } |
266 | ||
cb4cb2cb | 267 | static void sn_irq_info_free(struct rcu_head *head) |
1da177e4 LT |
268 | { |
269 | struct sn_irq_info *sn_irq_info; | |
1da177e4 | 270 | |
cb4cb2cb | 271 | sn_irq_info = container_of(head, struct sn_irq_info, rcu); |
1da177e4 LT |
272 | kfree(sn_irq_info); |
273 | } | |
274 | ||
275 | void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info) | |
276 | { | |
277 | nasid_t nasid = sn_irq_info->irq_nasid; | |
278 | int slice = sn_irq_info->irq_slice; | |
279 | int cpu = nasid_slice_to_cpuid(nasid, slice); | |
280 | ||
cb4cb2cb | 281 | pci_dev_get(pci_dev); |
1da177e4 LT |
282 | sn_irq_info->irq_cpuid = cpu; |
283 | sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev); | |
284 | ||
285 | /* link it into the sn_irq[irq] list */ | |
cb4cb2cb PB |
286 | spin_lock(&sn_irq_info_lock); |
287 | list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]); | |
288 | spin_unlock(&sn_irq_info_lock); | |
1da177e4 | 289 | |
2fcc3db0 | 290 | register_intr_pda(sn_irq_info); |
1da177e4 LT |
291 | } |
292 | ||
cb4cb2cb PB |
293 | void sn_irq_unfixup(struct pci_dev *pci_dev) |
294 | { | |
295 | struct sn_irq_info *sn_irq_info; | |
296 | ||
297 | /* Only cleanup IRQ stuff if this device has a host bus context */ | |
298 | if (!SN_PCIDEV_BUSSOFT(pci_dev)) | |
299 | return; | |
300 | ||
301 | sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info; | |
6f354b01 PB |
302 | if (!sn_irq_info || !sn_irq_info->irq_irq) { |
303 | kfree(sn_irq_info); | |
cb4cb2cb | 304 | return; |
6f354b01 | 305 | } |
cb4cb2cb PB |
306 | |
307 | unregister_intr_pda(sn_irq_info); | |
308 | spin_lock(&sn_irq_info_lock); | |
309 | list_del_rcu(&sn_irq_info->list); | |
310 | spin_unlock(&sn_irq_info_lock); | |
311 | call_rcu(&sn_irq_info->rcu, sn_irq_info_free); | |
cb4cb2cb PB |
312 | pci_dev_put(pci_dev); |
313 | } | |
314 | ||
735e60f4 MM |
315 | static inline void |
316 | sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info) | |
317 | { | |
318 | struct sn_pcibus_provider *pci_provider; | |
319 | ||
320 | pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type]; | |
321 | if (pci_provider && pci_provider->force_interrupt) | |
322 | (*pci_provider->force_interrupt)(sn_irq_info); | |
323 | } | |
324 | ||
1da177e4 LT |
325 | static void force_interrupt(int irq) |
326 | { | |
327 | struct sn_irq_info *sn_irq_info; | |
328 | ||
329 | if (!sn_ioif_inited) | |
330 | return; | |
cb4cb2cb PB |
331 | |
332 | rcu_read_lock(); | |
735e60f4 MM |
333 | list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list) |
334 | sn_call_force_intr_provider(sn_irq_info); | |
335 | ||
cb4cb2cb | 336 | rcu_read_unlock(); |
1da177e4 LT |
337 | } |
338 | ||
339 | /* | |
340 | * Check for lost interrupts. If the PIC int_status reg. says that | |
341 | * an interrupt has been sent, but not handled, and the interrupt | |
342 | * is not pending in either the cpu irr regs or in the soft irr regs, | |
343 | * and the interrupt is not in service, then the interrupt may have | |
344 | * been lost. Force an interrupt on that pin. It is possible that | |
345 | * the interrupt is in flight, so we may generate a spurious interrupt, | |
346 | * but we should never miss a real lost interrupt. | |
347 | */ | |
348 | static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info) | |
349 | { | |
53493dcf | 350 | u64 regval; |
1da177e4 LT |
351 | int irr_reg_num; |
352 | int irr_bit; | |
53493dcf | 353 | u64 irr_reg; |
1da177e4 LT |
354 | struct pcidev_info *pcidev_info; |
355 | struct pcibus_info *pcibus_info; | |
356 | ||
735e60f4 MM |
357 | /* |
358 | * Bridge types attached to TIO (anything but PIC) do not need this WAR | |
359 | * since they do not target Shub II interrupt registers. If that | |
360 | * ever changes, this check needs to accomodate. | |
361 | */ | |
362 | if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC) | |
363 | return; | |
364 | ||
1da177e4 LT |
365 | pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; |
366 | if (!pcidev_info) | |
367 | return; | |
368 | ||
369 | pcibus_info = | |
370 | (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info-> | |
371 | pdi_pcibus_info; | |
372 | regval = pcireg_intr_status_get(pcibus_info); | |
373 | ||
374 | irr_reg_num = irq_to_vector(irq) / 64; | |
375 | irr_bit = irq_to_vector(irq) % 64; | |
376 | switch (irr_reg_num) { | |
377 | case 0: | |
378 | irr_reg = ia64_getreg(_IA64_REG_CR_IRR0); | |
379 | break; | |
380 | case 1: | |
381 | irr_reg = ia64_getreg(_IA64_REG_CR_IRR1); | |
382 | break; | |
383 | case 2: | |
384 | irr_reg = ia64_getreg(_IA64_REG_CR_IRR2); | |
385 | break; | |
386 | case 3: | |
387 | irr_reg = ia64_getreg(_IA64_REG_CR_IRR3); | |
388 | break; | |
389 | } | |
390 | if (!test_bit(irr_bit, &irr_reg)) { | |
735e60f4 MM |
391 | if (!test_bit(irq, pda->sn_in_service_ivecs)) { |
392 | regval &= 0xff; | |
393 | if (sn_irq_info->irq_int_bit & regval & | |
394 | sn_irq_info->irq_last_intr) { | |
395 | regval &= ~(sn_irq_info->irq_int_bit & regval); | |
396 | sn_call_force_intr_provider(sn_irq_info); | |
1da177e4 LT |
397 | } |
398 | } | |
399 | } | |
400 | sn_irq_info->irq_last_intr = regval; | |
401 | } | |
402 | ||
403 | void sn_lb_int_war_check(void) | |
404 | { | |
cb4cb2cb | 405 | struct sn_irq_info *sn_irq_info; |
1da177e4 LT |
406 | int i; |
407 | ||
408 | if (!sn_ioif_inited || pda->sn_first_irq == 0) | |
409 | return; | |
cb4cb2cb PB |
410 | |
411 | rcu_read_lock(); | |
1da177e4 | 412 | for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) { |
cb4cb2cb | 413 | list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) { |
735e60f4 | 414 | sn_check_intr(i, sn_irq_info); |
1da177e4 LT |
415 | } |
416 | } | |
cb4cb2cb PB |
417 | rcu_read_unlock(); |
418 | } | |
419 | ||
2fcc3db0 | 420 | void __init sn_irq_lh_init(void) |
cb4cb2cb PB |
421 | { |
422 | int i; | |
423 | ||
424 | sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL); | |
425 | if (!sn_irq_lh) | |
426 | panic("SN PCI INIT: Failed to allocate memory for PCI init\n"); | |
427 | ||
428 | for (i = 0; i < NR_IRQS; i++) { | |
429 | sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL); | |
430 | if (!sn_irq_lh[i]) | |
431 | panic("SN PCI INIT: Failed IRQ memory allocation\n"); | |
432 | ||
433 | INIT_LIST_HEAD(sn_irq_lh[i]); | |
434 | } | |
1da177e4 | 435 | } |